1 /****************************************************************************** 2 * Filename: hw_ddi_0_osc_h 3 * Revised: 2019-03-08 14:23:17 +0100 (Fri, 08 Mar 2019) 4 * Revision: 55206 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_DDI_0_OSC_H__ 38 #define __HW_DDI_0_OSC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // DDI_0_OSC component 44 // 45 //***************************************************************************** 46 // Control 0 47 #define DDI_0_OSC_O_CTL0 0x00000000 48 49 // Control 1 50 #define DDI_0_OSC_O_CTL1 0x00000004 51 52 // RADC External Configuration 53 #define DDI_0_OSC_O_RADCEXTCFG 0x00000008 54 55 // Amplitude Compensation Control 56 #define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C 57 58 // Amplitude Compensation Threshold 1 59 #define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 60 61 // Amplitude Compensation Threshold 2 62 #define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 63 64 // Analog Bypass Values 1 65 #define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 66 67 // Internal 68 #define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C 69 70 // Analog Test Control 71 #define DDI_0_OSC_O_ATESTCTL 0x00000020 72 73 // ADC Doubler Nanoamp Control 74 #define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 75 76 // XOSCHF Control 77 #define DDI_0_OSC_O_XOSCHFCTL 0x00000028 78 79 // Low Frequency Oscillator Control 80 #define DDI_0_OSC_O_LFOSCCTL 0x0000002C 81 82 // RCOSCHF Control 83 #define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 84 85 // RCOSC_MF Control 86 #define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 87 88 // Status 0 89 #define DDI_0_OSC_O_STAT0 0x0000003C 90 91 // Status 1 92 #define DDI_0_OSC_O_STAT1 0x00000040 93 94 // Status 2 95 #define DDI_0_OSC_O_STAT2 0x00000044 96 97 //***************************************************************************** 98 // 99 // Register: DDI_0_OSC_O_CTL0 100 // 101 //***************************************************************************** 102 // Field: [31] XTAL_IS_24M 103 // 104 // Set based on the accurate high frequency XTAL. 105 // ENUMs: 106 // 24M Internal. Only to be used through TI provided API. 107 // 48M Internal. Only to be used through TI provided API. 108 #define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 109 #define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 110 #define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 111 #define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 112 #define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 113 114 // Field: [29] BYPASS_XOSC_LF_CLK_QUAL 115 // 116 // Internal. Only to be used through TI provided API. 117 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 118 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 119 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 120 121 // Field: [28] BYPASS_RCOSC_LF_CLK_QUAL 122 // 123 // Internal. Only to be used through TI provided API. 124 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 125 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 126 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 127 128 // Field: [27:26] DOUBLER_START_DURATION 129 // 130 // Internal. Only to be used through TI provided API. 131 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 132 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 133 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 134 135 // Field: [25] DOUBLER_RESET_DURATION 136 // 137 // Internal. Only to be used through TI provided API. 138 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 139 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 140 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 141 142 // Field: [24] CLK_DCDC_SRC_SEL 143 // 144 // Select DCDC clock source. 145 // 146 // 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC 147 // 1: CLK_DCDC is always 48 MHz clock from RCOSC 148 #define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 149 #define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 150 #define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 151 152 // Field: [14] HPOSC_MODE_EN 153 // 154 // 0: HPOSC mode is not enabled. The 48 MHz crystal is required for radio 155 // operation. 156 // 1: Enables HPOSC mode. The internal HPOSC can be used as HF system clock and 157 // for radio operation. 158 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 159 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 160 #define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 161 162 // Field: [12] RCOSC_LF_TRIMMED 163 // 164 // Internal. Only to be used through TI provided API. 165 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 166 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 167 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 168 169 // Field: [11] XOSC_HF_POWER_MODE 170 // 171 // Internal. Only to be used through TI provided API. 172 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 173 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 174 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 175 176 // Field: [10] XOSC_LF_DIG_BYPASS 177 // 178 // Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf 179 // clock. 180 // 181 // 0: Use 32kHz XOSC as xosc_lf clock source 182 // 1: Use digital input (from AON) as xosc_lf clock source. 183 // 184 // This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf 185 // as the sclk_lf source. The muxing performed by this bit is not glitch free. 186 // The following procedure must be followed when changing this field to avoid 187 // glitches on sclk_lf. 188 // 189 // 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock 190 // source. 191 // 2) Set or clear this bit to bypass or not bypass the xosc_lf. 192 // 3) Set SCLK_LF_SRC_SEL to use xosc_lf. 193 // 194 // It is recommended that either the rcosc_hf or xosc_hf (whichever is 195 // currently active) be selected as the source in step 1 above. This provides a 196 // faster clock change. 197 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 198 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 199 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 200 201 // Field: [9] CLK_LOSS_EN 202 // 203 // Enable clock loss detection and hence the indicators to the system 204 // controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. 205 // 206 // 0: Disable 207 // 1: Enable 208 // 209 // Clock loss detection must be disabled when changing the sclk_lf source. 210 // STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf 211 // source has completed. 212 #define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 213 #define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 214 #define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 215 216 // Field: [8:7] ACLK_TDC_SRC_SEL 217 // 218 // Source select for aclk_tdc. 219 // 220 // 00: RCOSC_HF (48MHz) 221 // 01: RCOSC_HF (24MHz) 222 // 10: XOSC_HF (24MHz) 223 // 11: Not used 224 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 225 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 226 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 227 228 // Field: [6:4] ACLK_REF_SRC_SEL 229 // 230 // Source select for aclk_ref 231 // 232 // 000: RCOSC_HF derived (31.25kHz) 233 // 001: XOSC_HF derived (31.25kHz) 234 // 010: RCOSC_LF (32kHz) 235 // 011: XOSC_LF (32.768kHz) 236 // 100: RCOSC_MF (2MHz) 237 // 101-111: Not used 238 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 239 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 240 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 241 242 // Field: [3:2] SCLK_LF_SRC_SEL 243 // 244 // Source select for sclk_lf 245 // ENUMs: 246 // XOSCLF Low frequency XOSC 247 // RCOSCLF Low frequency RCOSC 248 // XOSCHFDLF Low frequency clock derived from High Frequency 249 // XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN 250 // = 1) 251 // RCOSCHFDLF Low frequency clock derived from High Frequency 252 // RCOSC 253 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 254 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C 255 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 256 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C 257 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 258 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 259 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 260 261 // Field: [0] SCLK_HF_SRC_SEL 262 // 263 // Source select for sclk_hf. 264 // ENUMs: 265 // XOSC High frequency XOSC or HPOSC clk (use HPOSC when 266 // HPOSC_MODE_EN = 1 267 // RCOSC High frequency RCOSC clock 268 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 269 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 270 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 271 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 272 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 273 274 //***************************************************************************** 275 // 276 // Register: DDI_0_OSC_O_CTL1 277 // 278 //***************************************************************************** 279 // Field: [22:18] RCOSCHFCTRIMFRACT 280 // 281 // Internal. Only to be used through TI provided API. 282 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 283 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 284 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 285 286 // Field: [17] RCOSCHFCTRIMFRACT_EN 287 // 288 // Internal. Only to be used through TI provided API. 289 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 290 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 291 #define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 292 293 // Field: [1:0] XOSC_HF_FAST_START 294 // 295 // Internal. Only to be used through TI provided API. 296 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 297 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 298 #define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 299 300 //***************************************************************************** 301 // 302 // Register: DDI_0_OSC_O_RADCEXTCFG 303 // 304 //***************************************************************************** 305 // Field: [31:22] HPM_IBIAS_WAIT_CNT 306 // 307 // Internal. Only to be used through TI provided API. 308 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 309 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 310 #define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 311 312 // Field: [21:16] LPM_IBIAS_WAIT_CNT 313 // 314 // Internal. Only to be used through TI provided API. 315 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 316 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 317 #define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 318 319 // Field: [15:12] IDAC_STEP 320 // 321 // Internal. Only to be used through TI provided API. 322 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 323 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 324 #define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 325 326 // Field: [11:6] RADC_DAC_TH 327 // 328 // Internal. Only to be used through TI provided API. 329 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 330 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 331 #define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 332 333 // Field: [5] RADC_MODE_IS_SAR 334 // 335 // Internal. Only to be used through TI provided API. 336 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 337 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 338 #define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 339 340 //***************************************************************************** 341 // 342 // Register: DDI_0_OSC_O_AMPCOMPCTL 343 // 344 //***************************************************************************** 345 // Field: [30] AMPCOMP_REQ_MODE 346 // 347 // Internal. Only to be used through TI provided API. 348 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 349 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 350 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 351 352 // Field: [29:28] AMPCOMP_FSM_UPDATE_RATE 353 // 354 // Internal. Only to be used through TI provided API. 355 // ENUMs: 356 // 250KHZ Internal. Only to be used through TI provided API. 357 // 500KHZ Internal. Only to be used through TI provided API. 358 // 1MHZ Internal. Only to be used through TI provided API. 359 // 2MHZ Internal. Only to be used through TI provided API. 360 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 361 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 362 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 363 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 364 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 365 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 366 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 367 368 // Field: [27] AMPCOMP_SW_CTRL 369 // 370 // Internal. Only to be used through TI provided API. 371 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 372 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 373 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 374 375 // Field: [26] AMPCOMP_SW_EN 376 // 377 // Internal. Only to be used through TI provided API. 378 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 379 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 380 #define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 381 382 // Field: [23:20] IBIAS_OFFSET 383 // 384 // Internal. Only to be used through TI provided API. 385 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 386 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 387 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 388 389 // Field: [19:16] IBIAS_INIT 390 // 391 // Internal. Only to be used through TI provided API. 392 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 393 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 394 #define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 395 396 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL 397 // 398 // Internal. Only to be used through TI provided API. 399 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 400 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 401 #define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 402 403 // Field: [7:4] CAP_STEP 404 // 405 // Internal. Only to be used through TI provided API. 406 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 407 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 408 #define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 409 410 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT 411 // 412 // Internal. Only to be used through TI provided API. 413 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 414 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F 415 #define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 416 417 //***************************************************************************** 418 // 419 // Register: DDI_0_OSC_O_AMPCOMPTH1 420 // 421 //***************************************************************************** 422 // Field: [23:18] HPMRAMP3_LTH 423 // 424 // Internal. Only to be used through TI provided API. 425 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 426 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 427 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 428 429 // Field: [15:10] HPMRAMP3_HTH 430 // 431 // Internal. Only to be used through TI provided API. 432 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 433 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 434 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 435 436 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT 437 // 438 // Internal. Only to be used through TI provided API. 439 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 440 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 441 #define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 442 443 // Field: [5:0] HPMRAMP1_TH 444 // 445 // Internal. Only to be used through TI provided API. 446 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 447 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F 448 #define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 449 450 //***************************************************************************** 451 // 452 // Register: DDI_0_OSC_O_AMPCOMPTH2 453 // 454 //***************************************************************************** 455 // Field: [31:26] LPMUPDATE_LTH 456 // 457 // Internal. Only to be used through TI provided API. 458 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 459 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 460 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 461 462 // Field: [23:18] LPMUPDATE_HTH 463 // 464 // Internal. Only to be used through TI provided API. 465 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 466 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 467 #define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 468 469 // Field: [15:10] ADC_COMP_AMPTH_LPM 470 // 471 // Internal. Only to be used through TI provided API. 472 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 473 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 474 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 475 476 // Field: [7:2] ADC_COMP_AMPTH_HPM 477 // 478 // Internal. Only to be used through TI provided API. 479 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 480 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC 481 #define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 482 483 //***************************************************************************** 484 // 485 // Register: DDI_0_OSC_O_ANABYPASSVAL1 486 // 487 //***************************************************************************** 488 // Field: [19:16] XOSC_HF_ROW_Q12 489 // 490 // Internal. Only to be used through TI provided API. 491 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 492 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 493 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 494 495 // Field: [15:0] XOSC_HF_COLUMN_Q12 496 // 497 // Internal. Only to be used through TI provided API. 498 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 499 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF 500 #define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 501 502 //***************************************************************************** 503 // 504 // Register: DDI_0_OSC_O_ANABYPASSVAL2 505 // 506 //***************************************************************************** 507 // Field: [13:0] XOSC_HF_IBIASTHERM 508 // 509 // Internal. Only to be used through TI provided API. 510 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 511 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF 512 #define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 513 514 //***************************************************************************** 515 // 516 // Register: DDI_0_OSC_O_ATESTCTL 517 // 518 //***************************************************************************** 519 // Field: [31] SCLK_LF_AUX_EN 520 // 521 // Enable 32 kHz clock to AUX_COMPB. 522 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 523 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 524 #define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 525 526 // Field: [15:14] TEST_RCOSCMF 527 // 528 // Test mode control for RCOSC_MF 529 // 530 // 0x0: test modes disabled 531 // 0x1: boosted bias current into self biased inverter 532 // 0x2: clock qualification disabled 533 // 0x3: boosted bias current into self biased inverter + clock qualification 534 // disabled 535 #define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 536 #define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 537 #define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 538 539 // Field: [13:12] ATEST_RCOSCMF 540 // 541 // ATEST control for RCOSC_MF 542 // 543 // 0x0: ATEST disabled 544 // 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* 545 // enabled to send out 2MHz clock. 546 // 0x2: ATEST disabled 547 // 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* 548 // enabled to send out 2MHz clock. 549 #define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 550 #define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 551 #define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 552 553 //***************************************************************************** 554 // 555 // Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 556 // 557 //***************************************************************************** 558 // Field: [24] NANOAMP_BIAS_ENABLE 559 // 560 // Internal. Only to be used through TI provided API. 561 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 562 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 563 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 564 565 // Field: [23] SPARE23 566 // 567 // Software should not rely on the value of a reserved. Writing any other value 568 // than the reset value may result in undefined behavior 569 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 570 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 571 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 572 573 // Field: [5] ADC_SH_MODE_EN 574 // 575 // Internal. Only to be used through TI provided API. 576 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 577 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 578 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 579 580 // Field: [4] ADC_SH_VBUF_EN 581 // 582 // Internal. Only to be used through TI provided API. 583 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 584 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 585 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 586 587 // Field: [1:0] ADC_IREF_CTRL 588 // 589 // Internal. Only to be used through TI provided API. 590 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 591 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 592 #define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 593 594 //***************************************************************************** 595 // 596 // Register: DDI_0_OSC_O_XOSCHFCTL 597 // 598 //***************************************************************************** 599 // Field: [13] TCXO_MODE_XOSC_HF_EN 600 // 601 // If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, 602 // turning on the XOSC_HF bias current allowing a DC bias point to be provided 603 // to the clipped-sine wave clock signal on external input. 604 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 605 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 606 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 607 608 // Field: [12] TCXO_MODE 609 // 610 // If this register is 1 when BYPASS is 1, this will enable clock 611 // qualification on the TCXO clock on external input. This register has no 612 // effect when BYPASS is 0. 613 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 614 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 615 #define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 616 617 // Field: [9:8] PEAK_DET_ITRIM 618 // 619 // Internal. Only to be used through TI provided API. 620 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 621 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 622 #define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 623 624 // Field: [6] BYPASS 625 // 626 // Internal. Only to be used through TI provided API. 627 #define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 628 #define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 629 #define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 630 631 // Field: [4:2] HP_BUF_ITRIM 632 // 633 // Internal. Only to be used through TI provided API. 634 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 635 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C 636 #define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 637 638 // Field: [1:0] LP_BUF_ITRIM 639 // 640 // Internal. Only to be used through TI provided API. 641 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 642 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 643 #define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 644 645 //***************************************************************************** 646 // 647 // Register: DDI_0_OSC_O_LFOSCCTL 648 // 649 //***************************************************************************** 650 // Field: [23:22] XOSCLF_REGULATOR_TRIM 651 // 652 // Internal. Only to be used through TI provided API. 653 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 654 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 655 #define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 656 657 // Field: [21:18] XOSCLF_CMIRRWR_RATIO 658 // 659 // Internal. Only to be used through TI provided API. 660 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 661 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 662 #define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 663 664 // Field: [9:8] RCOSCLF_RTUNE_TRIM 665 // 666 // Internal. Only to be used through TI provided API. 667 // ENUMs: 668 // 6P0MEG Internal. Only to be used through TI provided API. 669 // 6P5MEG Internal. Only to be used through TI provided API. 670 // 7P0MEG Internal. Only to be used through TI provided API. 671 // 7P5MEG Internal. Only to be used through TI provided API. 672 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 673 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 674 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 675 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 676 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 677 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 678 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 679 680 // Field: [7:0] RCOSCLF_CTUNE_TRIM 681 // 682 // Internal. Only to be used through TI provided API. 683 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 684 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF 685 #define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 686 687 //***************************************************************************** 688 // 689 // Register: DDI_0_OSC_O_RCOSCHFCTL 690 // 691 //***************************************************************************** 692 // Field: [15:8] RCOSCHF_CTRIM 693 // 694 // Internal. Only to be used through TI provided API. 695 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 696 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 697 #define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 698 699 //***************************************************************************** 700 // 701 // Register: DDI_0_OSC_O_RCOSCMFCTL 702 // 703 //***************************************************************************** 704 // Field: [15:9] RCOSC_MF_CAP_ARRAY 705 // 706 // Adjust RCOSC_MF capacitor array. 707 // 708 // 0x0: nominal frequency, 0.625pF 709 // 0x40: highest frequency, 0.125pF 710 // 0x3F: lowest frequency, 1.125pF 711 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 712 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 713 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 714 715 // Field: [8] RCOSC_MF_REG_SEL 716 // 717 // Choose regulator type. 718 // 719 // 0: default 720 // 1: alternate 721 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 722 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 723 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 724 725 // Field: [7:6] RCOSC_MF_RES_COARSE 726 // 727 // Select coarse resistor for frequency adjustment. 728 // 729 // 0x0: 400kohms, default 730 // 0x1: 300kohms, min 731 // 0x2: 600kohms, max 732 // 0x3: 500kohms 733 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 734 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 735 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 736 737 // Field: [5:4] RCOSC_MF_RES_FINE 738 // 739 // Select fine resistor for frequency adjustment. 740 // 741 // 0x0: 11kohms, minimum resistance, max freq 742 // 0x1: 13kohms 743 // 0x2: 16kohms 744 // 0x3: 20kohms, max resistance, min freq 745 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 746 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 747 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 748 749 // Field: [3:0] RCOSC_MF_BIAS_ADJ 750 // 751 // Adjusts bias current to RCOSC_MF. 752 // 753 // 0x8 minimum current 754 // 0x0 default current 755 // 0x7 maximum current 756 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 757 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F 758 #define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 759 760 //***************************************************************************** 761 // 762 // Register: DDI_0_OSC_O_STAT0 763 // 764 //***************************************************************************** 765 // Field: [30:29] SCLK_LF_SRC 766 // 767 // Indicates source for the sclk_lf 768 // ENUMs: 769 // XOSCLF Low frequency XOSC 770 // RCOSCLF Low frequency RCOSC 771 // XOSCHFDLF Low frequency clock derived from High Frequency 772 // XOSC 773 // RCOSCHFDLF Low frequency clock derived from High Frequency 774 // RCOSC 775 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 776 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 777 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 778 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 779 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 780 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 781 #define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 782 783 // Field: [28] SCLK_HF_SRC 784 // 785 // Indicates source for the sclk_hf 786 // ENUMs: 787 // XOSC High frequency XOSC 788 // RCOSC High frequency RCOSC clock 789 #define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 790 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 791 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 792 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 793 #define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 794 795 // Field: [22] RCOSC_HF_EN 796 // 797 // RCOSC_HF_EN 798 #define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 799 #define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 800 #define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 801 802 // Field: [21] RCOSC_LF_EN 803 // 804 // RCOSC_LF_EN 805 #define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 806 #define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 807 #define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 808 809 // Field: [20] XOSC_LF_EN 810 // 811 // XOSC_LF_EN 812 #define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 813 #define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 814 #define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 815 816 // Field: [19] CLK_DCDC_RDY 817 // 818 // CLK_DCDC_RDY 819 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 820 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 821 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 822 823 // Field: [18] CLK_DCDC_RDY_ACK 824 // 825 // CLK_DCDC_RDY_ACK 826 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 827 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 828 #define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 829 830 // Field: [17] SCLK_HF_LOSS 831 // 832 // Indicates sclk_hf is lost 833 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 834 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 835 #define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 836 837 // Field: [16] SCLK_LF_LOSS 838 // 839 // Indicates sclk_lf is lost 840 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 841 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 842 #define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 843 844 // Field: [15] XOSC_HF_EN 845 // 846 // Indicates that XOSC_HF is enabled. 847 #define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 848 #define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 849 #define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 850 851 // Field: [13] XB_48M_CLK_EN 852 // 853 // Indicates that the 48MHz clock from the DOUBLER is enabled. 854 // 855 // It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler 856 // bypass for the 48MHz crystal). 857 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 858 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 859 #define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 860 861 // Field: [11] XOSC_HF_LP_BUF_EN 862 // 863 // XOSC_HF_LP_BUF_EN 864 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 865 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 866 #define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 867 868 // Field: [10] XOSC_HF_HP_BUF_EN 869 // 870 // XOSC_HF_HP_BUF_EN 871 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 872 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 873 #define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 874 875 // Field: [8] ADC_THMET 876 // 877 // ADC_THMET 878 #define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 879 #define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 880 #define DDI_0_OSC_STAT0_ADC_THMET_S 8 881 882 // Field: [7] ADC_DATA_READY 883 // 884 // indicates when adc_data is ready. 885 #define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 886 #define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 887 #define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 888 889 // Field: [6:1] ADC_DATA 890 // 891 // adc_data 892 #define DDI_0_OSC_STAT0_ADC_DATA_W 6 893 #define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E 894 #define DDI_0_OSC_STAT0_ADC_DATA_S 1 895 896 // Field: [0] PENDINGSCLKHFSWITCHING 897 // 898 // Indicates when SCLK_HF clock source is ready to be switched 899 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 900 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 901 #define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 902 903 //***************************************************************************** 904 // 905 // Register: DDI_0_OSC_O_STAT1 906 // 907 //***************************************************************************** 908 // Field: [31:28] RAMPSTATE 909 // 910 // AMPCOMP FSM State 911 // ENUMs: 912 // FAST_START_SETTLE FAST_START_SETTLE 913 // FAST_START FAST_START 914 // DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 915 // IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE 916 // IBIAS_INC IBIAS_INCREMENT 917 // LPM_UPDATE LPM_UPDATE 918 // IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE 919 // IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE 920 // IDAC_INCREMENT IDAC_INCREMENT 921 // HPM_UPDATE HPM_UPDATE 922 // HPM_RAMP3 HPM_RAMP3 923 // HPM_RAMP2 HPM_RAMP2 924 // HPM_RAMP1 HPM_RAMP1 925 // INITIALIZATION INITIALIZATION 926 // RESET RESET 927 #define DDI_0_OSC_STAT1_RAMPSTATE_W 4 928 #define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 929 #define DDI_0_OSC_STAT1_RAMPSTATE_S 28 930 #define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 931 #define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 932 #define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 933 #define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 934 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 935 #define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 936 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 937 #define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 938 #define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 939 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 940 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 941 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 942 #define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 943 #define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 944 #define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 945 946 // Field: [27:22] HPM_UPDATE_AMP 947 // 948 // XOSC_HF amplitude during HPM_UPDATE state. 949 // When amplitude compensation of XOSC_HF is enabled in high performance mode, 950 // this value is the amplitude of the crystal oscillations measured by the 951 // on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 952 // would indicate that the amplitude of the crystal is approximately 480 mV. 953 // To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero 954 // value. 955 #define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 956 #define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 957 #define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 958 959 // Field: [21:16] LPM_UPDATE_AMP 960 // 961 // XOSC_HF amplitude during LPM_UPDATE state 962 // When amplitude compensation of XOSC_HF is enabled in low power mode, this 963 // value is the amplitude of the crystal oscillations measured by the on-chip 964 // oscillator ADC, divided by 15 mV. For example, a value of 0x20 would 965 // indicate that the amplitude of the crystal is approximately 480 mV. To 966 // enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero 967 // value. 968 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 969 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 970 #define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 971 972 // Field: [15] FORCE_RCOSC_HF 973 // 974 // force_rcosc_hf 975 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 976 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 977 #define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 978 979 // Field: [14] SCLK_HF_EN 980 // 981 // SCLK_HF_EN 982 #define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 983 #define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 984 #define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 985 986 // Field: [13] SCLK_MF_EN 987 // 988 // SCLK_MF_EN 989 #define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 990 #define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 991 #define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 992 993 // Field: [12] ACLK_ADC_EN 994 // 995 // ACLK_ADC_EN 996 #define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 997 #define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 998 #define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 999 1000 // Field: [11] ACLK_TDC_EN 1001 // 1002 // ACLK_TDC_EN 1003 #define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 1004 #define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 1005 #define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 1006 1007 // Field: [10] ACLK_REF_EN 1008 // 1009 // ACLK_REF_EN 1010 #define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 1011 #define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 1012 #define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 1013 1014 // Field: [9] CLK_CHP_EN 1015 // 1016 // CLK_CHP_EN 1017 #define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 1018 #define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 1019 #define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 1020 1021 // Field: [8] CLK_DCDC_EN 1022 // 1023 // CLK_DCDC_EN 1024 #define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 1025 #define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 1026 #define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 1027 1028 // Field: [7] SCLK_HF_GOOD 1029 // 1030 // SCLK_HF_GOOD 1031 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 1032 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 1033 #define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 1034 1035 // Field: [6] SCLK_MF_GOOD 1036 // 1037 // SCLK_MF_GOOD 1038 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 1039 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 1040 #define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 1041 1042 // Field: [5] SCLK_LF_GOOD 1043 // 1044 // SCLK_LF_GOOD 1045 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 1046 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 1047 #define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 1048 1049 // Field: [4] ACLK_ADC_GOOD 1050 // 1051 // ACLK_ADC_GOOD 1052 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 1053 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 1054 #define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 1055 1056 // Field: [3] ACLK_TDC_GOOD 1057 // 1058 // ACLK_TDC_GOOD 1059 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 1060 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 1061 #define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 1062 1063 // Field: [2] ACLK_REF_GOOD 1064 // 1065 // ACLK_REF_GOOD. 1066 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 1067 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 1068 #define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 1069 1070 // Field: [1] CLK_CHP_GOOD 1071 // 1072 // CLK_CHP_GOOD 1073 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 1074 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 1075 #define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 1076 1077 // Field: [0] CLK_DCDC_GOOD 1078 // 1079 // CLK_DCDC_GOOD 1080 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 1081 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 1082 #define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 1083 1084 //***************************************************************************** 1085 // 1086 // Register: DDI_0_OSC_O_STAT2 1087 // 1088 //***************************************************************************** 1089 // Field: [31:26] ADC_DCBIAS 1090 // 1091 // DC Bias read by RADC during SAR mode 1092 // The value is an unsigned integer. It is used for debug only. 1093 #define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 1094 #define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 1095 #define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 1096 1097 // Field: [25] HPM_RAMP1_THMET 1098 // 1099 // Indication of threshold is met for hpm_ramp1 1100 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 1101 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 1102 #define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 1103 1104 // Field: [24] HPM_RAMP2_THMET 1105 // 1106 // Indication of threshold is met for hpm_ramp2 1107 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 1108 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 1109 #define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 1110 1111 // Field: [23] HPM_RAMP3_THMET 1112 // 1113 // Indication of threshold is met for hpm_ramp3 1114 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 1115 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 1116 #define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 1117 1118 // Field: [15:12] RAMPSTATE 1119 // 1120 // xosc_hf amplitude compensation FSM 1121 // 1122 // This is identical to STAT1.RAMPSTATE. See that description for encoding. 1123 #define DDI_0_OSC_STAT2_RAMPSTATE_W 4 1124 #define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 1125 #define DDI_0_OSC_STAT2_RAMPSTATE_S 12 1126 1127 // Field: [3] AMPCOMP_REQ 1128 // 1129 // ampcomp_req 1130 #define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 1131 #define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 1132 #define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 1133 1134 // Field: [2] XOSC_HF_AMPGOOD 1135 // 1136 // amplitude of xosc_hf is within the required threshold (set by DDI). Not used 1137 // for anything just for debug/status 1138 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 1139 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 1140 #define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 1141 1142 // Field: [1] XOSC_HF_FREQGOOD 1143 // 1144 // frequency of xosc_hf is good to use for the digital clocks 1145 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 1146 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 1147 #define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 1148 1149 // Field: [0] XOSC_HF_RF_FREQGOOD 1150 // 1151 // frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio 1152 // operations. Used for SW to start synthesizer. 1153 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 1154 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 1155 #define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 1156 1157 1158 #endif // __DDI_0_OSC__ 1159
