1 /****************************************************************************** 2 * Filename: hw_crypto_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CRYPTO_H__ 38 #define __HW_CRYPTO_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CRYPTO component 44 // 45 //***************************************************************************** 46 // Channel 0 Control 47 #define CRYPTO_O_DMACH0CTL 0x00000000 48 49 // Channel 0 External Address 50 #define CRYPTO_O_DMACH0EXTADDR 0x00000004 51 52 // Channel 0 DMA Length 53 #define CRYPTO_O_DMACH0LEN 0x0000000C 54 55 // DMAC Status 56 #define CRYPTO_O_DMASTAT 0x00000018 57 58 // DMAC Software Reset 59 #define CRYPTO_O_DMASWRESET 0x0000001C 60 61 // Channel 1 Control 62 #define CRYPTO_O_DMACH1CTL 0x00000020 63 64 // Channel 1 External Address 65 #define CRYPTO_O_DMACH1EXTADDR 0x00000024 66 67 // Channel 1 DMA Length 68 #define CRYPTO_O_DMACH1LEN 0x0000002C 69 70 // DMAC Master Run-time Parameters 71 #define CRYPTO_O_DMABUSCFG 0x00000078 72 73 // DMAC Port Error Raw Status 74 #define CRYPTO_O_DMAPORTERR 0x0000007C 75 76 // DMAC Version 77 #define CRYPTO_O_DMAHWVER 0x000000FC 78 79 // Key Store Write Area 80 #define CRYPTO_O_KEYWRITEAREA 0x00000400 81 82 // Key Store Written Area 83 #define CRYPTO_O_KEYWRITTENAREA 0x00000404 84 85 // Key Store Size 86 #define CRYPTO_O_KEYSIZE 0x00000408 87 88 // Key Store Read Area 89 #define CRYPTO_O_KEYREADAREA 0x0000040C 90 91 // AES_KEY2_0 / AES_GHASH_H_IN_0 92 #define CRYPTO_O_AESKEY20 0x00000500 93 94 // AES_KEY2_0 / AES_GHASH_H_IN_0 95 #define CRYPTO_O_AESKEY21 0x00000504 96 97 // AES_KEY2_0 / AES_GHASH_H_IN_0 98 #define CRYPTO_O_AESKEY22 0x00000508 99 100 // AES_KEY2_0 / AES_GHASH_H_IN_0 101 #define CRYPTO_O_AESKEY23 0x0000050C 102 103 // AES_KEY3_0 / AES_KEY2_4 104 #define CRYPTO_O_AESKEY30 0x00000510 105 106 // AES_KEY3_0 / AES_KEY2_4 107 #define CRYPTO_O_AESKEY31 0x00000514 108 109 // AES_KEY3_0 / AES_KEY2_4 110 #define CRYPTO_O_AESKEY32 0x00000518 111 112 // AES_KEY3_0 / AES_KEY2_4 113 #define CRYPTO_O_AESKEY33 0x0000051C 114 115 // AES initialization vector registers 116 #define CRYPTO_O_AESIV0 0x00000540 117 118 // AES initialization vector registers 119 #define CRYPTO_O_AESIV1 0x00000544 120 121 // AES initialization vector registers 122 #define CRYPTO_O_AESIV2 0x00000548 123 124 // AES initialization vector registers 125 #define CRYPTO_O_AESIV3 0x0000054C 126 127 // AES Control 128 #define CRYPTO_O_AESCTL 0x00000550 129 130 // AES Crypto Length 0 (LSW) 131 #define CRYPTO_O_AESDATALEN0 0x00000554 132 133 // AES Crypto Length 1 (MSW) 134 #define CRYPTO_O_AESDATALEN1 0x00000558 135 136 // AES Authentication Length 137 #define CRYPTO_O_AESAUTHLEN 0x0000055C 138 139 // Data Input/Output 140 #define CRYPTO_O_AESDATAOUT0 0x00000560 141 142 // AES Data Input_Output 0 143 #define CRYPTO_O_AESDATAIN0 0x00000560 144 145 // Data Input/Output 146 #define CRYPTO_O_AESDATAOUT1 0x00000564 147 148 // AES Data Input_Output 0 149 #define CRYPTO_O_AESDATAIN1 0x00000564 150 151 // Data Input/Output 152 #define CRYPTO_O_AESDATAOUT2 0x00000568 153 154 // AES Data Input_Output 2 155 #define CRYPTO_O_AESDATAIN2 0x00000568 156 157 // Data Input/Output 158 #define CRYPTO_O_AESDATAOUT3 0x0000056C 159 160 // AES Data Input_Output 3 161 #define CRYPTO_O_AESDATAIN3 0x0000056C 162 163 // AES Tag Out 0 164 #define CRYPTO_O_AESTAGOUT0 0x00000570 165 166 // AES Tag Out 0 167 #define CRYPTO_O_AESTAGOUT1 0x00000574 168 169 // AES Tag Out 0 170 #define CRYPTO_O_AESTAGOUT2 0x00000578 171 172 // AES Tag Out 0 173 #define CRYPTO_O_AESTAGOUT3 0x0000057C 174 175 // HASH Data Input 1 176 #define CRYPTO_O_HASHDATAIN1 0x00000604 177 178 // HASH Data Input 2 179 #define CRYPTO_O_HASHDATAIN2 0x00000608 180 181 // HASH Data Input 3 182 #define CRYPTO_O_HASHDATAIN3 0x0000060C 183 184 // HASH Data Input 4 185 #define CRYPTO_O_HASHDATAIN4 0x00000610 186 187 // HASH Data Input 5 188 #define CRYPTO_O_HASHDATAIN5 0x00000614 189 190 // HASH Data Input 6 191 #define CRYPTO_O_HASHDATAIN6 0x00000618 192 193 // HASH Data Input 7 194 #define CRYPTO_O_HASHDATAIN7 0x0000061C 195 196 // HASH Data Input 8 197 #define CRYPTO_O_HASHDATAIN8 0x00000620 198 199 // HASH Data Input 9 200 #define CRYPTO_O_HASHDATAIN9 0x00000624 201 202 // HASH Data Input 10 203 #define CRYPTO_O_HASHDATAIN10 0x00000628 204 205 // HASH Data Input 11 206 #define CRYPTO_O_HASHDATAIN11 0x0000062C 207 208 // HASH Data Input 12 209 #define CRYPTO_O_HASHDATAIN12 0x00000630 210 211 // HASH Data Input 13 212 #define CRYPTO_O_HASHDATAIN13 0x00000634 213 214 // HASH Data Input 14 215 #define CRYPTO_O_HASHDATAIN14 0x00000638 216 217 // HASH Data Input 15 218 #define CRYPTO_O_HASHDATAIN15 0x0000063C 219 220 // HASH Data Input 16 221 #define CRYPTO_O_HASHDATAIN16 0x00000640 222 223 // HASH Data Input 17 224 #define CRYPTO_O_HASHDATAIN17 0x00000644 225 226 // HASH Data Input 18 227 #define CRYPTO_O_HASHDATAIN18 0x00000648 228 229 // HASH Data Input 19 230 #define CRYPTO_O_HASHDATAIN19 0x0000064C 231 232 // HASH Data Input 20 233 #define CRYPTO_O_HASHDATAIN20 0x00000650 234 235 // HASH Data Input 21 236 #define CRYPTO_O_HASHDATAIN21 0x00000654 237 238 // HASH Data Input 22 239 #define CRYPTO_O_HASHDATAIN22 0x00000658 240 241 // HASH Data Input 23 242 #define CRYPTO_O_HASHDATAIN23 0x0000065C 243 244 // HASH Data Input 24 245 #define CRYPTO_O_HASHDATAIN24 0x00000660 246 247 // HASH Data Input 25 248 #define CRYPTO_O_HASHDATAIN25 0x00000664 249 250 // HASH Data Input 26 251 #define CRYPTO_O_HASHDATAIN26 0x00000668 252 253 // HASH Data Input 27 254 #define CRYPTO_O_HASHDATAIN27 0x0000066C 255 256 // HASH Data Input 28 257 #define CRYPTO_O_HASHDATAIN28 0x00000670 258 259 // HASH Data Input 29 260 #define CRYPTO_O_HASHDATAIN29 0x00000674 261 262 // HASH Data Input 30 263 #define CRYPTO_O_HASHDATAIN30 0x00000678 264 265 // HASH Data Input 31 266 #define CRYPTO_O_HASHDATAIN31 0x0000067C 267 268 // HASH Input_Output Buffer Control 269 #define CRYPTO_O_HASHIOBUFCTRL 0x00000680 270 271 // HASH Mode 272 #define CRYPTO_O_HASHMODE 0x00000684 273 274 // HASH Input Length LSB 275 #define CRYPTO_O_HASHINLENL 0x00000688 276 277 // HASH Input Length MSB 278 #define CRYPTO_O_HASHINLENH 0x0000068C 279 280 // HASH Digest A 281 #define CRYPTO_O_HASHDIGESTA 0x000006C0 282 283 // HASH Digest B 284 #define CRYPTO_O_HASHDIGESTB 0x000006C4 285 286 // HASH Digest C 287 #define CRYPTO_O_HASHDIGESTC 0x000006C8 288 289 // HASH Digest D 290 #define CRYPTO_O_HASHDIGESTD 0x000006CC 291 292 // HASH Digest E 293 #define CRYPTO_O_HASHDIGESTE 0x000006D0 294 295 // HASH Digest F 296 #define CRYPTO_O_HASHDIGESTF 0x000006D4 297 298 // HASH Digest G 299 #define CRYPTO_O_HASHDIGESTG 0x000006D8 300 301 // HASH Digest H 302 #define CRYPTO_O_HASHDIGESTH 0x000006DC 303 304 // HASH Digest I 305 #define CRYPTO_O_HASHDIGESTI 0x000006E0 306 307 // HASH Digest J 308 #define CRYPTO_O_HASHDIGESTJ 0x000006E4 309 310 // HASH Digest K 311 #define CRYPTO_O_HASHDIGESTK 0x000006E8 312 313 // HASH Digest L 314 #define CRYPTO_O_HASHDIGESTL 0x000006EC 315 316 // HASH Digest M 317 #define CRYPTO_O_HASHDIGESTM 0x000006F0 318 319 // HASH Digest N 320 #define CRYPTO_O_HASHDIGESTN 0x000006F4 321 322 // HASH Digest 0 323 #define CRYPTO_O_HASHDIGESTO 0x000006F8 324 325 // HASH Digest P 326 #define CRYPTO_O_HASHDIGESTP 0x000006FC 327 328 // Algorithm Select 329 #define CRYPTO_O_ALGSEL 0x00000700 330 331 // DMA Protection Control 332 #define CRYPTO_O_DMAPROTCTL 0x00000704 333 334 // Software Reset 335 #define CRYPTO_O_SWRESET 0x00000740 336 337 // Control Interrupt Configuration 338 #define CRYPTO_O_IRQTYPE 0x00000780 339 340 // Control Interrupt Enable 341 #define CRYPTO_O_IRQEN 0x00000784 342 343 // Control Interrupt Clear 344 #define CRYPTO_O_IRQCLR 0x00000788 345 346 // Control Interrupt Set 347 #define CRYPTO_O_IRQSET 0x0000078C 348 349 // Control Interrupt Status 350 #define CRYPTO_O_IRQSTAT 0x00000790 351 352 // Hardware Version 353 #define CRYPTO_O_HWVER 0x000007FC 354 355 //***************************************************************************** 356 // 357 // Register: CRYPTO_O_DMACH0CTL 358 // 359 //***************************************************************************** 360 // Field: [1] PRIO 361 // 362 // Channel priority 363 // 0: Low 364 // 1: High 365 // If both channels have the same priority, access of the channels to the 366 // external port is arbitrated using the round robin scheme. If one channel has 367 // a high priority and another one low, the channel with the high priority is 368 // served first, in case of simultaneous access requests. 369 #define CRYPTO_DMACH0CTL_PRIO 0x00000002 370 #define CRYPTO_DMACH0CTL_PRIO_BITN 1 371 #define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 372 #define CRYPTO_DMACH0CTL_PRIO_S 1 373 374 // Field: [0] EN 375 // 376 // Channel enable 377 // 0: Disabled 378 // 1: Enable 379 // Note: Disabling an active channel interrupts the DMA operation. The ongoing 380 // block transfer completes, but no new transfers are requested. 381 #define CRYPTO_DMACH0CTL_EN 0x00000001 382 #define CRYPTO_DMACH0CTL_EN_BITN 0 383 #define CRYPTO_DMACH0CTL_EN_M 0x00000001 384 #define CRYPTO_DMACH0CTL_EN_S 0 385 386 //***************************************************************************** 387 // 388 // Register: CRYPTO_O_DMACH0EXTADDR 389 // 390 //***************************************************************************** 391 // Field: [31:0] ADDR 392 // 393 // Channel external address value 394 // When read during operation, it holds the last updated external address after 395 // being sent to the master interface. Note: The crypto DMA copies out upto 3 396 // bytes until it hits a word boundary, thus the address need not be word 397 // aligned. 398 #define CRYPTO_DMACH0EXTADDR_ADDR_W 32 399 #define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF 400 #define CRYPTO_DMACH0EXTADDR_ADDR_S 0 401 402 //***************************************************************************** 403 // 404 // Register: CRYPTO_O_DMACH0LEN 405 // 406 //***************************************************************************** 407 // Field: [15:0] DMALEN 408 // 409 // Channel DMA length in bytes 410 // During configuration, this register contains the DMA transfer length in 411 // bytes. During operation, it contains the last updated value of the DMA 412 // transfer length after being sent to the master interface. 413 // Note: Setting this register to a nonzero value starts the transfer if the 414 // channel is enabled. Therefore, this register must be written last when 415 // setting up a DMA channel. 416 #define CRYPTO_DMACH0LEN_DMALEN_W 16 417 #define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF 418 #define CRYPTO_DMACH0LEN_DMALEN_S 0 419 420 //***************************************************************************** 421 // 422 // Register: CRYPTO_O_DMASTAT 423 // 424 //***************************************************************************** 425 // Field: [17] PORT_ERR 426 // 427 // Reflects possible transfer errors on the AHB port. 428 #define CRYPTO_DMASTAT_PORT_ERR 0x00020000 429 #define CRYPTO_DMASTAT_PORT_ERR_BITN 17 430 #define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 431 #define CRYPTO_DMASTAT_PORT_ERR_S 17 432 433 // Field: [1] CH1_ACT 434 // 435 // A value of 1 indicates that channel 1 is active (DMA transfer on-going). 436 #define CRYPTO_DMASTAT_CH1_ACT 0x00000002 437 #define CRYPTO_DMASTAT_CH1_ACT_BITN 1 438 #define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 439 #define CRYPTO_DMASTAT_CH1_ACT_S 1 440 441 // Field: [0] CH0_ACT 442 // 443 // A value of 1 indicates that channel 0 is active (DMA transfer on-going). 444 #define CRYPTO_DMASTAT_CH0_ACT 0x00000001 445 #define CRYPTO_DMASTAT_CH0_ACT_BITN 0 446 #define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 447 #define CRYPTO_DMASTAT_CH0_ACT_S 0 448 449 //***************************************************************************** 450 // 451 // Register: CRYPTO_O_DMASWRESET 452 // 453 //***************************************************************************** 454 // Field: [0] SWRES 455 // 456 // Software reset enable 457 // 0 : Disabled 458 // 1 : Enabled (self-cleared to 0) 459 // Completion of the software reset must be checked through the DMASTAT 460 #define CRYPTO_DMASWRESET_SWRES 0x00000001 461 #define CRYPTO_DMASWRESET_SWRES_BITN 0 462 #define CRYPTO_DMASWRESET_SWRES_M 0x00000001 463 #define CRYPTO_DMASWRESET_SWRES_S 0 464 465 //***************************************************************************** 466 // 467 // Register: CRYPTO_O_DMACH1CTL 468 // 469 //***************************************************************************** 470 // Field: [1] PRIO 471 // 472 // Channel priority 473 // 0: Low 474 // 1: High 475 // If both channels have the same priority, access of the channels to the 476 // external port is arbitrated using the round robin scheme. If one channel has 477 // a high priority and another one low, the channel with the high priority is 478 // served first, in case of simultaneous access requests. 479 #define CRYPTO_DMACH1CTL_PRIO 0x00000002 480 #define CRYPTO_DMACH1CTL_PRIO_BITN 1 481 #define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 482 #define CRYPTO_DMACH1CTL_PRIO_S 1 483 484 // Field: [0] EN 485 // 486 // Channel enable 487 // 0: Disabled 488 // 1: Enable 489 // Note: Disabling an active channel interrupts the DMA operation. The ongoing 490 // block transfer completes, but no new transfers are requested. 491 #define CRYPTO_DMACH1CTL_EN 0x00000001 492 #define CRYPTO_DMACH1CTL_EN_BITN 0 493 #define CRYPTO_DMACH1CTL_EN_M 0x00000001 494 #define CRYPTO_DMACH1CTL_EN_S 0 495 496 //***************************************************************************** 497 // 498 // Register: CRYPTO_O_DMACH1EXTADDR 499 // 500 //***************************************************************************** 501 // Field: [31:0] ADDR 502 // 503 // Channel external address value. 504 // When read during operation, it holds the last updated external address after 505 // being sent to the master interface. Note: The crypto DMA copies out upto 3 506 // bytes until it hits a word boundary, thus the address need not be word 507 // aligned. 508 #define CRYPTO_DMACH1EXTADDR_ADDR_W 32 509 #define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF 510 #define CRYPTO_DMACH1EXTADDR_ADDR_S 0 511 512 //***************************************************************************** 513 // 514 // Register: CRYPTO_O_DMACH1LEN 515 // 516 //***************************************************************************** 517 // Field: [15:0] DMALEN 518 // 519 // Channel DMA length in bytes. 520 // During configuration, this register contains the DMA transfer length in 521 // bytes. During operation, it contains the last updated value of the DMA 522 // transfer length after being sent to the master interface. 523 // Note: Setting this register to a nonzero value starts the transfer if the 524 // channel is enabled. Therefore, this register must be written last when 525 // setting up a DMA channel. 526 #define CRYPTO_DMACH1LEN_DMALEN_W 16 527 #define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF 528 #define CRYPTO_DMACH1LEN_DMALEN_S 0 529 530 //***************************************************************************** 531 // 532 // Register: CRYPTO_O_DMABUSCFG 533 // 534 //***************************************************************************** 535 // Field: [15:12] AHB_MST1_BURST_SIZE 536 // 537 // Maximum burst size that can be performed on the AHB bus 538 // ENUMs: 539 // 64_BYTE 64 bytes 540 // 32_BYTE 32 bytes 541 // 16_BYTE 16 bytes 542 // 8_BYTE 8 bytes 543 // 4_BYTE 4 bytes 544 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 545 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 546 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 547 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 548 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 549 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 550 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 551 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 552 553 // Field: [11] AHB_MST1_IDLE_EN 554 // 555 // Idle insertion between consecutive burst transfers on AHB 556 // ENUMs: 557 // IDLE Idle transfer insertion enabled 558 // NO_IDLE Do not insert idle transfers. 559 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 560 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 561 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 562 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 563 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 564 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 565 566 // Field: [10] AHB_MST1_INCR_EN 567 // 568 // Burst length type of AHB transfer 569 // ENUMs: 570 // SPECIFIED Fixed length bursts or single transfers 571 // UNSPECIFIED Unspecified length burst transfers 572 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 573 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 574 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 575 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 576 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 577 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 578 579 // Field: [9] AHB_MST1_LOCK_EN 580 // 581 // Locked transform on AHB 582 // ENUMs: 583 // LOCKED Transfers are locked 584 // NOT_LOCKED Transfers are not locked 585 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 586 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 587 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 588 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 589 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 590 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 591 592 // Field: [8] AHB_MST1_BIGEND 593 // 594 // Endianess for the AHB master 595 // ENUMs: 596 // BIG_ENDIAN Big Endian 597 // LITTLE_ENDIAN Little Endian 598 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 599 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 600 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 601 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 602 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 603 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 604 605 //***************************************************************************** 606 // 607 // Register: CRYPTO_O_DMAPORTERR 608 // 609 //***************************************************************************** 610 // Field: [12] PORT1_AHB_ERROR 611 // 612 // A value of 1 indicates that the EIP-101 has detected an AHB bus error 613 #define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 614 #define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 615 #define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 616 #define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 617 618 // Field: [9] PORT1_CHANNEL 619 // 620 // Indicates which channel has serviced last (channel 0 or channel 1) by AHB 621 // master port. 622 #define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 623 #define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 624 #define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 625 #define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 626 627 //***************************************************************************** 628 // 629 // Register: CRYPTO_O_DMAHWVER 630 // 631 //***************************************************************************** 632 // Field: [27:24] HW_MAJOR_VERSION 633 // 634 // Major version number 635 #define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 636 #define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 637 #define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 638 639 // Field: [23:20] HW_MINOR_VERSION 640 // 641 // Minor version number 642 #define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 643 #define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 644 #define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 645 646 // Field: [19:16] HW_PATCH_LEVEL 647 // 648 // Patch level 649 // Starts at 0 at first delivery of this version 650 #define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 651 #define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 652 #define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 653 654 // Field: [15:8] EIP_NUMBER_COMPL 655 // 656 // Bit-by-bit complement of the EIP_NUMBER field bits. 657 #define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 658 #define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 659 #define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 660 661 // Field: [7:0] EIP_NUMBER 662 // 663 // Binary encoding of the EIP-number of this DMA controller (209) 664 #define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 665 #define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF 666 #define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 667 668 //***************************************************************************** 669 // 670 // Register: CRYPTO_O_KEYWRITEAREA 671 // 672 //***************************************************************************** 673 // Field: [7] RAM_AREA7 674 // 675 // Each RAM_AREAx represents an area of 128 bits. 676 // Select the key store RAM area(s) where the key(s) needs to be written 677 // 0: RAM_AREA7 is not selected to be written. 678 // 1: RAM_AREA7 is selected to be written. 679 // Writing to multiple RAM locations is possible only when the selected RAM 680 // areas are sequential. 681 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 682 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 683 // or RAM_AREA6. 684 // ENUMs: 685 // SEL This RAM area is selected to be written 686 // NOT_SEL This RAM area is not selected to be written 687 #define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 688 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 689 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 690 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 691 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 692 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 693 694 // Field: [6] RAM_AREA6 695 // 696 // Each RAM_AREAx represents an area of 128 bits. 697 // Select the key store RAM area(s) where the key(s) needs to be written 698 // 0: RAM_AREA6 is not selected to be written. 699 // 1: RAM_AREA6 is selected to be written. 700 // Writing to multiple RAM locations is possible only when the selected RAM 701 // areas are sequential. 702 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 703 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 704 // or RAM_AREA6. 705 // ENUMs: 706 // SEL This RAM area is selected to be written 707 // NOT_SEL This RAM area is not selected to be written 708 #define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 709 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 710 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 711 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 712 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 713 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 714 715 // Field: [5] RAM_AREA5 716 // 717 // Each RAM_AREAx represents an area of 128 bits. 718 // Select the key store RAM area(s) where the key(s) needs to be written 719 // 0: RAM_AREA5 is not selected to be written. 720 // 1: RAM_AREA5 is selected to be written. 721 // Writing to multiple RAM locations is possible only when the selected RAM 722 // areas are sequential. 723 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 724 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 725 // or RAM_AREA6. 726 // ENUMs: 727 // SEL This RAM area is selected to be written 728 // NOT_SEL This RAM area is not selected to be written 729 #define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 730 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 731 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 732 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 733 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 734 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 735 736 // Field: [4] RAM_AREA4 737 // 738 // Each RAM_AREAx represents an area of 128 bits. 739 // Select the key store RAM area(s) where the key(s) needs to be written 740 // 0: RAM_AREA4 is not selected to be written. 741 // 1: RAM_AREA4 is selected to be written. 742 // Writing to multiple RAM locations is possible only when the selected RAM 743 // areas are sequential. 744 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 745 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 746 // or RAM_AREA6. 747 // ENUMs: 748 // SEL This RAM area is selected to be written 749 // NOT_SEL This RAM area is not selected to be written 750 #define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 751 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 752 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 753 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 754 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 755 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 756 757 // Field: [3] RAM_AREA3 758 // 759 // Each RAM_AREAx represents an area of 128 bits. 760 // Select the key store RAM area(s) where the key(s) needs to be written 761 // 0: RAM_AREA3 is not selected to be written. 762 // 1: RAM_AREA3 is selected to be written. 763 // Writing to multiple RAM locations is possible only when the selected RAM 764 // areas are sequential. 765 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 766 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 767 // or RAM_AREA6. 768 // ENUMs: 769 // SEL This RAM area is selected to be written 770 // NOT_SEL This RAM area is not selected to be written 771 #define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 772 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 773 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 774 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 775 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 776 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 777 778 // Field: [2] RAM_AREA2 779 // 780 // Each RAM_AREAx represents an area of 128 bits. 781 // Select the key store RAM area(s) where the key(s) needs to be written 782 // 0: RAM_AREA2 is not selected to be written. 783 // 1: RAM_AREA2 is selected to be written. 784 // Writing to multiple RAM locations is possible only when the selected RAM 785 // areas are sequential. 786 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 787 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 788 // or RAM_AREA6. 789 // ENUMs: 790 // SEL This RAM area is selected to be written 791 // NOT_SEL This RAM area is not selected to be written 792 #define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 793 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 794 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 795 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 796 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 797 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 798 799 // Field: [1] RAM_AREA1 800 // 801 // Each RAM_AREAx represents an area of 128 bits. 802 // Select the key store RAM area(s) where the key(s) needs to be written 803 // 0: RAM_AREA1 is not selected to be written. 804 // 1: RAM_AREA1 is selected to be written. 805 // Writing to multiple RAM locations is possible only when the selected RAM 806 // areas are sequential. 807 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 808 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 809 // or RAM_AREA6. 810 // ENUMs: 811 // SEL This RAM area is selected to be written 812 // NOT_SEL This RAM area is not selected to be written 813 #define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 814 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 815 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 816 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 817 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 818 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 819 820 // Field: [0] RAM_AREA0 821 // 822 // Each RAM_AREAx represents an area of 128 bits. 823 // Select the key store RAM area(s) where the key(s) needs to be written 824 // 0: RAM_AREA0 is not selected to be written. 825 // 1: RAM_AREA0 is selected to be written. 826 // Writing to multiple RAM locations is possible only when the selected RAM 827 // areas are sequential. 828 // Keys that require more than one RAM locations (key size is 192 or 256 bits), 829 // must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, 830 // or RAM_AREA6. 831 // ENUMs: 832 // SEL This RAM area is selected to be written 833 // NOT_SEL This RAM area is not selected to be written 834 #define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 835 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 836 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 837 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 838 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 839 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 840 841 //***************************************************************************** 842 // 843 // Register: CRYPTO_O_KEYWRITTENAREA 844 // 845 //***************************************************************************** 846 // Field: [7] RAM_AREA_WRITTEN7 847 // 848 // On read this bit returns the key area written status. 849 // 850 // This bit can be reset by writing a 1. 851 // 852 // Note: This register will be reset on a soft reset initiated by writing to 853 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 854 // store memory. 855 // ENUMs: 856 // WRITTEN This RAM area is written with valid key 857 // information 858 // NOT_WRITTEN This RAM area is not written with valid key 859 // information 860 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 861 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 862 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 863 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 864 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 865 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 866 867 // Field: [6] RAM_AREA_WRITTEN6 868 // 869 // On read this bit returns the key area written status. 870 // 871 // This bit can be reset by writing a 1. 872 // 873 // Note: This register will be reset on a soft reset initiated by writing to 874 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 875 // store memory. 876 // ENUMs: 877 // WRITTEN This RAM area is written with valid key 878 // information 879 // NOT_WRITTEN This RAM area is not written with valid key 880 // information 881 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 882 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 883 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 884 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 885 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 886 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 887 888 // Field: [5] RAM_AREA_WRITTEN5 889 // 890 // On read this bit returns the key area written status. 891 // 892 // This bit can be reset by writing a 1. 893 // 894 // Note: This register will be reset on a soft reset initiated by writing to 895 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 896 // store memory. 897 // ENUMs: 898 // WRITTEN This RAM area is written with valid key 899 // information 900 // NOT_WRITTEN This RAM area is not written with valid key 901 // information 902 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 903 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 904 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 905 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 906 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 907 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 908 909 // Field: [4] RAM_AREA_WRITTEN4 910 // 911 // On read this bit returns the key area written status. 912 // 913 // This bit can be reset by writing a 1. 914 // 915 // Note: This register will be reset on a soft reset initiated by writing to 916 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 917 // store memory. 918 // ENUMs: 919 // WRITTEN This RAM area is written with valid key 920 // information 921 // NOT_WRITTEN This RAM area is not written with valid key 922 // information 923 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 924 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 925 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 926 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 927 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 928 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 929 930 // Field: [3] RAM_AREA_WRITTEN3 931 // 932 // On read this bit returns the key area written status. 933 // 934 // This bit can be reset by writing a 1. 935 // 936 // Note: This register will be reset on a soft reset initiated by writing to 937 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 938 // store memory. 939 // ENUMs: 940 // WRITTEN This RAM area is written with valid key 941 // information 942 // NOT_WRITTEN This RAM area is not written with valid key 943 // information 944 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 945 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 946 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 947 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 948 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 949 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 950 951 // Field: [2] RAM_AREA_WRITTEN2 952 // 953 // On read this bit returns the key area written status. 954 // 955 // This bit can be reset by writing a 1. 956 // 957 // Note: This register will be reset on a soft reset initiated by writing to 958 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 959 // store memory. 960 // ENUMs: 961 // WRITTEN This RAM area is written with valid key 962 // information 963 // NOT_WRITTEN This RAM area is not written with valid key 964 // information 965 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 966 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 967 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 968 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 969 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 970 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 971 972 // Field: [1] RAM_AREA_WRITTEN1 973 // 974 // On read this bit returns the key area written status. 975 // 976 // This bit can be reset by writing a 1. 977 // 978 // Note: This register will be reset on a soft reset initiated by writing to 979 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 980 // store memory. 981 // ENUMs: 982 // WRITTEN This RAM area is written with valid key 983 // information 984 // NOT_WRITTEN This RAM area is not written with valid key 985 // information 986 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 987 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 988 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 989 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 990 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 991 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 992 993 // Field: [0] RAM_AREA_WRITTEN0 994 // 995 // On read this bit returns the key area written status. 996 // 997 // This bit can be reset by writing a 1. 998 // 999 // Note: This register will be reset on a soft reset initiated by writing to 1000 // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key 1001 // store memory. 1002 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 1003 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 1004 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 1005 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 1006 1007 //***************************************************************************** 1008 // 1009 // Register: CRYPTO_O_KEYSIZE 1010 // 1011 //***************************************************************************** 1012 // Field: [1:0] SIZE 1013 // 1014 // Key size: 1015 // 00: Reserved 1016 // When writing this to this register, the KEY_STORE_WRITTEN_AREA register is 1017 // reset. 1018 // ENUMs: 1019 // 256_BIT 256 bits 1020 // 192_BIT 192 bits 1021 // 128_BIT 128 bits 1022 #define CRYPTO_KEYSIZE_SIZE_W 2 1023 #define CRYPTO_KEYSIZE_SIZE_M 0x00000003 1024 #define CRYPTO_KEYSIZE_SIZE_S 0 1025 #define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 1026 #define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 1027 #define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 1028 1029 //***************************************************************************** 1030 // 1031 // Register: CRYPTO_O_KEYREADAREA 1032 // 1033 //***************************************************************************** 1034 // Field: [31] BUSY 1035 // 1036 // Key store operation busy status flag (read only): 1037 // 0: Operation is complete. 1038 // 1: Operation is not completed and the key store is busy. 1039 #define CRYPTO_KEYREADAREA_BUSY 0x80000000 1040 #define CRYPTO_KEYREADAREA_BUSY_BITN 31 1041 #define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 1042 #define CRYPTO_KEYREADAREA_BUSY_S 31 1043 1044 // Field: [3:0] RAM_AREA 1045 // 1046 // Selects the area of the key store RAM from where the key needs to be read 1047 // that will be writen to the AES engine 1048 // RAM_AREA: 1049 // 1050 // RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid 1051 // read areas for 192 and 256 bits key sizes. 1052 // Only RAM areas that contain valid written keys can be selected. 1053 // ENUMs: 1054 // NO_RAM No RAM 1055 // RAM_AREA7 RAM Area 7 1056 // RAM_AREA6 RAM Area 6 1057 // RAM_AREA5 RAM Area 5 1058 // RAM_AREA4 RAM Area 4 1059 // RAM_AREA3 RAM Area 3 1060 // RAM_AREA2 RAM Area 2 1061 // RAM_AREA1 RAM Area 1 1062 // RAM_AREA0 RAM Area 0 1063 #define CRYPTO_KEYREADAREA_RAM_AREA_W 4 1064 #define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F 1065 #define CRYPTO_KEYREADAREA_RAM_AREA_S 0 1066 #define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 1067 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 1068 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 1069 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 1070 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 1071 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 1072 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 1073 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 1074 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 1075 1076 //***************************************************************************** 1077 // 1078 // Register: CRYPTO_O_AESKEY20 1079 // 1080 //***************************************************************************** 1081 // Field: [31:0] AES_KEY2 1082 // 1083 // AES_KEY2/AES_GHASH_H[31:0] 1084 // 1085 // For GCM: 1086 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1087 // registers. Only used for modes that use the GHASH function (GCM). 1088 // -[255:128] - This register is used to store intermediate values and is 1089 // initialized with 0s when loading a new key. 1090 // 1091 // For CCM: 1092 // -[255:0] - This register is used to store intermediate values. 1093 // 1094 // For CBC-MAC: 1095 // -[255:0] - ZEROES - This register must remain 0. 1096 #define CRYPTO_AESKEY20_AES_KEY2_W 32 1097 #define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF 1098 #define CRYPTO_AESKEY20_AES_KEY2_S 0 1099 1100 //***************************************************************************** 1101 // 1102 // Register: CRYPTO_O_AESKEY21 1103 // 1104 //***************************************************************************** 1105 // Field: [31:0] AES_KEY2 1106 // 1107 // AES_KEY2/AES_GHASH_H[31:0] 1108 // 1109 // For GCM: 1110 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1111 // registers. Only used for modes that use the GHASH function (GCM). 1112 // -[255:128] - This register is used to store intermediate values and is 1113 // initialized with 0s when loading a new key. 1114 // 1115 // For CCM: 1116 // -[255:0] - This register is used to store intermediate values. 1117 // 1118 // For CBC-MAC: 1119 // -[255:0] - ZEROES - This register must remain 0. 1120 #define CRYPTO_AESKEY21_AES_KEY2_W 32 1121 #define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF 1122 #define CRYPTO_AESKEY21_AES_KEY2_S 0 1123 1124 //***************************************************************************** 1125 // 1126 // Register: CRYPTO_O_AESKEY22 1127 // 1128 //***************************************************************************** 1129 // Field: [31:0] AES_KEY2 1130 // 1131 // AES_KEY2/AES_GHASH_H[31:0] 1132 // 1133 // For GCM: 1134 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1135 // registers. Only used for modes that use the GHASH function (GCM). 1136 // -[255:128] - This register is used to store intermediate values and is 1137 // initialized with 0s when loading a new key. 1138 // 1139 // For CCM: 1140 // -[255:0] - This register is used to store intermediate values. 1141 // 1142 // For CBC-MAC: 1143 // -[255:0] - ZEROES - This register must remain 0. 1144 #define CRYPTO_AESKEY22_AES_KEY2_W 32 1145 #define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF 1146 #define CRYPTO_AESKEY22_AES_KEY2_S 0 1147 1148 //***************************************************************************** 1149 // 1150 // Register: CRYPTO_O_AESKEY23 1151 // 1152 //***************************************************************************** 1153 // Field: [31:0] AES_KEY2 1154 // 1155 // AES_KEY2/AES_GHASH_H[31:0] 1156 // 1157 // For GCM: 1158 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1159 // registers. Only used for modes that use the GHASH function (GCM). 1160 // -[255:128] - This register is used to store intermediate values and is 1161 // initialized with 0s when loading a new key. 1162 // 1163 // For CCM: 1164 // -[255:0] - This register is used to store intermediate values. 1165 // 1166 // For CBC-MAC: 1167 // -[255:0] - ZEROES - This register must remain 0. 1168 #define CRYPTO_AESKEY23_AES_KEY2_W 32 1169 #define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF 1170 #define CRYPTO_AESKEY23_AES_KEY2_S 0 1171 1172 //***************************************************************************** 1173 // 1174 // Register: CRYPTO_O_AESKEY30 1175 // 1176 //***************************************************************************** 1177 // Field: [31:0] AES_KEY3 1178 // 1179 // AES_KEY3[31:0]/AES_KEY2[159:128] 1180 // 1181 // For GCM: 1182 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1183 // registers. Only used for modes that use the GHASH function (GCM). 1184 // -[255:128] - This register is used to store intermediate values and is 1185 // initialized with 0s when loading a new key. 1186 // 1187 // For CCM: 1188 // -[255:0] - This register is used to store intermediate values. 1189 // 1190 // For CBC-MAC: 1191 // -[255:0] - ZEROES - This register must remain 0. 1192 #define CRYPTO_AESKEY30_AES_KEY3_W 32 1193 #define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF 1194 #define CRYPTO_AESKEY30_AES_KEY3_S 0 1195 1196 //***************************************************************************** 1197 // 1198 // Register: CRYPTO_O_AESKEY31 1199 // 1200 //***************************************************************************** 1201 // Field: [31:0] AES_KEY3 1202 // 1203 // AES_KEY3[31:0]/AES_KEY2[159:128] 1204 // 1205 // For GCM: 1206 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1207 // registers. Only used for modes that use the GHASH function (GCM). 1208 // -[255:128] - This register is used to store intermediate values and is 1209 // initialized with 0s when loading a new key. 1210 // 1211 // For CCM: 1212 // -[255:0] - This register is used to store intermediate values. 1213 // 1214 // For CBC-MAC: 1215 // -[255:0] - ZEROES - This register must remain 0. 1216 #define CRYPTO_AESKEY31_AES_KEY3_W 32 1217 #define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF 1218 #define CRYPTO_AESKEY31_AES_KEY3_S 0 1219 1220 //***************************************************************************** 1221 // 1222 // Register: CRYPTO_O_AESKEY32 1223 // 1224 //***************************************************************************** 1225 // Field: [31:0] AES_KEY3 1226 // 1227 // AES_KEY3[31:0]/AES_KEY2[159:128] 1228 // 1229 // For GCM: 1230 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1231 // registers. Only used for modes that use the GHASH function (GCM). 1232 // -[255:128] - This register is used to store intermediate values and is 1233 // initialized with 0s when loading a new key. 1234 // 1235 // For CCM: 1236 // -[255:0] - This register is used to store intermediate values. 1237 // 1238 // For CBC-MAC: 1239 // -[255:0] - ZEROES - This register must remain 0. 1240 #define CRYPTO_AESKEY32_AES_KEY3_W 32 1241 #define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF 1242 #define CRYPTO_AESKEY32_AES_KEY3_S 0 1243 1244 //***************************************************************************** 1245 // 1246 // Register: CRYPTO_O_AESKEY33 1247 // 1248 //***************************************************************************** 1249 // Field: [31:0] AES_KEY3 1250 // 1251 // AES_KEY3[31:0]/AES_KEY2[159:128] 1252 // 1253 // For GCM: 1254 // -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these 1255 // registers. Only used for modes that use the GHASH function (GCM). 1256 // -[255:128] - This register is used to store intermediate values and is 1257 // initialized with 0s when loading a new key. 1258 // 1259 // For CCM: 1260 // -[255:0] - This register is used to store intermediate values. 1261 // 1262 // For CBC-MAC: 1263 // -[255:0] - ZEROES - This register must remain 0. 1264 #define CRYPTO_AESKEY33_AES_KEY3_W 32 1265 #define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF 1266 #define CRYPTO_AESKEY33_AES_KEY3_S 0 1267 1268 //***************************************************************************** 1269 // 1270 // Register: CRYPTO_O_AESIV0 1271 // 1272 //***************************************************************************** 1273 // Field: [31:0] AES_IV 1274 // 1275 // AES_IV[31:0] 1276 // 1277 // Initialization vector 1278 // Used for regular non-ECB modes (CBC/CTR): 1279 // -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers 1280 // must be written with a new 128-bit IV. After an operation, these registers 1281 // contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode 1282 // is selected, this value is incremented with 0x1: After first use - When a 1283 // new data block is submitted to the engine 1284 // 1285 // For GCM: 1286 // -[127:0] - AES_IV - For GCM operations, these registers must be written with 1287 // a new 128-bit IV. 1288 // After an operation, these registers contain the updated 128-bit result IV, 1289 // generated by the EIP-120t. Note that bits [127:96] of the IV represent the 1290 // initial counter value (which is 1 for GCM) and must therefore be initialized 1291 // to 0x01000000. This value is incremented with 0x1: After first use - When a 1292 // new data block is submitted to the engine. 1293 // 1294 // For CCM: 1295 // -[127:0] - A0: For CCM this field must be written with value A0, this value 1296 // is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and 1297 // counter value. 'L' must be a copy from the 'L' value of the AES_CTRL 1298 // register. This 'L' indicates the width of the Nonce and counter. The loaded 1299 // counter must be initialized to 0. The total width of A0 is 128-bit. 1300 // 1301 // For CBC-MAC: 1302 // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the 1303 // start of each operation. After an operation, these registers contain the 1304 // 128-bit TAG output, generated by the EIP-120t. 1305 #define CRYPTO_AESIV0_AES_IV_W 32 1306 #define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF 1307 #define CRYPTO_AESIV0_AES_IV_S 0 1308 1309 //***************************************************************************** 1310 // 1311 // Register: CRYPTO_O_AESIV1 1312 // 1313 //***************************************************************************** 1314 // Field: [31:0] AES_IV 1315 // 1316 // AES_IV[31:0] 1317 // 1318 // Initialization vector 1319 // Used for regular non-ECB modes (CBC/CTR): 1320 // -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers 1321 // must be written with a new 128-bit IV. After an operation, these registers 1322 // contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode 1323 // is selected, this value is incremented with 0x1: After first use - When a 1324 // new data block is submitted to the engine 1325 // 1326 // For GCM: 1327 // -[127:0] - AES_IV - For GCM operations, these registers must be written with 1328 // a new 128-bit IV. 1329 // After an operation, these registers contain the updated 128-bit result IV, 1330 // generated by the EIP-120t. Note that bits [127:96] of the IV represent the 1331 // initial counter value (which is 1 for GCM) and must therefore be initialized 1332 // to 0x01000000. This value is incremented with 0x1: After first use - When a 1333 // new data block is submitted to the engine. 1334 // 1335 // For CCM: 1336 // -[127:0] - A0: For CCM this field must be written with value A0, this value 1337 // is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and 1338 // counter value. 'L' must be a copy from the 'L' value of the AES_CTRL 1339 // register. This 'L' indicates the width of the Nonce and counter. The loaded 1340 // counter must be initialized to 0. The total width of A0 is 128-bit. 1341 // 1342 // For CBC-MAC: 1343 // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the 1344 // start of each operation. After an operation, these registers contain the 1345 // 128-bit TAG output, generated by the EIP-120t. 1346 #define CRYPTO_AESIV1_AES_IV_W 32 1347 #define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF 1348 #define CRYPTO_AESIV1_AES_IV_S 0 1349 1350 //***************************************************************************** 1351 // 1352 // Register: CRYPTO_O_AESIV2 1353 // 1354 //***************************************************************************** 1355 // Field: [31:0] AES_IV 1356 // 1357 // AES_IV[31:0] 1358 // 1359 // Initialization vector 1360 // Used for regular non-ECB modes (CBC/CTR): 1361 // -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers 1362 // must be written with a new 128-bit IV. After an operation, these registers 1363 // contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode 1364 // is selected, this value is incremented with 0x1: After first use - When a 1365 // new data block is submitted to the engine 1366 // 1367 // For GCM: 1368 // -[127:0] - AES_IV - For GCM operations, these registers must be written with 1369 // a new 128-bit IV. 1370 // After an operation, these registers contain the updated 128-bit result IV, 1371 // generated by the EIP-120t. Note that bits [127:96] of the IV represent the 1372 // initial counter value (which is 1 for GCM) and must therefore be initialized 1373 // to 0x01000000. This value is incremented with 0x1: After first use - When a 1374 // new data block is submitted to the engine. 1375 // 1376 // For CCM: 1377 // -[127:0] - A0: For CCM this field must be written with value A0, this value 1378 // is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and 1379 // counter value. 'L' must be a copy from the 'L' value of the AES_CTRL 1380 // register. This 'L' indicates the width of the Nonce and counter. The loaded 1381 // counter must be initialized to 0. The total width of A0 is 128-bit. 1382 // 1383 // For CBC-MAC: 1384 // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the 1385 // start of each operation. After an operation, these registers contain the 1386 // 128-bit TAG output, generated by the EIP-120t. 1387 #define CRYPTO_AESIV2_AES_IV_W 32 1388 #define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF 1389 #define CRYPTO_AESIV2_AES_IV_S 0 1390 1391 //***************************************************************************** 1392 // 1393 // Register: CRYPTO_O_AESIV3 1394 // 1395 //***************************************************************************** 1396 // Field: [31:0] AES_IV 1397 // 1398 // AES_IV[31:0] 1399 // 1400 // Initialization vector 1401 // Used for regular non-ECB modes (CBC/CTR): 1402 // -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers 1403 // must be written with a new 128-bit IV. After an operation, these registers 1404 // contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode 1405 // is selected, this value is incremented with 0x1: After first use - When a 1406 // new data block is submitted to the engine 1407 // 1408 // For GCM: 1409 // -[127:0] - AES_IV - For GCM operations, these registers must be written with 1410 // a new 128-bit IV. 1411 // After an operation, these registers contain the updated 128-bit result IV, 1412 // generated by the EIP-120t. Note that bits [127:96] of the IV represent the 1413 // initial counter value (which is 1 for GCM) and must therefore be initialized 1414 // to 0x01000000. This value is incremented with 0x1: After first use - When a 1415 // new data block is submitted to the engine. 1416 // 1417 // For CCM: 1418 // -[127:0] - A0: For CCM this field must be written with value A0, this value 1419 // is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and 1420 // counter value. 'L' must be a copy from the 'L' value of the AES_CTRL 1421 // register. This 'L' indicates the width of the Nonce and counter. The loaded 1422 // counter must be initialized to 0. The total width of A0 is 128-bit. 1423 // 1424 // For CBC-MAC: 1425 // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the 1426 // start of each operation. After an operation, these registers contain the 1427 // 128-bit TAG output, generated by the EIP-120t. 1428 #define CRYPTO_AESIV3_AES_IV_W 32 1429 #define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF 1430 #define CRYPTO_AESIV3_AES_IV_S 0 1431 1432 //***************************************************************************** 1433 // 1434 // Register: CRYPTO_O_AESCTL 1435 // 1436 //***************************************************************************** 1437 // Field: [31] CONTEXT_READY 1438 // 1439 // If 1, this read-only status bit indicates that the context data registers 1440 // can be overwritten and the host is permitted to write the next context. 1441 #define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 1442 #define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 1443 #define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 1444 #define CRYPTO_AESCTL_CONTEXT_READY_S 31 1445 1446 // Field: [30] SAVED_CONTEXT_RDY 1447 // 1448 // If 1, this status bit indicates that an AES authentication TAG and/or IV 1449 // block(s) is/are available for the host to retrieve. This bit is only 1450 // asserted if the save_context bit is set to 1. The bit is mutual exclusive 1451 // with the context_ready bit. 1452 // Writing one clears the bit to 0, indicating the AES core can start its next 1453 // operation. This bit is also cleared when the 4th word of the output TAG 1454 // and/or IV is read. 1455 // Note: All other mode bit writes are ignored when this mode bit is written 1456 // with 1. 1457 // Note: This bit is controlled automatically by the EIP-120t for TAG read DMA 1458 // operations. 1459 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 1460 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 1461 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 1462 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 1463 1464 // Field: [29] SAVE_CONTEXT 1465 // 1466 // This bit indicates that an authentication TAG or result IV needs to be 1467 // stored as a result context. 1468 // Typically this bit must be set for authentication modes returning a TAG 1469 // (CBC-MAC, GCM and CCM), or for basic encryption modes that require future 1470 // continuation with the current result IV. 1471 // If this bit is set, the engine retains its full context until the TAG and/or 1472 // IV registers are read. 1473 // The TAG or IV must be read before the AES engine can start a new operation. 1474 #define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 1475 #define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 1476 #define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 1477 #define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 1478 1479 // Field: [24:22] CCM_M 1480 // 1481 // Defines M, which indicates the length of the authentication field for CCM 1482 // operations; the authentication field length equals two times (the value of 1483 // CCM-M plus one). 1484 // Note: The EIP-120t always returns a 128-bit authentication field, of which 1485 // the M least significant bytes are valid. All values are supported. 1486 #define CRYPTO_AESCTL_CCM_M_W 3 1487 #define CRYPTO_AESCTL_CCM_M_M 0x01C00000 1488 #define CRYPTO_AESCTL_CCM_M_S 22 1489 1490 // Field: [21:19] CCM_L 1491 // 1492 // Defines L, which indicates the width of the length field for CCM operations; 1493 // the length field in bytes equals the value of CMM-L plus one. All values are 1494 // supported. 1495 #define CRYPTO_AESCTL_CCM_L_W 3 1496 #define CRYPTO_AESCTL_CCM_L_M 0x00380000 1497 #define CRYPTO_AESCTL_CCM_L_S 19 1498 1499 // Field: [18] CCM 1500 // 1501 // If set to 1, AES-CCM is selected 1502 // AES-CCM is a combined mode, using AES for authentication and encryption. 1503 // Note: Selecting AES-CCM mode requires writing of the AAD length register 1504 // after all other registers. 1505 // Note: The CTR mode bit in this register must also be set to 1 to enable 1506 // AES-CTR; selecting other AES modes than CTR mode is invalid. 1507 #define CRYPTO_AESCTL_CCM 0x00040000 1508 #define CRYPTO_AESCTL_CCM_BITN 18 1509 #define CRYPTO_AESCTL_CCM_M 0x00040000 1510 #define CRYPTO_AESCTL_CCM_S 18 1511 1512 // Field: [17:16] GCM 1513 // 1514 // Set these bits to 11 to select AES-GCM mode. 1515 // AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the 1516 // power of 128) for authentication and AES-CTR mode for encryption. 1517 // Note: The CTR mode bit in this register must also be set to 1 to enable 1518 // AES-CTR 1519 // Bit combination description: 1520 // 00 = No GCM mode 1521 // 01 = Reserved, do not select 1522 // 10 = Reserved, do not select 1523 // 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) 1524 // Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), 1525 // other GCM modes are not allowed. 1526 #define CRYPTO_AESCTL_GCM_W 2 1527 #define CRYPTO_AESCTL_GCM_M 0x00030000 1528 #define CRYPTO_AESCTL_GCM_S 16 1529 1530 // Field: [15] CBC_MAC 1531 // 1532 // Set to 1 to select AES-CBC MAC mode. 1533 // The direction bit must be set to 1 for this mode. 1534 // Selecting this mode requires writing the length register after all other 1535 // registers. 1536 #define CRYPTO_AESCTL_CBC_MAC 0x00008000 1537 #define CRYPTO_AESCTL_CBC_MAC_BITN 15 1538 #define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 1539 #define CRYPTO_AESCTL_CBC_MAC_S 15 1540 1541 // Field: [8:7] CTR_WIDTH 1542 // 1543 // Specifies the counter width for AES-CTR mode 1544 // 00 = 32-bit counter 1545 // 01 = 64-bit counter 1546 // 10 = 96-bit counter 1547 // 11 = 128-bit counter 1548 // ENUMs: 1549 // 128_BIT 128 bits 1550 // 96_BIT 96 bits 1551 // 64_BIT 64 bits 1552 // 32_BIT 32 bits 1553 #define CRYPTO_AESCTL_CTR_WIDTH_W 2 1554 #define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 1555 #define CRYPTO_AESCTL_CTR_WIDTH_S 7 1556 #define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 1557 #define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 1558 #define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 1559 #define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 1560 1561 // Field: [6] CTR 1562 // 1563 // If set to 1, AES counter mode (CTR) is selected. 1564 // Note: This bit must also be set for GCM and CCM, when encryption/decryption 1565 // is required. 1566 #define CRYPTO_AESCTL_CTR 0x00000040 1567 #define CRYPTO_AESCTL_CTR_BITN 6 1568 #define CRYPTO_AESCTL_CTR_M 0x00000040 1569 #define CRYPTO_AESCTL_CTR_S 6 1570 1571 // Field: [5] CBC 1572 // 1573 // If set to 1, cipher-block-chaining (CBC) mode is selected. 1574 #define CRYPTO_AESCTL_CBC 0x00000020 1575 #define CRYPTO_AESCTL_CBC_BITN 5 1576 #define CRYPTO_AESCTL_CBC_M 0x00000020 1577 #define CRYPTO_AESCTL_CBC_S 5 1578 1579 // Field: [4:3] KEY_SIZE 1580 // 1581 // This read-only field specifies the key size. 1582 // The key size is automatically configured when a new key is loaded through 1583 // the key store module. 1584 // 00 = N/A - Reserved 1585 // 01 = 128-bit 1586 // 10 = 192-bit 1587 // 11 = 256-bit 1588 #define CRYPTO_AESCTL_KEY_SIZE_W 2 1589 #define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 1590 #define CRYPTO_AESCTL_KEY_SIZE_S 3 1591 1592 // Field: [2] DIR 1593 // 1594 // If set to 1 an encrypt operation is performed. 1595 // If set to 0 a decrypt operation is performed. 1596 // This bit must be written with a 1 when CBC-MAC is selected. 1597 #define CRYPTO_AESCTL_DIR 0x00000004 1598 #define CRYPTO_AESCTL_DIR_BITN 2 1599 #define CRYPTO_AESCTL_DIR_M 0x00000004 1600 #define CRYPTO_AESCTL_DIR_S 2 1601 1602 // Field: [1] INPUT_READY 1603 // 1604 // If 1, this status bit indicates that the 16-byte AES input buffer is empty. 1605 // The host is permitted to write the next block of data. 1606 // Writing 0 clears the bit to 0 and indicates that the AES core can use the 1607 // provided input data block. 1608 // Writing 1 to this bit is ignored. 1609 // Note: For DMA operations, this bit is automatically controlled by the 1610 // EIP-120t. 1611 // After reset, this bit is 0. After writing a context, this bit becomes 1. 1612 #define CRYPTO_AESCTL_INPUT_READY 0x00000002 1613 #define CRYPTO_AESCTL_INPUT_READY_BITN 1 1614 #define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 1615 #define CRYPTO_AESCTL_INPUT_READY_S 1 1616 1617 // Field: [0] OUTPUT_READY 1618 // 1619 // If 1, this status bit indicates that an AES output block is available to be 1620 // retrieved by the host. 1621 // Writing 0 clears the bit to 0 and indicates that output data is read by the 1622 // host. The AES core can provide a next output data block. 1623 // Writing 1 to this bit is ignored. 1624 // Note: For DMA operations, this bit is automatically controlled by the 1625 // EIP-120t. 1626 #define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 1627 #define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 1628 #define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 1629 #define CRYPTO_AESCTL_OUTPUT_READY_S 0 1630 1631 //***************************************************************************** 1632 // 1633 // Register: CRYPTO_O_AESDATALEN0 1634 // 1635 //***************************************************************************** 1636 // Field: [31:0] C_LENGTH 1637 // 1638 // C_LENGTH[31:0] 1639 // Bits [60:0] of the crypto length registers (LSW and MSW) store the 1640 // cryptographic data length in bytes for all modes. Once processing with this 1641 // context is started, this length decrements to 0. Data lengths up to (261: 1) 1642 // bytes are allowed. 1643 // For GCM, any value up to 236 - 32 bytes can be used. This is because a 1644 // 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 1645 // 2, resulting in a maximum number of bytes of 236 - 32. 1646 // A write to this register triggers the engine to start using this context. 1647 // This is valid for all modes except GCM and CCM. 1648 // Note: For the combined modes (GCM and CCM), this length does not include the 1649 // authentication only data; the authentication length is specified in the 1650 // AESAUTHLEN register 1651 // All modes must have a length greater than 0. For the combined modes, it is 1652 // allowed to have one of the lengths equal to 0. 1653 // For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program 1654 // zero to the length field; in that case the length is assumed infinite. 1655 // All data must be byte (8-bit) aligned for stream cipher modes; bit aligned 1656 // data streams are not supported by the EIP-120t. For block cipher modes, the 1657 // data length must be programmed in multiples of the block cipher size, 16 1658 // bytes. 1659 // For a host read operation, these registers return all-0s. 1660 #define CRYPTO_AESDATALEN0_C_LENGTH_W 32 1661 #define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF 1662 #define CRYPTO_AESDATALEN0_C_LENGTH_S 0 1663 1664 //***************************************************************************** 1665 // 1666 // Register: CRYPTO_O_AESDATALEN1 1667 // 1668 //***************************************************************************** 1669 // Field: [28:0] C_LENGTH 1670 // 1671 // C_LENGTH[60:32] 1672 // Bits [60:0] of the crypto length registers (LSW and MSW) store the 1673 // cryptographic data length in bytes for all modes. Once processing with this 1674 // context is started, this length decrements to 0. Data lengths up to (261: 1) 1675 // bytes are allowed. 1676 // For GCM, any value up to 236 - 32 bytes can be used. This is because a 1677 // 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - 1678 // 2, resulting in a maximum number of bytes of 236 - 32. 1679 // A write to this register triggers the engine to start using this context. 1680 // This is valid for all modes except GCM and CCM. 1681 // Note: For the combined modes (GCM and CCM), this length does not include the 1682 // authentication only data; the authentication length is specified in the 1683 // AESAUTHLEN register 1684 // All modes must have a length greater than 0. For the combined modes, it is 1685 // allowed to have one of the lengths equal to 0. 1686 // For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program 1687 // zero to the length field; in that case the length is assumed infinite. 1688 // All data must be byte (8-bit) aligned for stream cipher modes; bit aligned 1689 // data streams are not supported by the EIP-120t. For block cipher modes, the 1690 // data length must be programmed in multiples of the block cipher size, 16 1691 // bytes. 1692 // For a host read operation, these registers return all-0s. 1693 #define CRYPTO_AESDATALEN1_C_LENGTH_W 29 1694 #define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF 1695 #define CRYPTO_AESDATALEN1_C_LENGTH_S 0 1696 1697 //***************************************************************************** 1698 // 1699 // Register: CRYPTO_O_AESAUTHLEN 1700 // 1701 //***************************************************************************** 1702 // Field: [31:0] AUTH_LENGTH 1703 // 1704 // Bits [31:0] of the authentication length register store the authentication 1705 // data length in bytes for combined modes only (GCM or CCM). 1706 // Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any 1707 // value up to (2^32 - 1) bytes can be used. Once processing with this context 1708 // is started, this length decrements to 0. 1709 // A write to this register triggers the engine to start using this context for 1710 // GCM and CCM. 1711 // For a host read operation, these registers return all-0s. 1712 #define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 1713 #define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF 1714 #define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 1715 1716 //***************************************************************************** 1717 // 1718 // Register: CRYPTO_O_AESDATAOUT0 1719 // 1720 //***************************************************************************** 1721 // Field: [31:0] DATA 1722 // 1723 // Data register 0 for output block data from the Crypto peripheral. 1724 // These bits = AES Output Data[31:0] of {127:0] 1725 // 1726 // For normal operations, this register is not used, since data input and 1727 // output is transferred from and to the AES engine via DMA. 1728 // 1729 // For a Host read operation, these registers contain the 128-bit output block 1730 // from the latest AES operation. Reading from a word-aligned offset within 1731 // this address range will read one word (4 bytes) of data out the 4-word deep 1732 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1733 // full block) should be read before the core will move the next block to the 1734 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY 1735 // must be written. 1736 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1737 // (message) bytes/words can be written with any data. 1738 // 1739 // Note: The AAD / authentication only data is not copied to the output buffer 1740 // but only used for authentication. 1741 #define CRYPTO_AESDATAOUT0_DATA_W 32 1742 #define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF 1743 #define CRYPTO_AESDATAOUT0_DATA_S 0 1744 1745 //***************************************************************************** 1746 // 1747 // Register: CRYPTO_O_AESDATAIN0 1748 // 1749 //***************************************************************************** 1750 // Field: [31:0] AES_DATA_IN_OUT 1751 // 1752 // AES input data[31:0] / AES output data[31:0] 1753 // Data registers for input/output block data to/from the EIP-120t. 1754 // For normal operations, this register is not used, since data input and 1755 // output is transferred from and to the AES core via DMA. For a host write 1756 // operation, these registers must be written with the 128-bit input block for 1757 // the next AES operation. Writing at a word-aligned offset within this address 1758 // range stores the word (4 bytes) of data into the corresponding position of 1759 // 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is 1760 // used for the next AES operation. If the last data block is not completely 1761 // filled with valid data (see notes below), it is allowed to write only the 1762 // words with valid data. Next AES operation is triggered by writing to the 1763 // input_ready flag of the AES_CTRL register. 1764 // For a host read operation, these registers contain the 128-bit output block 1765 // from the latest AES operation. Reading from a word-aligned offset within 1766 // this address range reads one word (4 bytes) of data out the 4-word deep (16 1767 // bytes = 128-bits AES block) data output buffer. The words (4 words, one full 1768 // block) should be read before the core will move the next block to the data 1769 // output buffer. To empty the data output buffer, the output_ready flag of the 1770 // AES_CTRL register must be written. 1771 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1772 // (message) bytes/words can be written with any data. 1773 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1774 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1775 // may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the 1776 // last block of both AAD and message data may contain less than 128 bits 1777 // (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks 1778 // misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR 1779 // mode, the remaining data in an unaligned data block is ignored. 1780 // Note: The AAD / authentication only data is not copied to the output buffer 1781 // but only used for authentication. 1782 #define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 1783 #define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF 1784 #define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 1785 1786 //***************************************************************************** 1787 // 1788 // Register: CRYPTO_O_AESDATAOUT1 1789 // 1790 //***************************************************************************** 1791 // Field: [31:0] DATA 1792 // 1793 // Data register 0 for output block data from the Crypto peripheral. 1794 // These bits = AES Output Data[31:0] of {127:0] 1795 // 1796 // For normal operations, this register is not used, since data input and 1797 // output is transferred from and to the AES engine via DMA. 1798 // 1799 // For a Host read operation, these registers contain the 128-bit output block 1800 // from the latest AES operation. Reading from a word-aligned offset within 1801 // this address range will read one word (4 bytes) of data out the 4-word deep 1802 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1803 // full block) should be read before the core will move the next block to the 1804 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY 1805 // must be written. 1806 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1807 // (message) bytes/words can be written with any data. 1808 // 1809 // Note: The AAD / authentication only data is not copied to the output buffer 1810 // but only used for authentication. 1811 #define CRYPTO_AESDATAOUT1_DATA_W 32 1812 #define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF 1813 #define CRYPTO_AESDATAOUT1_DATA_S 0 1814 1815 //***************************************************************************** 1816 // 1817 // Register: CRYPTO_O_AESDATAIN1 1818 // 1819 //***************************************************************************** 1820 // Field: [31:0] AES_DATA_IN_OUT 1821 // 1822 // AES input data[31:0] / AES output data[63:32] 1823 // Data registers for input/output block data to/from the EIP-120t. 1824 // For normal operations, this register is not used, since data input and 1825 // output is transferred from and to the AES core via DMA. For a host write 1826 // operation, these registers must be written with the 128-bit input block for 1827 // the next AES operation. Writing at a word-aligned offset within this address 1828 // range stores the word (4 bytes) of data into the corresponding position of 1829 // 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is 1830 // used for the next AES operation. If the last data block is not completely 1831 // filled with valid data (see notes below), it is allowed to write only the 1832 // words with valid data. Next AES operation is triggered by writing to the 1833 // input_ready flag of the AES_CTRL register. 1834 // For a host read operation, these registers contain the 128-bit output block 1835 // from the latest AES operation. Reading from a word-aligned offset within 1836 // this address range reads one word (4 bytes) of data out the 4-word deep (16 1837 // bytes = 128-bits AES block) data output buffer. The words (4 words, one full 1838 // block) should be read before the core will move the next block to the data 1839 // output buffer. To empty the data output buffer, the output_ready flag of the 1840 // AES_CTRL register must be written. 1841 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1842 // (message) bytes/words can be written with any data. 1843 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1844 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1845 // may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the 1846 // last block of both AAD and message data may contain less than 128 bits 1847 // (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks 1848 // misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR 1849 // mode, the remaining data in an unaligned data block is ignored. 1850 // Note: The AAD / authentication only data is not copied to the output buffer 1851 // but only used for authentication. 1852 #define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 1853 #define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF 1854 #define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 1855 1856 //***************************************************************************** 1857 // 1858 // Register: CRYPTO_O_AESDATAOUT2 1859 // 1860 //***************************************************************************** 1861 // Field: [31:0] DATA 1862 // 1863 // Data register 0 for output block data from the Crypto peripheral. 1864 // These bits = AES Output Data[31:0] of {127:0] 1865 // 1866 // For normal operations, this register is not used, since data input and 1867 // output is transferred from and to the AES engine via DMA. 1868 // 1869 // For a Host read operation, these registers contain the 128-bit output block 1870 // from the latest AES operation. Reading from a word-aligned offset within 1871 // this address range will read one word (4 bytes) of data out the 4-word deep 1872 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1873 // full block) should be read before the core will move the next block to the 1874 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY 1875 // must be written. 1876 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1877 // (message) bytes/words can be written with any data. 1878 // 1879 // Note: The AAD / authentication only data is not copied to the output buffer 1880 // but only used for authentication. 1881 #define CRYPTO_AESDATAOUT2_DATA_W 32 1882 #define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF 1883 #define CRYPTO_AESDATAOUT2_DATA_S 0 1884 1885 //***************************************************************************** 1886 // 1887 // Register: CRYPTO_O_AESDATAIN2 1888 // 1889 //***************************************************************************** 1890 // Field: [31:0] AES_DATA_IN_OUT 1891 // 1892 // AES input data[95:64] / AES output data[95:64] 1893 // Data registers for input/output block data to/from the EIP-120t. 1894 // For normal operations, this register is not used, since data input and 1895 // output is transferred from and to the AES core via DMA. For a host write 1896 // operation, these registers must be written with the 128-bit input block for 1897 // the next AES operation. Writing at a word-aligned offset within this address 1898 // range stores the word (4 bytes) of data into the corresponding position of 1899 // 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is 1900 // used for the next AES operation. If the last data block is not completely 1901 // filled with valid data (see notes below), it is allowed to write only the 1902 // words with valid data. Next AES operation is triggered by writing to the 1903 // input_ready flag of the AES_CTRL register. 1904 // For a host read operation, these registers contain the 128-bit output block 1905 // from the latest AES operation. Reading from a word-aligned offset within 1906 // this address range reads one word (4 bytes) of data out the 4-word deep (16 1907 // bytes = 128-bits AES block) data output buffer. The words (4 words, one full 1908 // block) should be read before the core will move the next block to the data 1909 // output buffer. To empty the data output buffer, the output_ready flag of the 1910 // AES_CTRL register must be written. 1911 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1912 // (message) bytes/words can be written with any data. 1913 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1914 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1915 // may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the 1916 // last block of both AAD and message data may contain less than 128 bits 1917 // (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks 1918 // misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR 1919 // mode, the remaining data in an unaligned data block is ignored. 1920 // Note: The AAD / authentication only data is not copied to the output buffer 1921 // but only used for authentication. 1922 #define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 1923 #define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF 1924 #define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 1925 1926 //***************************************************************************** 1927 // 1928 // Register: CRYPTO_O_AESDATAOUT3 1929 // 1930 //***************************************************************************** 1931 // Field: [31:0] DATA 1932 // 1933 // Data register 0 for output block data from the Crypto peripheral. 1934 // These bits = AES Output Data[31:0] of {127:0] 1935 // 1936 // For normal operations, this register is not used, since data input and 1937 // output is transferred from and to the AES engine via DMA. 1938 // 1939 // For a Host read operation, these registers contain the 128-bit output block 1940 // from the latest AES operation. Reading from a word-aligned offset within 1941 // this address range will read one word (4 bytes) of data out the 4-word deep 1942 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1943 // full block) should be read before the core will move the next block to the 1944 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY 1945 // must be written. 1946 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1947 // (message) bytes/words can be written with any data. 1948 // 1949 // Note: The AAD / authentication only data is not copied to the output buffer 1950 // but only used for authentication. 1951 #define CRYPTO_AESDATAOUT3_DATA_W 32 1952 #define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF 1953 #define CRYPTO_AESDATAOUT3_DATA_S 0 1954 1955 //***************************************************************************** 1956 // 1957 // Register: CRYPTO_O_AESDATAIN3 1958 // 1959 //***************************************************************************** 1960 // Field: [31:0] AES_DATA_IN_OUT 1961 // 1962 // AES input data[127:96] / AES output data[127:96] 1963 // Data registers for input/output block data to/from the EIP-120t. 1964 // For normal operations, this register is not used, since data input and 1965 // output is transferred from and to the AES core via DMA. For a host write 1966 // operation, these registers must be written with the 128-bit input block for 1967 // the next AES operation. Writing at a word-aligned offset within this address 1968 // range stores the word (4 bytes) of data into the corresponding position of 1969 // 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is 1970 // used for the next AES operation. If the last data block is not completely 1971 // filled with valid data (see notes below), it is allowed to write only the 1972 // words with valid data. Next AES operation is triggered by writing to the 1973 // input_ready flag of the AES_CTRL register. 1974 // For a host read operation, these registers contain the 128-bit output block 1975 // from the latest AES operation. Reading from a word-aligned offset within 1976 // this address range reads one word (4 bytes) of data out the 4-word deep (16 1977 // bytes = 128-bits AES block) data output buffer. The words (4 words, one full 1978 // block) should be read before the core will move the next block to the data 1979 // output buffer. To empty the data output buffer, the output_ready flag of the 1980 // AES_CTRL register must be written. 1981 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1982 // (message) bytes/words can be written with any data. 1983 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1984 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1985 // may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the 1986 // last block of both AAD and message data may contain less than 128 bits 1987 // (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks 1988 // misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR 1989 // mode, the remaining data in an unaligned data block is ignored. 1990 // Note: The AAD / authentication only data is not copied to the output buffer 1991 // but only used for authentication. 1992 #define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 1993 #define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF 1994 #define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 1995 1996 //***************************************************************************** 1997 // 1998 // Register: CRYPTO_O_AESTAGOUT0 1999 // 2000 //***************************************************************************** 2001 // Field: [31:0] AES_TAG 2002 // 2003 // AES_TAG[31:0] 2004 // Bits [31:0] of this register stores the authentication value for the 2005 // combined and authentication only modes. 2006 // For a host read operation, these registers contain the last 128-bit TAG 2007 // output of the EIP-120t; the TAG is available until the next context is 2008 // written. 2009 // This register will only contain valid data if the TAG is available and when 2010 // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for 2011 // operations/modes that do not return a TAG, reads from this register return 2012 // data from the IV register. 2013 #define CRYPTO_AESTAGOUT0_AES_TAG_W 32 2014 #define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF 2015 #define CRYPTO_AESTAGOUT0_AES_TAG_S 0 2016 2017 //***************************************************************************** 2018 // 2019 // Register: CRYPTO_O_AESTAGOUT1 2020 // 2021 //***************************************************************************** 2022 // Field: [31:0] AES_TAG 2023 // 2024 // AES_TAG[31:0] 2025 // Bits [31:0] of this register stores the authentication value for the 2026 // combined and authentication only modes. 2027 // For a host read operation, these registers contain the last 128-bit TAG 2028 // output of the EIP-120t; the TAG is available until the next context is 2029 // written. 2030 // This register will only contain valid data if the TAG is available and when 2031 // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for 2032 // operations/modes that do not return a TAG, reads from this register return 2033 // data from the IV register. 2034 #define CRYPTO_AESTAGOUT1_AES_TAG_W 32 2035 #define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF 2036 #define CRYPTO_AESTAGOUT1_AES_TAG_S 0 2037 2038 //***************************************************************************** 2039 // 2040 // Register: CRYPTO_O_AESTAGOUT2 2041 // 2042 //***************************************************************************** 2043 // Field: [31:0] AES_TAG 2044 // 2045 // AES_TAG[31:0] 2046 // Bits [31:0] of this register stores the authentication value for the 2047 // combined and authentication only modes. 2048 // For a host read operation, these registers contain the last 128-bit TAG 2049 // output of the EIP-120t; the TAG is available until the next context is 2050 // written. 2051 // This register will only contain valid data if the TAG is available and when 2052 // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for 2053 // operations/modes that do not return a TAG, reads from this register return 2054 // data from the IV register. 2055 #define CRYPTO_AESTAGOUT2_AES_TAG_W 32 2056 #define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF 2057 #define CRYPTO_AESTAGOUT2_AES_TAG_S 0 2058 2059 //***************************************************************************** 2060 // 2061 // Register: CRYPTO_O_AESTAGOUT3 2062 // 2063 //***************************************************************************** 2064 // Field: [31:0] AES_TAG 2065 // 2066 // AES_TAG[31:0] 2067 // Bits [31:0] of this register stores the authentication value for the 2068 // combined and authentication only modes. 2069 // For a host read operation, these registers contain the last 128-bit TAG 2070 // output of the EIP-120t; the TAG is available until the next context is 2071 // written. 2072 // This register will only contain valid data if the TAG is available and when 2073 // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for 2074 // operations/modes that do not return a TAG, reads from this register return 2075 // data from the IV register. 2076 #define CRYPTO_AESTAGOUT3_AES_TAG_W 32 2077 #define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF 2078 #define CRYPTO_AESTAGOUT3_AES_TAG_S 0 2079 2080 //***************************************************************************** 2081 // 2082 // Register: CRYPTO_O_HASHDATAIN1 2083 // 2084 //***************************************************************************** 2085 // Field: [31:0] HASH_DATA_IN 2086 // 2087 // HASH_DATA_IN[63:32] 2088 // These registers must be written with the 512-bit input data. The data lines 2089 // are connected directly to the data input of the hash module and hence into 2090 // the engine's internal data buffer. Writing to each of the registers triggers 2091 // a corresponding 32-bit write enable to the internal buffer. 2092 // Note: The host may only write the input data buffer when 2093 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is 2094 // busy with processing. During processing, it is not allowed to write new 2095 // input data. 2096 // For message lengths larger than 64 bytes, multiple blocks of data are 2097 // written to this input buffer using a handshake through flags of the 2098 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2099 // bits in size. If the last block is not 512 bits long, only the least 2100 // significant bits of data must be written, but they must be padded with 0s to 2101 // the next 32-bit boundary. 2102 // Host read operations from these register addresses return 0s. 2103 #define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 2104 #define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF 2105 #define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 2106 2107 //***************************************************************************** 2108 // 2109 // Register: CRYPTO_O_HASHDATAIN2 2110 // 2111 //***************************************************************************** 2112 // Field: [31:0] HASH_DATA_IN 2113 // 2114 // HASH_DATA_IN[95:64] 2115 // These registers must be written with the 512-bit input data. The data lines 2116 // are connected directly to the data input of the hash module and hence into 2117 // the engine's internal data buffer. Writing to each of the registers triggers 2118 // a corresponding 32-bit write enable to the internal buffer. 2119 // Note: The host may only write the input data buffer when 2120 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is 2121 // busy with processing. During processing, it is not allowed to write new 2122 // input data. 2123 // For message lengths larger than 64 bytes, multiple blocks of data are 2124 // written to this input buffer using a handshake through flags of the 2125 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2126 // bits in size. If the last block is not 512 bits long, only the least 2127 // significant bits of data must be written, but they must be padded with 0s to 2128 // the next 32-bit boundary. 2129 // Host read operations from these register addresses return 0s. 2130 #define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 2131 #define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF 2132 #define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 2133 2134 //***************************************************************************** 2135 // 2136 // Register: CRYPTO_O_HASHDATAIN3 2137 // 2138 //***************************************************************************** 2139 // Field: [31:0] HASH_DATA_IN 2140 // 2141 // HASH_DATA_IN[127:96] 2142 // These registers must be written with the 512-bit input data. The data lines 2143 // are connected directly to the data input of the hash module and hence into 2144 // the engine's internal data buffer. Writing to each of the registers triggers 2145 // a corresponding 32-bit write enable to the internal buffer. 2146 // Note: The host may only write the input data buffer when the rfd_in bit of 2147 // the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is 2148 // busy with processing. During processing, it is not allowed to write new 2149 // input data. 2150 // For message lengths larger than 64 bytes, multiple blocks of data are 2151 // written to this input buffer using a handshake through flags of the 2152 // HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 2153 // bits in size. If the last block is not 512 bits long, only the least 2154 // significant bits of data must be written, but they must be padded with 0s to 2155 // the next 32-bit boundary. 2156 // Host read operations from these register addresses return 0s. 2157 #define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 2158 #define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF 2159 #define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 2160 2161 //***************************************************************************** 2162 // 2163 // Register: CRYPTO_O_HASHDATAIN4 2164 // 2165 //***************************************************************************** 2166 // Field: [31:0] HASH_DATA_IN 2167 // 2168 // HASH_DATA_IN[159:128] 2169 // These registers must be written with the 512-bit input data. The data lines 2170 // are connected directly to the data input of the hash module and hence into 2171 // the engine's internal data buffer. Writing to each of the registers triggers 2172 // a corresponding 32-bit write enable to the internal buffer. 2173 // Note: The host may only write the input data buffer when 2174 // HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2175 // is busy with processing. During processing, it is not allowed to write new 2176 // input data. 2177 // For message lengths larger than 64 bytes, multiple blocks of data are 2178 // written to this input buffer using a handshake through flags of the 2179 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2180 // bits in size. If the last block is not 512 bits long, only the least 2181 // significant bits of data must be written, but they must be padded with 0s to 2182 // the next 32-bit boundary. 2183 // Host read operations from these register addresses return 0s. 2184 #define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 2185 #define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF 2186 #define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 2187 2188 //***************************************************************************** 2189 // 2190 // Register: CRYPTO_O_HASHDATAIN5 2191 // 2192 //***************************************************************************** 2193 // Field: [31:0] HASH_DATA_IN 2194 // 2195 // HASH_DATA_IN[191:160] 2196 // These registers must be written with the 512-bit input data. The data lines 2197 // are connected directly to the data input of the hash module and hence into 2198 // the engine's internal data buffer. Writing to each of the registers triggers 2199 // a corresponding 32-bit write enable to the internal buffer. 2200 // Note: The host may only write the input data buffer when 2201 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2202 // is busy with processing. During processing, it is not allowed to write new 2203 // input data. 2204 // For message lengths larger than 64 bytes, multiple blocks of data are 2205 // written to this input buffer using a handshake through flags of the 2206 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2207 // bits in size. If the last block is not 512 bits long, only the least 2208 // significant bits of data must be written, but they must be padded with 0s to 2209 // the next 32-bit boundary. 2210 // Host read operations from these register addresses return 0s. 2211 #define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 2212 #define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF 2213 #define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 2214 2215 //***************************************************************************** 2216 // 2217 // Register: CRYPTO_O_HASHDATAIN6 2218 // 2219 //***************************************************************************** 2220 // Field: [31:0] HASH_DATA_IN 2221 // 2222 // HASH_DATA_IN[223:192] 2223 // These registers must be written with the 512-bit input data. The data lines 2224 // are connected directly to the data input of the hash module and hence into 2225 // the engine's internal data buffer. Writing to each of the registers triggers 2226 // a corresponding 32-bit write enable to the internal buffer. 2227 // Note: The host may only write the input data buffer when 2228 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2229 // is busy with processing. During processing, it is not allowed to write new 2230 // input data. 2231 // For message lengths larger than 64 bytes, multiple blocks of data are 2232 // written to this input buffer using a handshake through flags of the 2233 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2234 // bits in size. If the last block is not 512 bits long, only the least 2235 // significant bits of data must be written, but they must be padded with 0s to 2236 // the next 32-bit boundary. 2237 // Host read operations from these register addresses return 0s. 2238 #define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 2239 #define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF 2240 #define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 2241 2242 //***************************************************************************** 2243 // 2244 // Register: CRYPTO_O_HASHDATAIN7 2245 // 2246 //***************************************************************************** 2247 // Field: [31:0] HASH_DATA_IN 2248 // 2249 // HASH_DATA_IN[255:224] 2250 // These registers must be written with the 512-bit input data. The data lines 2251 // are connected directly to the data input of the hash module and hence into 2252 // the engine's internal data buffer. Writing to each of the registers triggers 2253 // a corresponding 32-bit write enable to the internal buffer. 2254 // Note: The host may only write the input data buffer when 2255 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2256 // is busy with processing. During processing, it is not allowed to write new 2257 // input data. 2258 // For message lengths larger than 64 bytes, multiple blocks of data are 2259 // written to this input buffer using a handshake through flags of the 2260 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2261 // bits in size. If the last block is not 512 bits long, only the least 2262 // significant bits of data must be written, but they must be padded with 0s to 2263 // the next 32-bit boundary. 2264 // Host read operations from these register addresses return 0s. 2265 #define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 2266 #define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF 2267 #define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 2268 2269 //***************************************************************************** 2270 // 2271 // Register: CRYPTO_O_HASHDATAIN8 2272 // 2273 //***************************************************************************** 2274 // Field: [31:0] HASH_DATA_IN 2275 // 2276 // HASH_DATA_IN[287:256] 2277 // These registers must be written with the 512-bit input data. The data lines 2278 // are connected directly to the data input of the hash module and hence into 2279 // the engine's internal data buffer. Writing to each of the registers triggers 2280 // a corresponding 32-bit write enable to the internal buffer. 2281 // Note: The host may only write the input data buffer when 2282 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2283 // is busy with processing. During processing, it is not allowed to write new 2284 // input data. 2285 // For message lengths larger than 64 bytes, multiple blocks of data are 2286 // written to this input buffer using a handshake through flags of the 2287 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2288 // bits in size. If the last block is not 512 bits long, only the least 2289 // significant bits of data must be written, but they must be padded with 0s to 2290 // the next 32-bit boundary. 2291 // Host read operations from these register addresses return 0s. 2292 #define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 2293 #define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF 2294 #define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 2295 2296 //***************************************************************************** 2297 // 2298 // Register: CRYPTO_O_HASHDATAIN9 2299 // 2300 //***************************************************************************** 2301 // Field: [31:0] HASH_DATA_IN 2302 // 2303 // HASH_DATA_IN[319:288] 2304 // These registers must be written with the 512-bit input data. The data lines 2305 // are connected directly to the data input of the hash module and hence into 2306 // the engine's internal data buffer. Writing to each of the registers triggers 2307 // a corresponding 32-bit write enable to the internal buffer. 2308 // Note: The host may only write the input data buffer when 2309 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2310 // is busy with processing. During processing, it is not allowed to write new 2311 // input data. 2312 // For message lengths larger than 64 bytes, multiple blocks of data are 2313 // written to this input buffer using a handshake through flags of the 2314 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2315 // bits in size. If the last block is not 512 bits long, only the least 2316 // significant bits of data must be written, but they must be padded with 0s to 2317 // the next 32-bit boundary. 2318 // Host read operations from these register addresses return 0s. 2319 #define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 2320 #define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF 2321 #define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 2322 2323 //***************************************************************************** 2324 // 2325 // Register: CRYPTO_O_HASHDATAIN10 2326 // 2327 //***************************************************************************** 2328 // Field: [31:0] HASH_DATA_IN 2329 // 2330 // HASH_DATA_IN[351:320] 2331 // These registers must be written with the 512-bit input data. The data lines 2332 // are connected directly to the data input of the hash module and hence into 2333 // the engine's internal data buffer. Writing to each of the registers triggers 2334 // a corresponding 32-bit write enable to the internal buffer. 2335 // Note: The host may only write the input data buffer when 2336 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2337 // is busy with processing. During processing, it is not allowed to write new 2338 // input data. 2339 // For message lengths larger than 64 bytes, multiple blocks of data are 2340 // written to this input buffer using a handshake through flags of the 2341 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2342 // bits in size. If the last block is not 512 bits long, only the least 2343 // significant bits of data must be written, but they must be padded with 0s to 2344 // the next 32-bit boundary. 2345 // Host read operations from these register addresses return 0s. 2346 #define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 2347 #define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF 2348 #define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 2349 2350 //***************************************************************************** 2351 // 2352 // Register: CRYPTO_O_HASHDATAIN11 2353 // 2354 //***************************************************************************** 2355 // Field: [31:0] HASH_DATA_IN 2356 // 2357 // HASH_DATA_IN[383:352] 2358 // These registers must be written with the 512-bit input data. The data lines 2359 // are connected directly to the data input of the hash module and hence into 2360 // the engine's internal data buffer. Writing to each of the registers triggers 2361 // a corresponding 32-bit write enable to the internal buffer. 2362 // Note: The host may only write the input data buffer when 2363 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2364 // is busy with processing. During processing, it is not allowed to write new 2365 // input data. 2366 // For message lengths larger than 64 bytes, multiple blocks of data are 2367 // written to this input buffer using a handshake through flags of the 2368 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2369 // bits in size. If the last block is not 512 bits long, only the least 2370 // significant bits of data must be written, but they must be padded with 0s to 2371 // the next 32-bit boundary. 2372 // Host read operations from these register addresses return 0s. 2373 #define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 2374 #define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF 2375 #define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 2376 2377 //***************************************************************************** 2378 // 2379 // Register: CRYPTO_O_HASHDATAIN12 2380 // 2381 //***************************************************************************** 2382 // Field: [31:0] HASH_DATA_IN 2383 // 2384 // HASH_DATA_IN[415:384] 2385 // These registers must be written with the 512-bit input data. The data lines 2386 // are connected directly to the data input of the hash module and hence into 2387 // the engine's internal data buffer. Writing to each of the registers triggers 2388 // a corresponding 32-bit write enable to the internal buffer. 2389 // Note: The host may only write the input data buffer when 2390 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2391 // is busy with processing. During processing, it is not allowed to write new 2392 // input data. 2393 // For message lengths larger than 64 bytes, multiple blocks of data are 2394 // written to this input buffer using a handshake through flags of the 2395 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2396 // bits in size. If the last block is not 512 bits long, only the least 2397 // significant bits of data must be written, but they must be padded with 0s to 2398 // the next 32-bit boundary. 2399 // Host read operations from these register addresses return 0s. 2400 #define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 2401 #define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF 2402 #define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 2403 2404 //***************************************************************************** 2405 // 2406 // Register: CRYPTO_O_HASHDATAIN13 2407 // 2408 //***************************************************************************** 2409 // Field: [31:0] HASH_DATA_IN 2410 // 2411 // HASH_DATA_IN[447:416] 2412 // These registers must be written with the 512-bit input data. The data lines 2413 // are connected directly to the data input of the hash module and hence into 2414 // the engine's internal data buffer. Writing to each of the registers triggers 2415 // a corresponding 32-bit write enable to the internal buffer. 2416 // Note: The host may only write the input data buffer when 2417 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2418 // is busy with processing. During processing, it is not allowed to write new 2419 // input data. 2420 // For message lengths larger than 64 bytes, multiple blocks of data are 2421 // written to this input buffer using a handshake through flags of the 2422 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2423 // bits in size. If the last block is not 512 bits long, only the least 2424 // significant bits of data must be written, but they must be padded with 0s to 2425 // the next 32-bit boundary. 2426 // Host read operations from these register addresses return 0s. 2427 #define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 2428 #define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF 2429 #define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 2430 2431 //***************************************************************************** 2432 // 2433 // Register: CRYPTO_O_HASHDATAIN14 2434 // 2435 //***************************************************************************** 2436 // Field: [31:0] HASH_DATA_IN 2437 // 2438 // HASH_DATA_IN[479:448] 2439 // These registers must be written with the 512-bit input data. The data lines 2440 // are connected directly to the data input of the hash module and hence into 2441 // the engine's internal data buffer. Writing to each of the registers triggers 2442 // a corresponding 32-bit write enable to the internal buffer. 2443 // Note: The host may only write the input data buffer when 2444 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2445 // is busy with processing. During processing, it is not allowed to write new 2446 // input data. 2447 // For message lengths larger than 64 bytes, multiple blocks of data are 2448 // written to this input buffer using a handshake through flags of the 2449 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2450 // bits in size. If the last block is not 512 bits long, only the least 2451 // significant bits of data must be written, but they must be padded with 0s to 2452 // the next 32-bit boundary. 2453 // Host read operations from these register addresses return 0s. 2454 #define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 2455 #define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF 2456 #define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 2457 2458 //***************************************************************************** 2459 // 2460 // Register: CRYPTO_O_HASHDATAIN15 2461 // 2462 //***************************************************************************** 2463 // Field: [31:0] HASH_DATA_IN 2464 // 2465 // HASH_DATA_IN[511:480] 2466 // These registers must be written with the 512-bit input data. The data lines 2467 // are connected directly to the data input of the hash module and hence into 2468 // the engine's internal data buffer. Writing to each of the registers triggers 2469 // a corresponding 32-bit write enable to the internal buffer. 2470 // Note: The host may only write the input data buffer when 2471 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2472 // is busy with processing. During processing, it is not allowed to write new 2473 // input data. 2474 // For message lengths larger than 64 bytes, multiple blocks of data are 2475 // written to this input buffer using a handshake through flags of the 2476 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2477 // bits in size. If the last block is not 512 bits long, only the least 2478 // significant bits of data must be written, but they must be padded with 0s to 2479 // the next 32-bit boundary. 2480 // Host read operations from these register addresses return 0s. 2481 #define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 2482 #define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF 2483 #define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 2484 2485 //***************************************************************************** 2486 // 2487 // Register: CRYPTO_O_HASHDATAIN16 2488 // 2489 //***************************************************************************** 2490 // Field: [31:0] HASH_DATA_IN 2491 // 2492 // HASH_DATA_IN[543:512] 2493 // These registers must be written with the 512-bit input data. The data lines 2494 // are connected directly to the data input of the hash module and hence into 2495 // the engine's internal data buffer. Writing to each of the registers triggers 2496 // a corresponding 32-bit write enable to the internal buffer. 2497 // Note: The host may only write the input data buffer when 2498 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2499 // is busy with processing. During processing, it is not allowed to write new 2500 // input data. 2501 // For message lengths larger than 64 bytes, multiple blocks of data are 2502 // written to this input buffer using a handshake through flags of the 2503 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2504 // bits in size. If the last block is not 512 bits long, only the least 2505 // significant bits of data must be written, but they must be padded with 0s to 2506 // the next 32-bit boundary. 2507 // Host read operations from these register addresses return 0s. 2508 #define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 2509 #define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF 2510 #define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 2511 2512 //***************************************************************************** 2513 // 2514 // Register: CRYPTO_O_HASHDATAIN17 2515 // 2516 //***************************************************************************** 2517 // Field: [31:0] HASH_DATA_IN 2518 // 2519 // HASH_DATA_IN[575:544] 2520 // These registers must be written with the 512-bit input data. The data lines 2521 // are connected directly to the data input of the hash module and hence into 2522 // the engine's internal data buffer. Writing to each of the registers triggers 2523 // a corresponding 32-bit write enable to the internal buffer. 2524 // Note: The host may only write the input data buffer when 2525 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2526 // is busy with processing. During processing, it is not allowed to write new 2527 // input data. 2528 // For message lengths larger than 64 bytes, multiple blocks of data are 2529 // written to this input buffer using a handshake through flags of the 2530 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2531 // bits in size. If the last block is not 512 bits long, only the least 2532 // significant bits of data must be written, but they must be padded with 0s to 2533 // the next 32-bit boundary. 2534 // Host read operations from these register addresses return 0s. 2535 #define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 2536 #define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF 2537 #define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 2538 2539 //***************************************************************************** 2540 // 2541 // Register: CRYPTO_O_HASHDATAIN18 2542 // 2543 //***************************************************************************** 2544 // Field: [31:0] HASH_DATA_IN 2545 // 2546 // HASH_DATA_IN[607:576] 2547 // These registers must be written with the 512-bit input data. The data lines 2548 // are connected directly to the data input of the hash module and hence into 2549 // the engine's internal data buffer. Writing to each of the registers triggers 2550 // a corresponding 32-bit write enable to the internal buffer. 2551 // Note: The host may only write the input data buffer when 2552 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2553 // is busy with processing. During processing, it is not allowed to write new 2554 // input data. 2555 // For message lengths larger than 64 bytes, multiple blocks of data are 2556 // written to this input buffer using a handshake through flags of the 2557 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2558 // bits in size. If the last block is not 512 bits long, only the least 2559 // significant bits of data must be written, but they must be padded with 0s to 2560 // the next 32-bit boundary. 2561 // Host read operations from these register addresses return 0s. 2562 #define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 2563 #define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF 2564 #define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 2565 2566 //***************************************************************************** 2567 // 2568 // Register: CRYPTO_O_HASHDATAIN19 2569 // 2570 //***************************************************************************** 2571 // Field: [31:0] HASH_DATA_IN 2572 // 2573 // HASH_DATA_IN[639:608] 2574 // These registers must be written with the 512-bit input data. The data lines 2575 // are connected directly to the data input of the hash module and hence into 2576 // the engine's internal data buffer. Writing to each of the registers triggers 2577 // a corresponding 32-bit write enable to the internal buffer. 2578 // Note: The host may only write the input data buffer when 2579 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2580 // is busy with processing. During processing, it is not allowed to write new 2581 // input data. 2582 // For message lengths larger than 64 bytes, multiple blocks of data are 2583 // written to this input buffer using a handshake through flags of the 2584 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2585 // bits in size. If the last block is not 512 bits long, only the least 2586 // significant bits of data must be written, but they must be padded with 0s to 2587 // the next 32-bit boundary. 2588 // Host read operations from these register addresses return 0s. 2589 #define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 2590 #define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF 2591 #define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 2592 2593 //***************************************************************************** 2594 // 2595 // Register: CRYPTO_O_HASHDATAIN20 2596 // 2597 //***************************************************************************** 2598 // Field: [31:0] HASH_DATA_IN 2599 // 2600 // HASH_DATA_IN[671:640] 2601 // These registers must be written with the 512-bit input data. The data lines 2602 // are connected directly to the data input of the hash module and hence into 2603 // the engine's internal data buffer. Writing to each of the registers triggers 2604 // a corresponding 32-bit write enable to the internal buffer. 2605 // Note: The host may only write the input data buffer when 2606 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2607 // is busy with processing. During processing, it is not allowed to write new 2608 // input data. 2609 // For message lengths larger than 64 bytes, multiple blocks of data are 2610 // written to this input buffer using a handshake through flags of the 2611 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2612 // bits in size. If the last block is not 512 bits long, only the least 2613 // significant bits of data must be written, but they must be padded with 0s to 2614 // the next 32-bit boundary. 2615 // Host read operations from these register addresses return 0s. 2616 #define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 2617 #define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF 2618 #define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 2619 2620 //***************************************************************************** 2621 // 2622 // Register: CRYPTO_O_HASHDATAIN21 2623 // 2624 //***************************************************************************** 2625 // Field: [31:0] HASH_DATA_IN 2626 // 2627 // HASH_DATA_IN[703:672] 2628 // These registers must be written with the 512-bit input data. The data lines 2629 // are connected directly to the data input of the hash module and hence into 2630 // the engine's internal data buffer. Writing to each of the registers triggers 2631 // a corresponding 32-bit write enable to the internal buffer. 2632 // Note: The host may only write the input data buffer when 2633 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2634 // is busy with processing. During processing, it is not allowed to write new 2635 // input data. 2636 // For message lengths larger than 64 bytes, multiple blocks of data are 2637 // written to this input buffer using a handshake through flags of the 2638 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2639 // bits in size. If the last block is not 512 bits long, only the least 2640 // significant bits of data must be written, but they must be padded with 0s to 2641 // the next 32-bit boundary. 2642 // Host read operations from these register addresses return 0s. 2643 #define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 2644 #define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF 2645 #define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 2646 2647 //***************************************************************************** 2648 // 2649 // Register: CRYPTO_O_HASHDATAIN22 2650 // 2651 //***************************************************************************** 2652 // Field: [31:0] HASH_DATA_IN 2653 // 2654 // HASH_DATA_IN[735:704] 2655 // These registers must be written with the 512-bit input data. The data lines 2656 // are connected directly to the data input of the hash module and hence into 2657 // the engine's internal data buffer. Writing to each of the registers triggers 2658 // a corresponding 32-bit write enable to the internal buffer. 2659 // Note: The host may only write the input data buffer when 2660 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2661 // is busy with processing. During processing, it is not allowed to write new 2662 // input data. 2663 // For message lengths larger than 64 bytes, multiple blocks of data are 2664 // written to this input buffer using a handshake through flags of the 2665 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2666 // bits in size. If the last block is not 512 bits long, only the least 2667 // significant bits of data must be written, but they must be padded with 0s to 2668 // the next 32-bit boundary. 2669 // Host read operations from these register addresses return 0s. 2670 #define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 2671 #define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF 2672 #define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 2673 2674 //***************************************************************************** 2675 // 2676 // Register: CRYPTO_O_HASHDATAIN23 2677 // 2678 //***************************************************************************** 2679 // Field: [31:0] HASH_DATA_IN 2680 // 2681 // HASH_DATA_IN[767:736] 2682 // These registers must be written with the 512-bit input data. The data lines 2683 // are connected directly to the data input of the hash module and hence into 2684 // the engine's internal data buffer. Writing to each of the registers triggers 2685 // a corresponding 32-bit write enable to the internal buffer. 2686 // Note: The host may only write the input data buffer when 2687 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2688 // is busy with processing. During processing, it is not allowed to write new 2689 // input data. 2690 // For message lengths larger than 64 bytes, multiple blocks of data are 2691 // written to this input buffer using a handshake through flags of the 2692 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2693 // bits in size. If the last block is not 512 bits long, only the least 2694 // significant bits of data must be written, but they must be padded with 0s to 2695 // the next 32-bit boundary. 2696 // Host read operations from these register addresses return 0s. 2697 #define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 2698 #define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF 2699 #define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 2700 2701 //***************************************************************************** 2702 // 2703 // Register: CRYPTO_O_HASHDATAIN24 2704 // 2705 //***************************************************************************** 2706 // Field: [31:0] HASH_DATA_IN 2707 // 2708 // HASH_DATA_IN[799:768] 2709 // These registers must be written with the 512-bit input data. The data lines 2710 // are connected directly to the data input of the hash module and hence into 2711 // the engine's internal data buffer. Writing to each of the registers triggers 2712 // a corresponding 32-bit write enable to the internal buffer. 2713 // Note: The host may only write the input data buffer when 2714 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2715 // is busy with processing. During processing, it is not allowed to write new 2716 // input data. 2717 // For message lengths larger than 64 bytes, multiple blocks of data are 2718 // written to this input buffer using a handshake through flags of the 2719 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2720 // bits in size. If the last block is not 512 bits long, only the least 2721 // significant bits of data must be written, but they must be padded with 0s to 2722 // the next 32-bit boundary. 2723 // Host read operations from these register addresses return 0s. 2724 #define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 2725 #define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF 2726 #define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 2727 2728 //***************************************************************************** 2729 // 2730 // Register: CRYPTO_O_HASHDATAIN25 2731 // 2732 //***************************************************************************** 2733 // Field: [31:0] HASH_DATA_IN 2734 // 2735 // HASH_DATA_IN[831:800] 2736 // These registers must be written with the 512-bit input data. The data lines 2737 // are connected directly to the data input of the hash module and hence into 2738 // the engine's internal data buffer. Writing to each of the registers triggers 2739 // a corresponding 32-bit write enable to the internal buffer. 2740 // Note: The host may only write the input data buffer when 2741 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2742 // is busy with processing. During processing, it is not allowed to write new 2743 // input data. 2744 // For message lengths larger than 64 bytes, multiple blocks of data are 2745 // written to this input buffer using a handshake through flags of the 2746 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2747 // bits in size. If the last block is not 512 bits long, only the least 2748 // significant bits of data must be written, but they must be padded with 0s to 2749 // the next 32-bit boundary. 2750 // Host read operations from these register addresses return 0s. 2751 #define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 2752 #define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF 2753 #define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 2754 2755 //***************************************************************************** 2756 // 2757 // Register: CRYPTO_O_HASHDATAIN26 2758 // 2759 //***************************************************************************** 2760 // Field: [31:0] HASH_DATA_IN 2761 // 2762 // HASH_DATA_IN[863:832] 2763 // These registers must be written with the 512-bit input data. The data lines 2764 // are connected directly to the data input of the hash module and hence into 2765 // the engine's internal data buffer. Writing to each of the registers triggers 2766 // a corresponding 32-bit write enable to the internal buffer. 2767 // Note: The host may only write the input data buffer when 2768 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2769 // is busy with processing. During processing, it is not allowed to write new 2770 // input data. 2771 // For message lengths larger than 64 bytes, multiple blocks of data are 2772 // written to this input buffer using a handshake through flags of the 2773 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2774 // bits in size. If the last block is not 512 bits long, only the least 2775 // significant bits of data must be written, but they must be padded with 0s to 2776 // the next 32-bit boundary. 2777 // Host read operations from these register addresses return 0s. 2778 #define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 2779 #define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF 2780 #define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 2781 2782 //***************************************************************************** 2783 // 2784 // Register: CRYPTO_O_HASHDATAIN27 2785 // 2786 //***************************************************************************** 2787 // Field: [31:0] HASH_DATA_IN 2788 // 2789 // HASH_DATA_IN[895:864] 2790 // These registers must be written with the 512-bit input data. The data lines 2791 // are connected directly to the data input of the hash module and hence into 2792 // the engine's internal data buffer. Writing to each of the registers triggers 2793 // a corresponding 32-bit write enable to the internal buffer. 2794 // Note: The host may only write the input data buffer when 2795 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2796 // is busy with processing. During processing, it is not allowed to write new 2797 // input data. 2798 // For message lengths larger than 64 bytes, multiple blocks of data are 2799 // written to this input buffer using a handshake through flags of the 2800 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2801 // bits in size. If the last block is not 512 bits long, only the least 2802 // significant bits of data must be written, but they must be padded with 0s to 2803 // the next 32-bit boundary. 2804 // Host read operations from these register addresses return 0s. 2805 #define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 2806 #define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF 2807 #define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 2808 2809 //***************************************************************************** 2810 // 2811 // Register: CRYPTO_O_HASHDATAIN28 2812 // 2813 //***************************************************************************** 2814 // Field: [31:0] HASH_DATA_IN 2815 // 2816 // HASH_DATA_IN[923:896] 2817 // These registers must be written with the 512-bit input data. The data lines 2818 // are connected directly to the data input of the hash module and hence into 2819 // the engine's internal data buffer. Writing to each of the registers triggers 2820 // a corresponding 32-bit write enable to the internal buffer. 2821 // Note: The host may only write the input data buffer when 2822 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2823 // is busy with processing. During processing, it is not allowed to write new 2824 // input data. 2825 // For message lengths larger than 64 bytes, multiple blocks of data are 2826 // written to this input buffer using a handshake through flags of the 2827 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2828 // bits in size. If the last block is not 512 bits long, only the least 2829 // significant bits of data must be written, but they must be padded with 0s to 2830 // the next 32-bit boundary. 2831 // Host read operations from these register addresses return 0s. 2832 #define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 2833 #define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF 2834 #define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 2835 2836 //***************************************************************************** 2837 // 2838 // Register: CRYPTO_O_HASHDATAIN29 2839 // 2840 //***************************************************************************** 2841 // Field: [31:0] HASH_DATA_IN 2842 // 2843 // HASH_DATA_IN[959:924] 2844 // These registers must be written with the 512-bit input data. The data lines 2845 // are connected directly to the data input of the hash module and hence into 2846 // the engine's internal data buffer. Writing to each of the registers triggers 2847 // a corresponding 32-bit write enable to the internal buffer. 2848 // Note: The host may only write the input data buffer when 2849 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2850 // is busy with processing. During processing, it is not allowed to write new 2851 // input data. 2852 // For message lengths larger than 64 bytes, multiple blocks of data are 2853 // written to this input buffer using a handshake through flags of the 2854 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2855 // bits in size. If the last block is not 512 bits long, only the least 2856 // significant bits of data must be written, but they must be padded with 0s to 2857 // the next 32-bit boundary. 2858 // Host read operations from these register addresses return 0s. 2859 #define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 2860 #define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF 2861 #define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 2862 2863 //***************************************************************************** 2864 // 2865 // Register: CRYPTO_O_HASHDATAIN30 2866 // 2867 //***************************************************************************** 2868 // Field: [31:0] HASH_DATA_IN 2869 // 2870 // HASH_DATA_IN[991:960] 2871 // These registers must be written with the 512-bit input data. The data lines 2872 // are connected directly to the data input of the hash module and hence into 2873 // the engine's internal data buffer. Writing to each of the registers triggers 2874 // a corresponding 32-bit write enable to the internal buffer. 2875 // Note: The host may only write the input data buffer when 2876 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2877 // is busy with processing. During processing, it is not allowed to write new 2878 // input data. 2879 // For message lengths larger than 64 bytes, multiple blocks of data are 2880 // written to this input buffer using a handshake through flags of the 2881 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2882 // bits in size. If the last block is not 512 bits long, only the least 2883 // significant bits of data must be written, but they must be padded with 0s to 2884 // the next 32-bit boundary. 2885 // Host read operations from these register addresses return 0s. 2886 #define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 2887 #define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF 2888 #define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 2889 2890 //***************************************************************************** 2891 // 2892 // Register: CRYPTO_O_HASHDATAIN31 2893 // 2894 //***************************************************************************** 2895 // Field: [31:0] HASH_DATA_IN 2896 // 2897 // HASH_DATA_IN[1023:992] 2898 // These registers must be written with the 512-bit input data. The data lines 2899 // are connected directly to the data input of the hash module and hence into 2900 // the engine's internal data buffer. Writing to each of the registers triggers 2901 // a corresponding 32-bit write enable to the internal buffer. 2902 // Note: The host may only write the input data buffer when 2903 // HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine 2904 // is busy with processing. During processing, it is not allowed to write new 2905 // input data. 2906 // For message lengths larger than 64 bytes, multiple blocks of data are 2907 // written to this input buffer using a handshake through flags of the 2908 // HASHIOBUFCTRL register. All blocks except the last are required to be 512 2909 // bits in size. If the last block is not 512 bits long, only the least 2910 // significant bits of data must be written, but they must be padded with 0s to 2911 // the next 32-bit boundary. 2912 // Host read operations from these register addresses return 0s. 2913 #define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 2914 #define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF 2915 #define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 2916 2917 //***************************************************************************** 2918 // 2919 // Register: CRYPTO_O_HASHIOBUFCTRL 2920 // 2921 //***************************************************************************** 2922 // Field: [7] PAD_DMA_MESSAGE 2923 // 2924 // Note: This bit must only be used when data is supplied through the DMA. It 2925 // should not be used when data is supplied through the slave interface. 2926 // This bit indicates whether the hash engine has to pad the message, received 2927 // through the DMA and finalize the hash. 2928 // When set to 1, the hash engine pads the last block using the programmed 2929 // length. After padding, the final hash result is calculated. 2930 // When set to 0, the hash engine treats the last written block as block-size 2931 // aligned and calculates the intermediate digest. 2932 // This bit is automatically cleared when the last DMA data block is arrived in 2933 // the hash engine. 2934 #define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 2935 #define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 2936 #define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 2937 #define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 2938 2939 // Field: [6] GET_DIGEST 2940 // 2941 // Note: The bit description below is only applicable when data is sent through 2942 // the slave interface. This bit must be set to 0 when data is received through 2943 // the DMA. 2944 // This bit indicates whether the hash engine should provide the hash digest. 2945 // When provided simultaneously with data_in_av, the hash digest is provided 2946 // after processing the data that is currently in the HASHDATAINn register. 2947 // When provided without data_in_av, the current internal digest buffer value 2948 // is copied to the HASHDIGESTn registers. 2949 // The host must write a 1 to this bit to make the intermediate hash digest 2950 // available. 2951 // Writing 0 to this bit has no effect. 2952 // This bit is automatically cleared (that is, reads 0) when the hash engine 2953 // has processed the contents of the HASHDATAINn register. In the period 2954 // between this bit is set by the host and the actual HASHDATAINn processing, 2955 // this bit reads 1. 2956 #define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 2957 #define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 2958 #define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 2959 #define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 2960 2961 // Field: [5] PAD_MESSAGE 2962 // 2963 // Note: The bit description below is only applicable when data is sent through 2964 // the slave interface. This bit must be set to 0 when data is received through 2965 // the DMA. 2966 // This bit indicates that the HASHDATAINn registers hold the last data of the 2967 // message and hash padding must be applied. 2968 // The host must write this bit to 1 in order to indicate to the hash engine 2969 // that the HASHDATAINn register currently holds the last data of the message. 2970 // When pad_message is set to 1, the hash engine will add padding bits to the 2971 // data currently in the HASHDATAINn register. 2972 // When the last message block is smaller than 512 bits, the pad_message bit 2973 // must be set to 1 together with the data_in_av bit. 2974 // When the last message block is equal to 512 bits, pad_message may be set 2975 // together with data_in_av. In this case the pad_message bit may also be set 2976 // after the last data block has been written to the hash engine (so when the 2977 // rfd_in bit has become 1 again after writing the last data block). 2978 // Writing 0 to this bit has no effect. 2979 // This bit is automatically cleared (i.e. reads 0) by the hash engine. This 2980 // bit reads 1 between the time it was set by the host and the hash engine 2981 // interpreted its value. 2982 #define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 2983 #define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 2984 #define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 2985 #define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 2986 2987 // Field: [2] RFD_IN 2988 // 2989 // Note: The bit description below is only applicable when data is sent through 2990 // the slave interface. This bit can be ignored when data is received through 2991 // the DMA. 2992 // Read-only status of the input buffer of the hash engine. 2993 // When 1, the input buffer of the hash engine can accept new data; the 2994 // HASHDATAINn registers can safely be populated with new data. 2995 // When 0, the input buffer of the hash engine is processing the data that is 2996 // currently in HASHDATAINn; writing new data to these registers is not 2997 // allowed. 2998 #define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 2999 #define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 3000 #define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 3001 #define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 3002 3003 // Field: [1] DATA_IN_AV 3004 // 3005 // Note: The bit description below is only applicable when data is sent through 3006 // the slave interface. This bit must be set to 0 when data is received through 3007 // the DMA. 3008 // This bit indicates that the HASHDATAINn registers contain new input data for 3009 // processing. 3010 // The host must write a 1 to this bit to start processing the data in 3011 // HASHDATAINn; the hash engine will process the new data as soon as it is 3012 // ready for it (rfd_in bit is 1). 3013 // Writing 0 to this bit has no effect. 3014 // This bit is automatically cleared (i.e. reads as 0) when the hash engine 3015 // starts processing the HASHDATAINn contents. This bit reads 1 between the 3016 // time it was set by the host and the hash engine actually starts processing 3017 // the input data block. 3018 #define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 3019 #define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 3020 #define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 3021 #define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 3022 3023 // Field: [0] OUTPUT_FULL 3024 // 3025 // Indicates that the output buffer registers (HASHDIGESTn) are available for 3026 // reading by the host. 3027 // When this bit reads 0, the output buffer registers are released; the hash 3028 // engine is allowed to write new data to it. In this case, the registers 3029 // should not be read by the host. 3030 // When this bit reads 1, the hash engine has stored the result of the latest 3031 // hash operation in the output buffer registers. As long as this bit reads 1, 3032 // the host may read output buffer registers and the hash engine is prevented 3033 // from writing new data to the output buffer. 3034 // After retrieving the hash result data from the output buffer, the host must 3035 // write a 1 to this bit to clear it. This makes the digest output buffer 3036 // available for the hash engine to store new hash results. 3037 // Writing 0 to this bit has no effect. 3038 // Note: If this bit is asserted (1) no new operation should be started before 3039 // the digest is retrieved from the hash engine and this bit is cleared (0). 3040 #define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 3041 #define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 3042 #define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 3043 #define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 3044 3045 //***************************************************************************** 3046 // 3047 // Register: CRYPTO_O_HASHMODE 3048 // 3049 //***************************************************************************** 3050 // Field: [6] SHA384_MODE 3051 // 3052 // The host must write this bit with 1 prior to processing a SHA 384 session. 3053 #define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 3054 #define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 3055 #define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 3056 #define CRYPTO_HASHMODE_SHA384_MODE_S 6 3057 3058 // Field: [5] SHA512_MODE 3059 // 3060 // The host must write this bit with 1 prior to processing a SHA 512 session. 3061 #define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 3062 #define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 3063 #define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 3064 #define CRYPTO_HASHMODE_SHA512_MODE_S 5 3065 3066 // Field: [4] SHA224_MODE 3067 // 3068 // The host must write this bit with 1 prior to processing a SHA 224 session. 3069 #define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 3070 #define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 3071 #define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 3072 #define CRYPTO_HASHMODE_SHA224_MODE_S 4 3073 3074 // Field: [3] SHA256_MODE 3075 // 3076 // The host must write this bit with 1 prior to processing a SHA 256 session. 3077 #define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 3078 #define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 3079 #define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 3080 #define CRYPTO_HASHMODE_SHA256_MODE_S 3 3081 3082 // Field: [0] NEW_HASH 3083 // 3084 // When set to 1, it indicates that the hash engine must start processing a new 3085 // hash session. The [HASHDIGESTn.* ] registers will automatically be loaded 3086 // with the initial hash algorithm constants of the selected hash algorithm. 3087 // When this bit is 0 while the hash processing is started, the initial hash 3088 // algorithm constants are not loaded in the HASHDIGESTn registers. The hash 3089 // engine will start processing with the digest that is currently in its 3090 // internal HASHDIGESTn registers. 3091 // This bit is automatically cleared when hash processing is started. 3092 #define CRYPTO_HASHMODE_NEW_HASH 0x00000001 3093 #define CRYPTO_HASHMODE_NEW_HASH_BITN 0 3094 #define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 3095 #define CRYPTO_HASHMODE_NEW_HASH_S 0 3096 3097 //***************************************************************************** 3098 // 3099 // Register: CRYPTO_O_HASHINLENL 3100 // 3101 //***************************************************************************** 3102 // Field: [31:0] LENGTH_IN 3103 // 3104 // LENGTH_IN[31:0] 3105 // Message length registers. The content of these registers is used by the hash 3106 // engine during the message padding phase of the hash session. The data lines 3107 // of this registers are directly connected to the interface of the hash 3108 // engine. 3109 // For a write operation by the host, these registers should be written with 3110 // the message length in bits. 3111 // 3112 // Final hash operations: 3113 // The total input data length must be programmed for new hash operations that 3114 // require finalization (padding). The input data must be provided through the 3115 // slave or DMA interface. 3116 // 3117 // Continued hash operations (finalized): 3118 // For continued hash operations that require finalization, the total message 3119 // length must be programmed, including the length of previously hashed data 3120 // that corresponds to the written input digest. 3121 // 3122 // Non-final hash operations: 3123 // For hash operations that do not require finalization (input data length is 3124 // multiple of 512-bits which is SHA-256 data block size), the length field 3125 // does not need to be programmed since not used by the operation. 3126 // 3127 // If the message length in bits is below (2^32-1), then only this register 3128 // needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s 3129 // in this case. 3130 // The host may write the length register at any time during the hash session 3131 // when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written 3132 // before the last data of the active hash session is written into the hash 3133 // engine. 3134 // host read operations from these register locations will return 0s. 3135 // Note: When getting data from DMA, this register must be programmed before 3136 // DMA is programmed to start. 3137 #define CRYPTO_HASHINLENL_LENGTH_IN_W 32 3138 #define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF 3139 #define CRYPTO_HASHINLENL_LENGTH_IN_S 0 3140 3141 //***************************************************************************** 3142 // 3143 // Register: CRYPTO_O_HASHINLENH 3144 // 3145 //***************************************************************************** 3146 // Field: [31:0] LENGTH_IN 3147 // 3148 // LENGTH_IN[63:32] 3149 // Message length registers. The content of these registers is used by the hash 3150 // engine during the message padding phase of the hash session. The data lines 3151 // of this registers are directly connected to the interface of the hash 3152 // engine. 3153 // For a write operation by the host, these registers should be written with 3154 // the message length in bits. 3155 // 3156 // Final hash operations: 3157 // The total input data length must be programmed for new hash operations that 3158 // require finalization (padding). The input data must be provided through the 3159 // slave or DMA interface. 3160 // 3161 // Continued hash operations (finalized): 3162 // For continued hash operations that require finalization, the total message 3163 // length must be programmed, including the length of previously hashed data 3164 // that corresponds to the written input digest. 3165 // 3166 // Non-final hash operations: 3167 // For hash operations that do not require finalization (input data length is 3168 // multiple of 512-bits which is SHA-256 data block size), the length field 3169 // does not need to be programmed since not used by the operation. 3170 // 3171 // If the message length in bits is below (2^32-1), then only HASHINLENL needs 3172 // to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in 3173 // this case. 3174 // The host may write the length register at any time during the hash session 3175 // when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written 3176 // before the last data of the active hash session is written into the hash 3177 // engine. 3178 // host read operations from these register locations will return 0s. 3179 // Note: When getting data from DMA, this register must be programmed before 3180 // DMA is programmed to start. 3181 #define CRYPTO_HASHINLENH_LENGTH_IN_W 32 3182 #define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF 3183 #define CRYPTO_HASHINLENH_LENGTH_IN_S 0 3184 3185 //***************************************************************************** 3186 // 3187 // Register: CRYPTO_O_HASHDIGESTA 3188 // 3189 //***************************************************************************** 3190 // Field: [31:0] HASH_DIGEST 3191 // 3192 // HASH_DIGEST[31:0] 3193 // Hash digest registers 3194 // Write operation: 3195 // 3196 // Continued hash: 3197 // These registers should be written with the context data, before the start of 3198 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3199 // session). 3200 // 3201 // New hash: 3202 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3203 // internal digest registers are automatically set to the SHA-256 algorithm 3204 // constant and these register should not be written. 3205 // 3206 // Reading from these registers provides the intermediate hash result 3207 // (non-final hash operation) or the final hash result (final hash operation) 3208 // after data processing. 3209 #define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 3210 #define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF 3211 #define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 3212 3213 //***************************************************************************** 3214 // 3215 // Register: CRYPTO_O_HASHDIGESTB 3216 // 3217 //***************************************************************************** 3218 // Field: [31:0] HASH_DIGEST 3219 // 3220 // HASH_DIGEST[63:32] 3221 // Hash digest registers 3222 // Write operation: 3223 // 3224 // Continued hash: 3225 // These registers should be written with the context data, before the start of 3226 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3227 // session). 3228 // 3229 // New hash: 3230 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3231 // internal digest registers are automatically set to the SHA-256 algorithm 3232 // constant and these register should not be written. 3233 // 3234 // Reading from these registers provides the intermediate hash result 3235 // (non-final hash operation) or the final hash result (final hash operation) 3236 // after data processing. 3237 #define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 3238 #define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF 3239 #define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 3240 3241 //***************************************************************************** 3242 // 3243 // Register: CRYPTO_O_HASHDIGESTC 3244 // 3245 //***************************************************************************** 3246 // Field: [31:0] HASH_DIGEST 3247 // 3248 // HASH_DIGEST[95:64] 3249 // Hash digest registers 3250 // Write operation: 3251 // 3252 // Continued hash: 3253 // These registers should be written with the context data, before the start of 3254 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3255 // session). 3256 // 3257 // New hash: 3258 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3259 // internal digest registers are automatically set to the SHA-256 algorithm 3260 // constant and these register should not be written. 3261 // 3262 // Reading from these registers provides the intermediate hash result 3263 // (non-final hash operation) or the final hash result (final hash operation) 3264 // after data processing. 3265 #define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 3266 #define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF 3267 #define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 3268 3269 //***************************************************************************** 3270 // 3271 // Register: CRYPTO_O_HASHDIGESTD 3272 // 3273 //***************************************************************************** 3274 // Field: [31:0] HASH_DIGEST 3275 // 3276 // HASH_DIGEST[127:96] 3277 // Hash digest registers 3278 // Write operation: 3279 // 3280 // Continued hash: 3281 // These registers should be written with the context data, before the start of 3282 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3283 // session). 3284 // 3285 // New hash: 3286 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3287 // internal digest registers are automatically set to the SHA-256 algorithm 3288 // constant and these register should not be written. 3289 // 3290 // Reading from these registers provides the intermediate hash result 3291 // (non-final hash operation) or the final hash result (final hash operation) 3292 // after data processing. 3293 #define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 3294 #define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF 3295 #define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 3296 3297 //***************************************************************************** 3298 // 3299 // Register: CRYPTO_O_HASHDIGESTE 3300 // 3301 //***************************************************************************** 3302 // Field: [31:0] HASH_DIGEST 3303 // 3304 // HASH_DIGEST[159:128] 3305 // Hash digest registers 3306 // Write operation: 3307 // 3308 // Continued hash: 3309 // These registers should be written with the context data, before the start of 3310 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3311 // session). 3312 // 3313 // New hash: 3314 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3315 // internal digest registers are automatically set to the SHA-256 algorithm 3316 // constant and these register should not be written. 3317 // 3318 // Reading from these registers provides the intermediate hash result 3319 // (non-final hash operation) or the final hash result (final hash operation) 3320 // after data processing. 3321 #define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 3322 #define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF 3323 #define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 3324 3325 //***************************************************************************** 3326 // 3327 // Register: CRYPTO_O_HASHDIGESTF 3328 // 3329 //***************************************************************************** 3330 // Field: [31:0] HASH_DIGEST 3331 // 3332 // HASH_DIGEST[191:160] 3333 // Hash digest registers 3334 // Write operation: 3335 // 3336 // Continued hash: 3337 // These registers should be written with the context data, before the start of 3338 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3339 // session). 3340 // 3341 // New hash: 3342 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3343 // internal digest registers are automatically set to the SHA-256 algorithm 3344 // constant and these register should not be written. 3345 // 3346 // Reading from these registers provides the intermediate hash result 3347 // (non-final hash operation) or the final hash result (final hash operation) 3348 // after data processing. 3349 #define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 3350 #define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF 3351 #define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 3352 3353 //***************************************************************************** 3354 // 3355 // Register: CRYPTO_O_HASHDIGESTG 3356 // 3357 //***************************************************************************** 3358 // Field: [31:0] HASH_DIGEST 3359 // 3360 // HASH_DIGEST[223:192] 3361 // Hash digest registers 3362 // Write operation: 3363 // 3364 // Continued hash: 3365 // These registers should be written with the context data, before the start of 3366 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3367 // session). 3368 // 3369 // New hash: 3370 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3371 // internal digest registers are automatically set to the SHA-256 algorithm 3372 // constant and these register should not be written. 3373 // 3374 // Reading from these registers provides the intermediate hash result 3375 // (non-final hash operation) or the final hash result (final hash operation) 3376 // after data processing. 3377 #define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 3378 #define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF 3379 #define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 3380 3381 //***************************************************************************** 3382 // 3383 // Register: CRYPTO_O_HASHDIGESTH 3384 // 3385 //***************************************************************************** 3386 // Field: [31:0] HASH_DIGEST 3387 // 3388 // HASH_DIGEST[255:224] 3389 // Hash digest registers 3390 // Write operation: 3391 // 3392 // Continued hash: 3393 // These registers should be written with the context data, before the start of 3394 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3395 // session). 3396 // 3397 // New hash: 3398 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3399 // internal digest registers are automatically set to the SHA-256 algorithm 3400 // constant and these register should not be written. 3401 // 3402 // Reading from these registers provides the intermediate hash result 3403 // (non-final hash operation) or the final hash result (final hash operation) 3404 // after data processing. 3405 #define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 3406 #define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF 3407 #define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 3408 3409 //***************************************************************************** 3410 // 3411 // Register: CRYPTO_O_HASHDIGESTI 3412 // 3413 //***************************************************************************** 3414 // Field: [31:0] HASH_DIGEST 3415 // 3416 // HASH_DIGEST[287:256] 3417 // Hash digest registers 3418 // Write operation: 3419 // 3420 // Continued hash: 3421 // These registers should be written with the context data, before the start of 3422 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3423 // session). 3424 // 3425 // New hash: 3426 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3427 // internal digest registers are automatically set to the SHA-256 algorithm 3428 // constant and these register should not be written. 3429 // 3430 // Reading from these registers provides the intermediate hash result 3431 // (non-final hash operation) or the final hash result (final hash operation) 3432 // after data processing. 3433 #define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 3434 #define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF 3435 #define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 3436 3437 //***************************************************************************** 3438 // 3439 // Register: CRYPTO_O_HASHDIGESTJ 3440 // 3441 //***************************************************************************** 3442 // Field: [31:0] HASH_DIGEST 3443 // 3444 // HASH_DIGEST[319:288] 3445 // Hash digest registers 3446 // Write operation: 3447 // 3448 // Continued hash: 3449 // These registers should be written with the context data, before the start of 3450 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3451 // session). 3452 // 3453 // New hash: 3454 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3455 // internal digest registers are automatically set to the SHA-256 algorithm 3456 // constant and these register should not be written. 3457 // 3458 // Reading from these registers provides the intermediate hash result 3459 // (non-final hash operation) or the final hash result (final hash operation) 3460 // after data processing. 3461 #define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 3462 #define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF 3463 #define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 3464 3465 //***************************************************************************** 3466 // 3467 // Register: CRYPTO_O_HASHDIGESTK 3468 // 3469 //***************************************************************************** 3470 // Field: [31:0] HASH_DIGEST 3471 // 3472 // HASH_DIGEST[351:320] 3473 // Hash digest registers 3474 // Write operation: 3475 // 3476 // Continued hash: 3477 // These registers should be written with the context data, before the start of 3478 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3479 // session). 3480 // 3481 // New hash: 3482 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3483 // internal digest registers are automatically set to the SHA-256 algorithm 3484 // constant and these register should not be written. 3485 // 3486 // Reading from these registers provides the intermediate hash result 3487 // (non-final hash operation) or the final hash result (final hash operation) 3488 // after data processing. 3489 #define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 3490 #define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF 3491 #define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 3492 3493 //***************************************************************************** 3494 // 3495 // Register: CRYPTO_O_HASHDIGESTL 3496 // 3497 //***************************************************************************** 3498 // Field: [31:0] HASH_DIGEST 3499 // 3500 // HASH_DIGEST[383:352] 3501 // Hash digest registers 3502 // Write operation: 3503 // 3504 // Continued hash: 3505 // These registers should be written with the context data, before the start of 3506 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3507 // session). 3508 // 3509 // New hash: 3510 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3511 // internal digest registers are automatically set to the SHA-256 algorithm 3512 // constant and these register should not be written. 3513 // 3514 // Reading from these registers provides the intermediate hash result 3515 // (non-final hash operation) or the final hash result (final hash operation) 3516 // after data processing. 3517 #define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 3518 #define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF 3519 #define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 3520 3521 //***************************************************************************** 3522 // 3523 // Register: CRYPTO_O_HASHDIGESTM 3524 // 3525 //***************************************************************************** 3526 // Field: [31:0] HASH_DIGEST 3527 // 3528 // HASH_DIGEST[415:384] 3529 // Hash digest registers 3530 // Write operation: 3531 // 3532 // Continued hash: 3533 // These registers should be written with the context data, before the start of 3534 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3535 // session). 3536 // 3537 // New hash: 3538 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3539 // internal digest registers are automatically set to the SHA-256 algorithm 3540 // constant and these register should not be written. 3541 // 3542 // Reading from these registers provides the intermediate hash result 3543 // (non-final hash operation) or the final hash result (final hash operation) 3544 // after data processing. 3545 #define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 3546 #define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF 3547 #define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 3548 3549 //***************************************************************************** 3550 // 3551 // Register: CRYPTO_O_HASHDIGESTN 3552 // 3553 //***************************************************************************** 3554 // Field: [31:0] HASH_DIGEST 3555 // 3556 // HASH_DIGEST[447:416] 3557 // Hash digest registers 3558 // Write operation: 3559 // 3560 // Continued hash: 3561 // These registers should be written with the context data, before the start of 3562 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3563 // session). 3564 // 3565 // New hash: 3566 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3567 // internal digest registers are automatically set to the SHA-256 algorithm 3568 // constant and these register should not be written. 3569 // 3570 // Reading from these registers provides the intermediate hash result 3571 // (non-final hash operation) or the final hash result (final hash operation) 3572 // after data processing. 3573 #define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 3574 #define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF 3575 #define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 3576 3577 //***************************************************************************** 3578 // 3579 // Register: CRYPTO_O_HASHDIGESTO 3580 // 3581 //***************************************************************************** 3582 // Field: [31:0] HASH_DIGEST 3583 // 3584 // HASH_DIGEST[479:448] 3585 // Hash digest registers 3586 // Write operation: 3587 // 3588 // Continued hash: 3589 // These registers should be written with the context data, before the start of 3590 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3591 // session). 3592 // 3593 // New hash: 3594 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3595 // internal digest registers are automatically set to the SHA-256 algorithm 3596 // constant and these register should not be written. 3597 // 3598 // Reading from these registers provides the intermediate hash result 3599 // (non-final hash operation) or the final hash result (final hash operation) 3600 // after data processing. 3601 #define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 3602 #define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF 3603 #define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 3604 3605 //***************************************************************************** 3606 // 3607 // Register: CRYPTO_O_HASHDIGESTP 3608 // 3609 //***************************************************************************** 3610 // Field: [31:0] HASH_DIGEST 3611 // 3612 // HASH_DIGEST[511:480] 3613 // Hash digest registers 3614 // Write operation: 3615 // 3616 // Continued hash: 3617 // These registers should be written with the context data, before the start of 3618 // a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash 3619 // session). 3620 // 3621 // New hash: 3622 // When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the 3623 // internal digest registers are automatically set to the SHA-256 algorithm 3624 // constant and these register should not be written. 3625 // 3626 // Reading from these registers provides the intermediate hash result 3627 // (non-final hash operation) or the final hash result (final hash operation) 3628 // after data processing. 3629 #define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 3630 #define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF 3631 #define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 3632 3633 //***************************************************************************** 3634 // 3635 // Register: CRYPTO_O_ALGSEL 3636 // 3637 //***************************************************************************** 3638 // Field: [32] HASH_SHA_512 3639 // 3640 // If set to one, selects the hash engine in 512B mode as destination for the 3641 // DMA 3642 // The maximum transfer size to DMA engine is set to 64 bytes for reading and 3643 // 32 bytes for writing (the latter is only applicable if the hash result is 3644 // written out through the DMA). 3645 #define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 3646 #define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 3647 #define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 3648 #define CRYPTO_ALGSEL_HASH_SHA_512_S 32 3649 3650 // Field: [31] TAG 3651 // 3652 // If this bit is cleared to 0, the DMA operation involves only data. 3653 // If this bit is set, the DMA operation includes a TAG (Authentication Result 3654 // / Digest). 3655 // For SHA-256 operation, a DMA must be set up for both input data and TAG. For 3656 // any other selected module, setting this bit only allows a DMA that reads the 3657 // TAG. No data allowed to be transferred to or from the selected module via 3658 // the DMA. 3659 #define CRYPTO_ALGSEL_TAG 0x80000000 3660 #define CRYPTO_ALGSEL_TAG_BITN 31 3661 #define CRYPTO_ALGSEL_TAG_M 0x80000000 3662 #define CRYPTO_ALGSEL_TAG_S 31 3663 3664 // Field: [2] HASH_SHA_256 3665 // 3666 // If set to one, selects the hash engine in 256B mode as destination for the 3667 // DMA 3668 // The maximum transfer size to DMA engine is set to 64 bytes for reading and 3669 // 32 bytes for writing (the latter is only applicable if the hash result is 3670 // written out through the DMA). 3671 #define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 3672 #define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 3673 #define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 3674 #define CRYPTO_ALGSEL_HASH_SHA_256_S 2 3675 3676 // Field: [1] AES 3677 // 3678 // If set to one, selects the AES engine as source/destination for the DMA 3679 // The read and write maximum transfer size to the DMA engine is set to 16 3680 // bytes. 3681 #define CRYPTO_ALGSEL_AES 0x00000002 3682 #define CRYPTO_ALGSEL_AES_BITN 1 3683 #define CRYPTO_ALGSEL_AES_M 0x00000002 3684 #define CRYPTO_ALGSEL_AES_S 1 3685 3686 // Field: [0] KEY_STORE 3687 // 3688 // If set to one, selects the Key Store as destination for the DMA 3689 // The maximum transfer size to DMA engine is set to 32 bytes (however 3690 // transfers of 16, 24 and 32 bytes are allowed) 3691 #define CRYPTO_ALGSEL_KEY_STORE 0x00000001 3692 #define CRYPTO_ALGSEL_KEY_STORE_BITN 0 3693 #define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 3694 #define CRYPTO_ALGSEL_KEY_STORE_S 0 3695 3696 //***************************************************************************** 3697 // 3698 // Register: CRYPTO_O_DMAPROTCTL 3699 // 3700 //***************************************************************************** 3701 // Field: [0] PROT_EN 3702 // 3703 // Select AHB transfer protection control for DMA transfers using the key store 3704 // area as destination. 3705 // 0 : transfers use 'USER' type access. 3706 // 1 : transfers use 'PRIVILEGED' type access. 3707 #define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 3708 #define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 3709 #define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 3710 #define CRYPTO_DMAPROTCTL_PROT_EN_S 0 3711 3712 //***************************************************************************** 3713 // 3714 // Register: CRYPTO_O_SWRESET 3715 // 3716 //***************************************************************************** 3717 // Field: [0] SW_RESET 3718 // 3719 // If this bit is set to 1, the following modules are reset: 3720 // - Master control internal state is reset. That includes interrupt, error 3721 // status register, and result available interrupt generation FSM. 3722 // - Key store module state is reset. That includes clearing the written area 3723 // flags; therefore, the keys must be reloaded to the key store module. 3724 // Writing 0 has no effect. 3725 // The bit is self cleared after executing the reset. 3726 #define CRYPTO_SWRESET_SW_RESET 0x00000001 3727 #define CRYPTO_SWRESET_SW_RESET_BITN 0 3728 #define CRYPTO_SWRESET_SW_RESET_M 0x00000001 3729 #define CRYPTO_SWRESET_SW_RESET_S 0 3730 3731 //***************************************************************************** 3732 // 3733 // Register: CRYPTO_O_IRQTYPE 3734 // 3735 //***************************************************************************** 3736 // Field: [0] LEVEL 3737 // 3738 // If this bit is 0, the interrupt output is a pulse. 3739 // If this bit is set to 1, the interrupt is a level interrupt that must be 3740 // cleared by writing the interrupt clear register. 3741 // This bit is applicable for both interrupt output signals. 3742 #define CRYPTO_IRQTYPE_LEVEL 0x00000001 3743 #define CRYPTO_IRQTYPE_LEVEL_BITN 0 3744 #define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 3745 #define CRYPTO_IRQTYPE_LEVEL_S 0 3746 3747 //***************************************************************************** 3748 // 3749 // Register: CRYPTO_O_IRQEN 3750 // 3751 //***************************************************************************** 3752 // Field: [1] DMA_IN_DONE 3753 // 3754 // If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt 3755 // output is disabled and remains 0. 3756 // If this bit is set to 1, the DMA input done interrupt output is enabled. 3757 #define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 3758 #define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 3759 #define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 3760 #define CRYPTO_IRQEN_DMA_IN_DONE_S 1 3761 3762 // Field: [0] RESULT_AVAIL 3763 // 3764 // If this bit is set to 0, the result available (irq_result_av) interrupt 3765 // output is disabled and remains 0. 3766 // If this bit is set to 1, the result available interrupt output is enabled. 3767 #define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 3768 #define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 3769 #define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 3770 #define CRYPTO_IRQEN_RESULT_AVAIL_S 0 3771 3772 //***************************************************************************** 3773 // 3774 // Register: CRYPTO_O_IRQCLR 3775 // 3776 //***************************************************************************** 3777 // Field: [31] DMA_BUS_ERR 3778 // 3779 // If 1 is written to this bit, the DMA bus error status is cleared. 3780 // Writing 0 has no effect. 3781 #define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 3782 #define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 3783 #define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 3784 #define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 3785 3786 // Field: [30] KEY_ST_WR_ERR 3787 // 3788 // If 1 is written to this bit, the key store write error status is cleared. 3789 // Writing 0 has no effect. 3790 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 3791 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 3792 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 3793 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 3794 3795 // Field: [29] KEY_ST_RD_ERR 3796 // 3797 // If 1 is written to this bit, the key store read error status is cleared. 3798 // Writing 0 has no effect. 3799 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 3800 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 3801 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 3802 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 3803 3804 // Field: [1] DMA_IN_DONE 3805 // 3806 // If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt 3807 // output is cleared. 3808 // Writing 0 has no effect. 3809 // Note that clearing an interrupt makes sense only if the interrupt output is 3810 // programmed as level (refer to IRQTYPE). 3811 #define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 3812 #define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 3813 #define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 3814 #define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 3815 3816 // Field: [0] RESULT_AVAIL 3817 // 3818 // If 1 is written to this bit, the result available (irq_result_av) interrupt 3819 // output is cleared. 3820 // Writing 0 has no effect. 3821 // Note that clearing an interrupt makes sense only if the interrupt output is 3822 // programmed as level (refer to IRQTYPE). 3823 #define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 3824 #define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 3825 #define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 3826 #define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 3827 3828 //***************************************************************************** 3829 // 3830 // Register: CRYPTO_O_IRQSET 3831 // 3832 //***************************************************************************** 3833 // Field: [1] DMA_IN_DONE 3834 // 3835 // If 1 is written to this bit, the DMA data in done (irq_dma_in_done) 3836 // interrupt output is set to one. 3837 // Writing 0 has no effect. 3838 // If the interrupt configuration register is programmed to pulse, clearing the 3839 // DMA data in done (irq_dma_in_done) interrupt is not needed. If it is 3840 // programmed to level, clearing the interrupt output should be done by writing 3841 // the interrupt clear register (IRQCLR.DMA_IN_DONE). 3842 #define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 3843 #define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 3844 #define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 3845 #define CRYPTO_IRQSET_DMA_IN_DONE_S 1 3846 3847 // Field: [0] RESULT_AVAIL 3848 // 3849 // If 1 is written to this bit, the result available (irq_result_av) interrupt 3850 // output is set to one. 3851 // Writing 0 has no effect. 3852 // If the interrupt configuration register is programmed to pulse, clearing the 3853 // result available (irq_result_av) interrupt is not needed. If it is 3854 // programmed to level, clearing the interrupt output should be done by writing 3855 // the interrupt clear register (IRQCLR.RESULT_AVAIL). 3856 #define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 3857 #define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 3858 #define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 3859 #define CRYPTO_IRQSET_RESULT_AVAIL_S 0 3860 3861 //***************************************************************************** 3862 // 3863 // Register: CRYPTO_O_IRQSTAT 3864 // 3865 //***************************************************************************** 3866 // Field: [31] DMA_BUS_ERR 3867 // 3868 // This bit is set when a DMA bus error is detected during a DMA operation. The 3869 // value of this register is held until it is cleared through the 3870 // IRQCLR.DMA_BUS_ERR 3871 // Note: This error is asserted if an error is detected on the AHB master 3872 // interface during a DMA operation. 3873 #define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 3874 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 3875 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 3876 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 3877 3878 // Field: [30] KEY_ST_WR_ERR 3879 // 3880 // This bit is set when a write error is detected during the DMA write 3881 // operation to the key store memory. The value of this register is held until 3882 // it is cleared through the IRQCLR.KEY_ST_WR_ERR register. 3883 // Note: This error is asserted if a DMA operation does not cover a full key 3884 // area or more areas are written than expected. 3885 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 3886 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 3887 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 3888 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 3889 3890 // Field: [29] KEY_ST_RD_ERR 3891 // 3892 // This bit is set when a read error is detected during the read of a key from 3893 // the key store, while copying it to the AES core. The value of this register 3894 // is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. 3895 // Note: This error is asserted if a key location is selected in the key store 3896 // that is not available. 3897 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 3898 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 3899 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 3900 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 3901 3902 // Field: [1] DMA_IN_DONE 3903 // 3904 // This read only bit returns the actual DMA data in done (irq_data_in_done) 3905 // interrupt status of the DMA data in done interrupt output pin 3906 // (irq_data_in_done). 3907 #define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 3908 #define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 3909 #define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 3910 #define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 3911 3912 // Field: [0] RESULT_AVAIL 3913 // 3914 // This read only bit returns the actual result available (irq_result_av) 3915 // interrupt status of the result available interrupt output pin 3916 // (irq_result_av). 3917 #define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 3918 #define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 3919 #define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 3920 #define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 3921 3922 //***************************************************************************** 3923 // 3924 // Register: CRYPTO_O_HWVER 3925 // 3926 //***************************************************************************** 3927 // Field: [27:24] HW_MAJOR_VER 3928 // 3929 // Major version number 3930 #define CRYPTO_HWVER_HW_MAJOR_VER_W 4 3931 #define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 3932 #define CRYPTO_HWVER_HW_MAJOR_VER_S 24 3933 3934 // Field: [23:20] HW_MINOR_VER 3935 // 3936 // Minor version number 3937 #define CRYPTO_HWVER_HW_MINOR_VER_W 4 3938 #define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 3939 #define CRYPTO_HWVER_HW_MINOR_VER_S 20 3940 3941 // Field: [19:16] HW_PATCH_LVL 3942 // 3943 // Patch level 3944 // Starts at 0 at first delivery of this version 3945 #define CRYPTO_HWVER_HW_PATCH_LVL_W 4 3946 #define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 3947 #define CRYPTO_HWVER_HW_PATCH_LVL_S 16 3948 3949 // Field: [15:8] VER_NUM_COMPL 3950 // 3951 // These bits simply contain the complement of bits [7:0] (0x87), used by a 3952 // driver to ascertain that the EIP-120t register is indeed read. 3953 #define CRYPTO_HWVER_VER_NUM_COMPL_W 8 3954 #define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 3955 #define CRYPTO_HWVER_VER_NUM_COMPL_S 8 3956 3957 // Field: [7:0] VER_NUM 3958 // 3959 // These bits encode the EIP number for the EIP-120t, this field contains the 3960 // value 120 (decimal) or 0x78. 3961 #define CRYPTO_HWVER_VER_NUM_W 8 3962 #define CRYPTO_HWVER_VER_NUM_M 0x000000FF 3963 #define CRYPTO_HWVER_VER_NUM_S 0 3964 3965 3966 #endif // __CRYPTO__ 3967
