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Searched refs:CRYPTO_BASE (Results 1 – 7 of 7) sorted by relevance

/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dcrypto.c102 HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); in CRYPTOAesLoadKey()
105 HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; in CRYPTOAesLoadKey()
106 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | in CRYPTOAesLoadKey()
110 HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; in CRYPTOAesLoadKey()
113 HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | in CRYPTOAesLoadKey()
119 if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { in CRYPTOAesLoadKey()
120 HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; in CRYPTOAesLoadKey()
124 HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); in CRYPTOAesLoadKey()
127 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in CRYPTOAesLoadKey()
130 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; in CRYPTOAesLoadKey()
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Daes.c79 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; in AESSetInitializationVector()
80 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; in AESSetInitializationVector()
81 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; in AESSetInitializationVector()
82 HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; in AESSetInitializationVector()
94 …HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; … in AESStartDMAOperation()
96 …while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESUL… in AESStartDMAOperation()
99 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in AESStartDMAOperation()
102 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; in AESStartDMAOperation()
105 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; in AESStartDMAOperation()
110 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in AESStartDMAOperation()
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Dsha2.c75 … HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; in SHA2StartDMAOperation()
77 …while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESUL… in SHA2StartDMAOperation()
81 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; in SHA2StartDMAOperation()
84 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; in SHA2StartDMAOperation()
87 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; in SHA2StartDMAOperation()
92 HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; in SHA2StartDMAOperation()
95 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; in SHA2StartDMAOperation()
98 HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; in SHA2StartDMAOperation()
115 …while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_… in SHA2WaitForIRQFlags()
118 irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); in SHA2WaitForIRQFlags()
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Dsha2.h462 HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; in SHA2SelectAlgorithm()
486 HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = length; in SHA2SetMessageLength()
518 HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i]; in SHA2SetDigest()
550 if (HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) & CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M) { in SHA2GetDigest()
557 digest[i] = HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))); in SHA2GetDigest()
570 HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL); in SHA2ClearDigestAvailableFlag()
595 HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; in SHA2IntEnable()
598 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in SHA2IntEnable()
623 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in SHA2IntDisable()
642 mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in SHA2IntStatusMasked()
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Daes.h488 HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); in AESInvalidateKey()
511 HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; in AESSelectAlgorithm()
529 HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; in AESSetCtrl()
556 HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; in AESSetDataLength()
557 HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; in AESSetDataLength()
583 HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; in AESSetAuthLength()
596 HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; in AESReset()
621 HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; in AESIntEnable()
624 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; in AESIntEnable()
649 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; in AESIntDisable()
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Dcrypto.h356 HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; in CRYPTOAesEcbFinish()
357 HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; in CRYPTOAesEcbFinish()
377 HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; in CRYPTOAesCbcFinish()
378 HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; in CRYPTOAesCbcFinish()
557 return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT)); in CRYPTODmaStatus()
613 HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; in CRYPTOIntEnable()
616 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; in CRYPTOIntEnable()
642 HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; in CRYPTOIntDisable()
671 ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); in CRYPTOIntStatus()
672 return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); in CRYPTOIntStatus()
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/hal_ti-2.7.6/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_memmap.h64 #define CRYPTO_BASE 0x40024000 // CRYPTO macro