Searched refs:AUX_ANAIF_BASE (Results 1 – 3 of 3) sorted by relevance
99 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCDisable()100 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCDisable()106 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; in AUXADCDisable()129 …HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCT… in AUXADCEnableAsync()133 …HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_… in AUXADCEnableAsync()167 …HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCT… in AUXADCEnableSync()171 …HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_… in AUXADCEnableSync()200 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) in AUXADCFlushFifo()201 HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) in AUXADCFlushFifo()213 while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); in AUXADCReadFifo()[all …]
313 HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; in AUXADCGenManualTrigger()335 return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); in AUXADCGetFifoStatus()
96 #define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF macro
