1 /****************************************************************************** 2 * Filename: hw_aon_rtc_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_RTC_H__ 38 #define __HW_AON_RTC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_RTC component 44 // 45 //***************************************************************************** 46 // Control 47 #define AON_RTC_O_CTL 0x00000000 48 49 // Event Flags, RTC Status 50 #define AON_RTC_O_EVFLAGS 0x00000004 51 52 // Second Counter Value, Integer Part 53 #define AON_RTC_O_SEC 0x00000008 54 55 // Second Counter Value, Fractional Part 56 #define AON_RTC_O_SUBSEC 0x0000000C 57 58 // Subseconds Increment 59 #define AON_RTC_O_SUBSECINC 0x00000010 60 61 // Channel Configuration 62 #define AON_RTC_O_CHCTL 0x00000014 63 64 // Channel 0 Compare Value 65 #define AON_RTC_O_CH0CMP 0x00000018 66 67 // Channel 1 Compare Value 68 #define AON_RTC_O_CH1CMP 0x0000001C 69 70 // Channel 2 Compare Value 71 #define AON_RTC_O_CH2CMP 0x00000020 72 73 // Channel 2 Compare Value Auto-increment 74 #define AON_RTC_O_CH2CMPINC 0x00000024 75 76 // Channel 1 Capture Value 77 #define AON_RTC_O_CH1CAPT 0x00000028 78 79 // AON Synchronization 80 #define AON_RTC_O_SYNC 0x0000002C 81 82 // Current Counter Value 83 #define AON_RTC_O_TIME 0x00000030 84 85 // Synchronization to SCLK_LF 86 #define AON_RTC_O_SYNCLF 0x00000034 87 88 //***************************************************************************** 89 // 90 // Register: AON_RTC_O_CTL 91 // 92 //***************************************************************************** 93 // Field: [18:16] COMB_EV_MASK 94 // 95 // Eventmask selecting which delayed events that form the combined event. 96 // ENUMs: 97 // CH2 Use Channel 2 delayed event in combined event 98 // CH1 Use Channel 1 delayed event in combined event 99 // CH0 Use Channel 0 delayed event in combined event 100 // NONE No event is selected for combined event. 101 #define AON_RTC_CTL_COMB_EV_MASK_W 3 102 #define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 103 #define AON_RTC_CTL_COMB_EV_MASK_S 16 104 #define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 105 #define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 106 #define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 107 #define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 108 109 // Field: [11:8] EV_DELAY 110 // 111 // Number of SCLK_LF clock cycles waited before generating delayed events. 112 // (Common setting for all RTC cannels) the delayed event is delayed 113 // ENUMs: 114 // D144 Delay by 144 clock cycles 115 // D128 Delay by 128 clock cycles 116 // D112 Delay by 112 clock cycles 117 // D96 Delay by 96 clock cycles 118 // D80 Delay by 80 clock cycles 119 // D64 Delay by 64 clock cycles 120 // D48 Delay by 48 clock cycles 121 // D32 Delay by 32 clock cycles 122 // D16 Delay by 16 clock cycles 123 // D8 Delay by 8 clock cycles 124 // D4 Delay by 4 clock cycles 125 // D2 Delay by 2 clock cycles 126 // D1 Delay by 1 clock cycles 127 // D0 No delay on delayed event 128 #define AON_RTC_CTL_EV_DELAY_W 4 129 #define AON_RTC_CTL_EV_DELAY_M 0x00000F00 130 #define AON_RTC_CTL_EV_DELAY_S 8 131 #define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 132 #define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 133 #define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 134 #define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 135 #define AON_RTC_CTL_EV_DELAY_D80 0x00000900 136 #define AON_RTC_CTL_EV_DELAY_D64 0x00000800 137 #define AON_RTC_CTL_EV_DELAY_D48 0x00000700 138 #define AON_RTC_CTL_EV_DELAY_D32 0x00000600 139 #define AON_RTC_CTL_EV_DELAY_D16 0x00000500 140 #define AON_RTC_CTL_EV_DELAY_D8 0x00000400 141 #define AON_RTC_CTL_EV_DELAY_D4 0x00000300 142 #define AON_RTC_CTL_EV_DELAY_D2 0x00000200 143 #define AON_RTC_CTL_EV_DELAY_D1 0x00000100 144 #define AON_RTC_CTL_EV_DELAY_D0 0x00000000 145 146 // Field: [7] RESET 147 // 148 // RTC Counter reset. 149 // 150 // Writing 1 to this bit will reset the RTC counter. 151 // 152 // This bit is cleared when reset takes effect 153 #define AON_RTC_CTL_RESET 0x00000080 154 #define AON_RTC_CTL_RESET_BITN 7 155 #define AON_RTC_CTL_RESET_M 0x00000080 156 #define AON_RTC_CTL_RESET_S 7 157 158 // Field: [2] RTC_4KHZ_EN 159 // 160 // RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 161 // which is used by AUX timer. 162 // 163 // 0: RTC_4KHZ signal is forced to 0 164 // 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) 165 #define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 166 #define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 167 #define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 168 #define AON_RTC_CTL_RTC_4KHZ_EN_S 2 169 170 // Field: [1] RTC_UPD_EN 171 // 172 // RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is 173 // SCLK_LF divided by 2 174 // 175 // 0: RTC_UPD signal is forced to 0 176 // 1: RTC_UPD signal is toggling @16 kHz 177 #define AON_RTC_CTL_RTC_UPD_EN 0x00000002 178 #define AON_RTC_CTL_RTC_UPD_EN_BITN 1 179 #define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 180 #define AON_RTC_CTL_RTC_UPD_EN_S 1 181 182 // Field: [0] EN 183 // 184 // Enable RTC counter 185 // 186 // 0: Halted (frozen) 187 // 1: Running 188 #define AON_RTC_CTL_EN 0x00000001 189 #define AON_RTC_CTL_EN_BITN 0 190 #define AON_RTC_CTL_EN_M 0x00000001 191 #define AON_RTC_CTL_EN_S 0 192 193 //***************************************************************************** 194 // 195 // Register: AON_RTC_O_EVFLAGS 196 // 197 //***************************************************************************** 198 // Field: [16] CH2 199 // 200 // Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or 201 // passes the CH2CMP value. 202 // 203 // An event will be scheduled to occur as soon as possible when writing to 204 // CH2CMP provided that the channel is enabled and the new value matches any 205 // time between next RTC value and 1 second in the past 206 // 207 // Writing 1 clears this flag. 208 // 209 // AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it 210 // using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. 211 #define AON_RTC_EVFLAGS_CH2 0x00010000 212 #define AON_RTC_EVFLAGS_CH2_BITN 16 213 #define AON_RTC_EVFLAGS_CH2_M 0x00010000 214 #define AON_RTC_EVFLAGS_CH2_S 16 215 216 // Field: [8] CH1 217 // 218 // Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: 219 // - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP 220 // value. 221 // - CHCTL.CH1_CAPT_EN = 1 and capture occurs. 222 // 223 // An event will be scheduled to occur as soon as possible when writing to 224 // CH1CMP provided that the channel is enabled, in compare mode and the new 225 // value matches any time between next RTC value and 1 second in the past. 226 // 227 // Writing 1 clears this flag. 228 #define AON_RTC_EVFLAGS_CH1 0x00000100 229 #define AON_RTC_EVFLAGS_CH1_BITN 8 230 #define AON_RTC_EVFLAGS_CH1_M 0x00000100 231 #define AON_RTC_EVFLAGS_CH1_S 8 232 233 // Field: [0] CH0 234 // 235 // Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or 236 // passes the CH0CMP value. 237 // 238 // An event will be scheduled to occur as soon as possible when writing to 239 // CH0CMP provided that the channels is enabled and the new value matches any 240 // time between next RTC value and 1 second in the past. 241 // 242 // Writing 1 clears this flag. 243 #define AON_RTC_EVFLAGS_CH0 0x00000001 244 #define AON_RTC_EVFLAGS_CH0_BITN 0 245 #define AON_RTC_EVFLAGS_CH0_M 0x00000001 246 #define AON_RTC_EVFLAGS_CH0_S 0 247 248 //***************************************************************************** 249 // 250 // Register: AON_RTC_O_SEC 251 // 252 //***************************************************************************** 253 // Field: [31:0] VALUE 254 // 255 // Unsigned integer representing Real Time Clock in seconds. 256 // 257 // When reading this register the content of SUBSEC.VALUE is simultaneously 258 // latched. A consistent reading of the combined Real Time Clock can be 259 // obtained by first reading this register, then reading SUBSEC register. 260 #define AON_RTC_SEC_VALUE_W 32 261 #define AON_RTC_SEC_VALUE_M 0xFFFFFFFF 262 #define AON_RTC_SEC_VALUE_S 0 263 264 //***************************************************************************** 265 // 266 // Register: AON_RTC_O_SUBSEC 267 // 268 //***************************************************************************** 269 // Field: [31:0] VALUE 270 // 271 // Unsigned integer representing Real Time Clock in fractions of a second 272 // (VALUE/2^32 seconds) at the time when SEC register was read. 273 // 274 // Examples : 275 // - 0x0000_0000 = 0.0 sec 276 // - 0x4000_0000 = 0.25 sec 277 // - 0x8000_0000 = 0.5 sec 278 // - 0xC000_0000 = 0.75 sec 279 #define AON_RTC_SUBSEC_VALUE_W 32 280 #define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF 281 #define AON_RTC_SUBSEC_VALUE_S 0 282 283 //***************************************************************************** 284 // 285 // Register: AON_RTC_O_SUBSECINC 286 // 287 //***************************************************************************** 288 // Field: [23:0] VALUEINC 289 // 290 // This value compensates for a SCLK_LF clock which has an offset from 32768 291 // Hz. 292 // 293 // The compensation value can be found as 2^38 / freq, where freq is SCLK_LF 294 // clock frequency in Hertz 295 // 296 // This value is added to SUBSEC.VALUE on every cycle, and carry of this is 297 // added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with 298 // SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a 299 // hidden 6-bit register that generates a carry into the above mentioned 300 // addition on overflow. 301 // The default value corresponds to incrementing by precisely 1/32768 of a 302 // second. 303 // 304 // NOTE: This register is read only. Modification of the register value must be 305 // done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and 306 // AUX_SYSIF:RTCSUBSECINCCTL 307 #define AON_RTC_SUBSECINC_VALUEINC_W 24 308 #define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF 309 #define AON_RTC_SUBSECINC_VALUEINC_S 0 310 311 //***************************************************************************** 312 // 313 // Register: AON_RTC_O_CHCTL 314 // 315 //***************************************************************************** 316 // Field: [18] CH2_CONT_EN 317 // 318 // Set to enable continuous operation of Channel 2 319 #define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 320 #define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 321 #define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 322 #define AON_RTC_CHCTL_CH2_CONT_EN_S 18 323 324 // Field: [16] CH2_EN 325 // 326 // RTC Channel 2 Enable 327 // 328 // 0: Disable RTC Channel 2 329 // 1: Enable RTC Channel 2 330 #define AON_RTC_CHCTL_CH2_EN 0x00010000 331 #define AON_RTC_CHCTL_CH2_EN_BITN 16 332 #define AON_RTC_CHCTL_CH2_EN_M 0x00010000 333 #define AON_RTC_CHCTL_CH2_EN_S 16 334 335 // Field: [9] CH1_CAPT_EN 336 // 337 // Set Channel 1 mode 338 // 339 // 0: Compare mode (default) 340 // 1: Capture mode 341 #define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 342 #define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 343 #define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 344 #define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 345 346 // Field: [8] CH1_EN 347 // 348 // RTC Channel 1 Enable 349 // 350 // 0: Disable RTC Channel 1 351 // 1: Enable RTC Channel 1 352 #define AON_RTC_CHCTL_CH1_EN 0x00000100 353 #define AON_RTC_CHCTL_CH1_EN_BITN 8 354 #define AON_RTC_CHCTL_CH1_EN_M 0x00000100 355 #define AON_RTC_CHCTL_CH1_EN_S 8 356 357 // Field: [0] CH0_EN 358 // 359 // RTC Channel 0 Enable 360 // 361 // 0: Disable RTC Channel 0 362 // 1: Enable RTC Channel 0 363 #define AON_RTC_CHCTL_CH0_EN 0x00000001 364 #define AON_RTC_CHCTL_CH0_EN_BITN 0 365 #define AON_RTC_CHCTL_CH0_EN_M 0x00000001 366 #define AON_RTC_CHCTL_CH0_EN_S 0 367 368 //***************************************************************************** 369 // 370 // Register: AON_RTC_O_CH0CMP 371 // 372 //***************************************************************************** 373 // Field: [31:0] VALUE 374 // 375 // RTC Channel 0 compare value. 376 // 377 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 378 // the compare value. 379 // 380 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 381 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 382 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 383 // exciting the compare value. 384 // 385 // Writing to this register can trigger an immediate*) event in case the new 386 // compare value matches a Real Time Clock value from 1 second in the past up 387 // till current Real Time Clock value. 388 // 389 // Example: 390 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 391 // 392 // *) It can take up to one SCLK_LF clock cycles before event occurs due to 393 // synchronization. 394 #define AON_RTC_CH0CMP_VALUE_W 32 395 #define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF 396 #define AON_RTC_CH0CMP_VALUE_S 0 397 398 //***************************************************************************** 399 // 400 // Register: AON_RTC_O_CH1CMP 401 // 402 //***************************************************************************** 403 // Field: [31:0] VALUE 404 // 405 // RTC Channel 1 compare value. 406 // 407 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 408 // the compare value. 409 // 410 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 411 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 412 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 413 // exciting the compare value. 414 // 415 // Writing to this register can trigger an immediate*) event in case the new 416 // compare value matches a Real Time Clock value from 1 second in the past up 417 // till current Real Time Clock value. 418 // 419 // Example: 420 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 421 // 422 // *) It can take up to one SCLK_LF clock cycles before event occurs due to 423 // synchronization. 424 #define AON_RTC_CH1CMP_VALUE_W 32 425 #define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF 426 #define AON_RTC_CH1CMP_VALUE_S 0 427 428 //***************************************************************************** 429 // 430 // Register: AON_RTC_O_CH2CMP 431 // 432 //***************************************************************************** 433 // Field: [31:0] VALUE 434 // 435 // RTC Channel 2 compare value. 436 // 437 // Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of 438 // the compare value. 439 // 440 // The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE 441 // (31:16) values of the Real Time Clock register. A Cannel 0 event is 442 // generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or 443 // exciting the compare value. 444 // 445 // Writing to this register can trigger an immediate*) event in case the new 446 // compare value matches a Real Time Clock value from 1 second in the past up 447 // till current Real Time Clock value. 448 // 449 // Example: 450 // To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 451 // 452 // *) It can take up to one SCLK_LF clock cycles before event occurs due to 453 // synchronization. 454 #define AON_RTC_CH2CMP_VALUE_W 32 455 #define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF 456 #define AON_RTC_CH2CMP_VALUE_S 0 457 458 //***************************************************************************** 459 // 460 // Register: AON_RTC_O_CH2CMPINC 461 // 462 //***************************************************************************** 463 // Field: [31:0] VALUE 464 // 465 // If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every 466 // channel 2 compare event. 467 #define AON_RTC_CH2CMPINC_VALUE_W 32 468 #define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF 469 #define AON_RTC_CH2CMPINC_VALUE_S 0 470 471 //***************************************************************************** 472 // 473 // Register: AON_RTC_O_CH1CAPT 474 // 475 //***************************************************************************** 476 // Field: [31:16] SEC 477 // 478 // Value of SEC.VALUE bits 15:0 at capture time. 479 #define AON_RTC_CH1CAPT_SEC_W 16 480 #define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 481 #define AON_RTC_CH1CAPT_SEC_S 16 482 483 // Field: [15:0] SUBSEC 484 // 485 // Value of SUBSEC.VALUE bits 31:16 at capture time. 486 #define AON_RTC_CH1CAPT_SUBSEC_W 16 487 #define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF 488 #define AON_RTC_CH1CAPT_SUBSEC_S 0 489 490 //***************************************************************************** 491 // 492 // Register: AON_RTC_O_SYNC 493 // 494 //***************************************************************************** 495 // Field: [0] WBUSY 496 // 497 // This register will always return 0,- however it will not return the value 498 // until there are no outstanding write requests between MCU and AON 499 // 500 // Note: Writing to this register prior to reading will force a wait until next 501 // SCLK_MF edge. This is recommended for syncing read registers from AON when 502 // waking up from sleep 503 // Failure to do so may result in reading AON values from prior to going to 504 // sleep 505 #define AON_RTC_SYNC_WBUSY 0x00000001 506 #define AON_RTC_SYNC_WBUSY_BITN 0 507 #define AON_RTC_SYNC_WBUSY_M 0x00000001 508 #define AON_RTC_SYNC_WBUSY_S 0 509 510 //***************************************************************************** 511 // 512 // Register: AON_RTC_O_TIME 513 // 514 //***************************************************************************** 515 // Field: [31:16] SEC_L 516 // 517 // Returns the lower halfword of SEC register. 518 #define AON_RTC_TIME_SEC_L_W 16 519 #define AON_RTC_TIME_SEC_L_M 0xFFFF0000 520 #define AON_RTC_TIME_SEC_L_S 16 521 522 // Field: [15:0] SUBSEC_H 523 // 524 // Returns the upper halfword of SUBSEC register. 525 #define AON_RTC_TIME_SUBSEC_H_W 16 526 #define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF 527 #define AON_RTC_TIME_SUBSEC_H_S 0 528 529 //***************************************************************************** 530 // 531 // Register: AON_RTC_O_SYNCLF 532 // 533 //***************************************************************************** 534 // Field: [0] PHASE 535 // 536 // This bit will always return the SCLK_LF phase. The return will delayed until 537 // a positive or negative edge of SCLK_LF is seen. 538 // 0: Falling edge of SCLK_LF 539 // 1: Rising edge of SCLK_LF 540 #define AON_RTC_SYNCLF_PHASE 0x00000001 541 #define AON_RTC_SYNCLF_PHASE_BITN 0 542 #define AON_RTC_SYNCLF_PHASE_M 0x00000001 543 #define AON_RTC_SYNCLF_PHASE_S 0 544 545 546 #endif // __AON_RTC__ 547
