1 /****************************************************************************** 2 * Filename: hw_aon_pmctl_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_PMCTL_H__ 38 #define __HW_AON_PMCTL_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_PMCTL component 44 // 45 //***************************************************************************** 46 // AUX SCE Clock Management 47 #define AON_PMCTL_O_AUXSCECLK 0x00000004 48 49 // RAM Configuration 50 #define AON_PMCTL_O_RAMCFG 0x00000008 51 52 // Power Management Control 53 #define AON_PMCTL_O_PWRCTL 0x00000010 54 55 // AON Power and Reset Status 56 #define AON_PMCTL_O_PWRSTAT 0x00000014 57 58 // Shutdown Control 59 #define AON_PMCTL_O_SHUTDOWN 0x00000018 60 61 // Recharge Controller Configuration 62 #define AON_PMCTL_O_RECHARGECFG 0x0000001C 63 64 // Recharge Controller Status 65 #define AON_PMCTL_O_RECHARGESTAT 0x00000020 66 67 // Oscillator Configuration 68 #define AON_PMCTL_O_OSCCFG 0x00000024 69 70 // Reset Management 71 #define AON_PMCTL_O_RESETCTL 0x00000028 72 73 // Sleep Control 74 #define AON_PMCTL_O_SLEEPCTL 0x0000002C 75 76 // JTAG Configuration 77 #define AON_PMCTL_O_JTAGCFG 0x00000034 78 79 // JTAG USERCODE 80 #define AON_PMCTL_O_JTAGUSERCODE 0x0000003C 81 82 //***************************************************************************** 83 // 84 // Register: AON_PMCTL_O_AUXSCECLK 85 // 86 //***************************************************************************** 87 // Field: [8] PD_SRC 88 // 89 // Selects the clock source for the AUX domain when AUX is in powerdown mode. 90 // Note: Switching the clock source is guaranteed to be glitch-free 91 // ENUMs: 92 // SCLK_LF LF clock (SCLK_LF ) 93 // NO_CLOCK No clock 94 #define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 95 #define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 96 #define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 97 #define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 98 #define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 99 #define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 100 101 // Field: [0] SRC 102 // 103 // Selects the clock source for the AUX domain when AUX is in active mode. 104 // Note: Switching the clock source is guaranteed to be glitch-free 105 // ENUMs: 106 // SCLK_MF MF Clock (SCLK_MF) 107 // SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) 108 #define AON_PMCTL_AUXSCECLK_SRC 0x00000001 109 #define AON_PMCTL_AUXSCECLK_SRC_BITN 0 110 #define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 111 #define AON_PMCTL_AUXSCECLK_SRC_S 0 112 #define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 113 #define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 114 115 //***************************************************************************** 116 // 117 // Register: AON_PMCTL_O_RAMCFG 118 // 119 //***************************************************************************** 120 // Field: [17] AUX_SRAM_PWR_OFF 121 // 122 // Internal. Only to be used through TI provided API. 123 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 124 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 125 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 126 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 127 128 // Field: [16] AUX_SRAM_RET_EN 129 // 130 // Internal. Only to be used through TI provided API. 131 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 132 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 133 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 134 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 135 136 // Field: [3:0] BUS_SRAM_RET_EN 137 // 138 // MCU SRAM is partitioned into 5 banks . This register controls which of the 139 // banks that has retention during MCU Bus domain power off 140 // ENUMs: 141 // RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 142 // ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 143 // RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 144 // ,SRAM:BANK2 and SRAM:BANK3 145 // RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and 146 // SRAM:BANK2 147 // RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1 148 // RET_NONE Retention is disabled 149 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 150 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F 151 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 152 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F 153 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 154 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 155 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001 156 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 157 158 //***************************************************************************** 159 // 160 // Register: AON_PMCTL_O_PWRCTL 161 // 162 //***************************************************************************** 163 // Field: [2] DCDC_ACTIVE 164 // 165 // Select to use DCDC regulator for VDDR in active mode 166 // 167 // 0: Use GLDO for regulation of VDDR in active mode. 168 // 1: Use DCDC for regulation of VDDR in active mode. 169 // 170 // DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active 171 // mode 172 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 173 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 174 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 175 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 176 177 // Field: [1] EXT_REG_MODE 178 // 179 // Status of source for VDDRsupply: 180 // 181 // 0: DCDC or GLDO are generating VDDR 182 // 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR 183 #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 184 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 185 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 186 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 187 188 // Field: [0] DCDC_EN 189 // 190 // Select to use DCDC regulator during recharge of VDDR 191 // 192 // 0: Use GLDO for recharge of VDDR 193 // 1: Use DCDC for recharge of VDDR 194 // 195 // Note: This bitfield should be set to the same as DCDC_ACTIVE 196 #define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 197 #define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 198 #define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 199 #define AON_PMCTL_PWRCTL_DCDC_EN_S 0 200 201 //***************************************************************************** 202 // 203 // Register: AON_PMCTL_O_PWRSTAT 204 // 205 //***************************************************************************** 206 // Field: [2] JTAG_PD_ON 207 // 208 // Indicates JTAG power state: 209 // 210 // 0: JTAG is powered off 211 // 1: JTAG is powered on 212 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 213 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 214 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 215 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 216 217 // Field: [1] AUX_BUS_RESET_DONE 218 // 219 // Indicates Reset Done from AUX Bus: 220 // 221 // 0: AUX Bus is being reset 222 // 1: AUX Bus reset is released 223 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 224 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 225 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 226 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 227 228 // Field: [0] AUX_RESET_DONE 229 // 230 // Indicates Reset Done from AUX: 231 // 232 // 0: AUX is being reset 233 // 1: AUX reset is released 234 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 235 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 236 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 237 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 238 239 //***************************************************************************** 240 // 241 // Register: AON_PMCTL_O_SHUTDOWN 242 // 243 //***************************************************************************** 244 // Field: [0] EN 245 // 246 // Shutdown control. 247 // 248 // 0: Do not write 0 to this bit. 249 // 1: Immediately start the process to enter shutdown mode 250 #define AON_PMCTL_SHUTDOWN_EN 0x00000001 251 #define AON_PMCTL_SHUTDOWN_EN_BITN 0 252 #define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 253 #define AON_PMCTL_SHUTDOWN_EN_S 0 254 255 //***************************************************************************** 256 // 257 // Register: AON_PMCTL_O_RECHARGECFG 258 // 259 //***************************************************************************** 260 // Field: [31:30] MODE 261 // 262 // Selects recharge algorithm for VDDR when the system is running on the uLDO 263 // ENUMs: 264 // COMPARATOR External recharge comparator. 265 // Note that the clock to 266 // the recharge comparator must be enabled, 267 // 268 // [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], 269 // before selecting this recharge algorithm. 270 // ADAPTIVE Adaptive timer 271 // STATIC Static timer 272 // OFF Recharge disabled 273 #define AON_PMCTL_RECHARGECFG_MODE_W 2 274 #define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 275 #define AON_PMCTL_RECHARGECFG_MODE_S 30 276 #define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 277 #define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 278 #define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 279 #define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 280 281 // Field: [23:20] C2 282 // 283 // Internal. Only to be used through TI provided API. 284 #define AON_PMCTL_RECHARGECFG_C2_W 4 285 #define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 286 #define AON_PMCTL_RECHARGECFG_C2_S 20 287 288 // Field: [19:16] C1 289 // 290 // Internal. Only to be used through TI provided API. 291 #define AON_PMCTL_RECHARGECFG_C1_W 4 292 #define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 293 #define AON_PMCTL_RECHARGECFG_C1_S 16 294 295 // Field: [15:11] MAX_PER_M 296 // 297 // Internal. Only to be used through TI provided API. 298 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 299 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 300 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 301 302 // Field: [10:8] MAX_PER_E 303 // 304 // Internal. Only to be used through TI provided API. 305 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 306 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 307 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 308 309 // Field: [7:3] PER_M 310 // 311 // Internal. Only to be used through TI provided API. 312 #define AON_PMCTL_RECHARGECFG_PER_M_W 5 313 #define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 314 #define AON_PMCTL_RECHARGECFG_PER_M_S 3 315 316 // Field: [2:0] PER_E 317 // 318 // Internal. Only to be used through TI provided API. 319 #define AON_PMCTL_RECHARGECFG_PER_E_W 3 320 #define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 321 #define AON_PMCTL_RECHARGECFG_PER_E_S 0 322 323 //***************************************************************************** 324 // 325 // Register: AON_PMCTL_O_RECHARGESTAT 326 // 327 //***************************************************************************** 328 // Field: [19:16] VDDR_SMPLS 329 // 330 // The last 4 VDDR samples. 331 // 332 // For each bit: 333 // 0: VDDR was below VDDR_OK threshold when recharge started 334 // 1: VDDR was above VDDR_OK threshold when recharge started 335 // 336 // The register is updated prior to every recharge period with a shift left, 337 // and bit 0 is updated with the last VDDR sample. 338 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 339 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 340 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 341 342 // Field: [15:0] MAX_USED_PER 343 // 344 // Shows the maximum number of 32kHz periods that have separated two recharge 345 // cycles and VDDR still was above VDDR_OK threshold when the latter recharge 346 // started. This register can be used as an indication of the leakage current 347 // during standby. 348 // 349 // This bitfield is cleared to 0 when writing this register. 350 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 351 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF 352 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 353 354 //***************************************************************************** 355 // 356 // Register: AON_PMCTL_O_OSCCFG 357 // 358 //***************************************************************************** 359 // Field: [7:3] PER_M 360 // 361 // Internal. Only to be used through TI provided API. 362 #define AON_PMCTL_OSCCFG_PER_M_W 5 363 #define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 364 #define AON_PMCTL_OSCCFG_PER_M_S 3 365 366 // Field: [2:0] PER_E 367 // 368 // Internal. Only to be used through TI provided API. 369 #define AON_PMCTL_OSCCFG_PER_E_W 3 370 #define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 371 #define AON_PMCTL_OSCCFG_PER_E_S 0 372 373 //***************************************************************************** 374 // 375 // Register: AON_PMCTL_O_RESETCTL 376 // 377 //***************************************************************************** 378 // Field: [31] SYSRESET 379 // 380 // Cold reset register. Writing 1 to this bitfield will reset the entire chip 381 // and cause boot code to run again. 382 // 383 // 0: No effect 384 // 1: Generate system reset. Appears as SYSRESET in RESET_SRC 385 #define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 386 #define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 387 #define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 388 #define AON_PMCTL_RESETCTL_SYSRESET_S 31 389 390 // Field: [25] BOOT_DET_1_CLR 391 // 392 // Internal. Only to be used through TI provided API. 393 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 394 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 395 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 396 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 397 398 // Field: [24] BOOT_DET_0_CLR 399 // 400 // Internal. Only to be used through TI provided API. 401 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 402 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 403 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 404 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 405 406 // Field: [17] BOOT_DET_1_SET 407 // 408 // Internal. Only to be used through TI provided API. 409 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 410 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 411 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 412 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 413 414 // Field: [16] BOOT_DET_0_SET 415 // 416 // Internal. Only to be used through TI provided API. 417 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 418 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 419 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 420 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 421 422 // Field: [15] WU_FROM_SD 423 // 424 // A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from 425 // SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin 426 // being forced low) 427 // 428 // Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup 429 // sources. 430 // 431 // 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 432 // 1: A wakeup has occurred from SHUTDOWN 433 // 434 // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 435 #define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 436 #define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 437 #define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 438 #define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 439 440 // Field: [14] GPIO_WU_FROM_SD 441 // 442 // A wakeup from SHUTDOWN on an IO event has occurred 443 // 444 // Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup 445 // sources. 446 // 447 // 0: The wakeup did not occur from SHUTDOWN on an IO event 448 // 1: A wakeup from SHUTDOWN occurred from an IO event 449 // 450 // The case where WU_FROM_SD is asserted but this bitfield is not asserted will 451 // only occur in a debug session. The boot code will not proceed with wakeup 452 // from SHUTDOWN procedure until this bitfield is asserted as well. 453 // 454 // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 455 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 456 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 457 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 458 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 459 460 // Field: [13] BOOT_DET_1 461 // 462 // Internal. Only to be used through TI provided API. 463 #define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 464 #define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 465 #define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 466 #define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 467 468 // Field: [12] BOOT_DET_0 469 // 470 // Internal. Only to be used through TI provided API. 471 #define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 472 #define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 473 #define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 474 #define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 475 476 // Field: [8] VDDS_LOSS_EN 477 // 478 // Controls reset generation in case VDDS is lost 479 // 480 // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 481 // 1: Brown out detect of VDDS generates system reset 482 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 483 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 484 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 485 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 486 487 // Field: [7] VDDR_LOSS_EN 488 // 489 // Controls reset generation in case VDDR is lost 490 // 491 // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 492 // 1: Brown out detect of VDDR generates system reset 493 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 494 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 495 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 496 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 497 498 // Field: [6] VDD_LOSS_EN 499 // 500 // Controls reset generation in case VDD is lost 501 // 502 // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 503 // 1: Brown out detect of VDD generates system reset 504 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 505 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 506 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 507 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 508 509 // Field: [5] CLK_LOSS_EN 510 // 511 // Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when 512 // clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 513 // 514 // 0: Clock loss is ignored 515 // 1: Clock loss generates system reset 516 // 517 // Note: Clock loss reset generation must be disabled when changing clock 518 // source for SCLK_LF. Failure to do so may result in a spurious system 519 // reset. Clock loss reset generation is controlled by 520 // [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 521 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 522 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 523 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 524 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 525 526 // Field: [4] MCU_WARM_RESET 527 // 528 // Internal. Only to be used through TI provided API. 529 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 530 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 531 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 532 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 533 534 // Field: [3:1] RESET_SRC 535 // 536 // Shows the root cause of the last system reset. More than the reported reset 537 // source can have been active during the last system reset but only the root 538 // cause is reported. 539 // 540 // The capture feature is not rearmed until all off the possible reset sources 541 // have been released and the result has been copied to AON_PMCTL. During the 542 // copy and rearm process it is one 2MHz period in which and eventual new 543 // system reset will be reported as Power on reset regardless of the root 544 // cause. 545 // ENUMs: 546 // WARMRESET Software reset via PRCM warm reset request 547 // SYSRESET Software reset via SYSRESET or hardware power 548 // management timeout detection. 549 // 550 // Note: The hardware power 551 // management timeout circuit is always enabled. 552 // CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect 553 // VDDR_LOSS Brown out detect on VDDR 554 // VDDS_LOSS Brown out detect on VDDS 555 // PIN_RESET Reset pin 556 // PWR_ON Power on reset 557 #define AON_PMCTL_RESETCTL_RESET_SRC_W 3 558 #define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E 559 #define AON_PMCTL_RESETCTL_RESET_SRC_S 1 560 #define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E 561 #define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C 562 #define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A 563 #define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 564 #define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 565 #define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 566 #define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 567 568 //***************************************************************************** 569 // 570 // Register: AON_PMCTL_O_SLEEPCTL 571 // 572 //***************************************************************************** 573 // Field: [0] IO_PAD_SLEEP_DIS 574 // 575 // Controls the I/O pad sleep mode. The boot code will set this bitfield 576 // automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is 577 // set). 578 // 579 // 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations 580 // are latched. Inputs are transparent if pad is configured as input before 581 // IO_PAD_SLEEP_DIS is set to 1 582 // 1: I/O pad sleep mode is disabled 583 // 584 // Application software must reconfigure the state for all IO's before setting 585 // this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. 586 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 587 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 588 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 589 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 590 591 //***************************************************************************** 592 // 593 // Register: AON_PMCTL_O_JTAGCFG 594 // 595 //***************************************************************************** 596 // Field: [8] JTAG_PD_FORCE_ON 597 // 598 // Controls JTAG Power domain power state: 599 // 600 // 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be 601 // powered off unless a debugger is attached) 602 // 1: JTAG Power Domain is forced on, independent of debug subsystem. 603 // 604 // Note: The reset value causes JTAG Power domain to be powered on by default. 605 // Software must clear this bit to turn off the JTAG Power domain 606 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 607 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 608 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 609 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 610 611 //***************************************************************************** 612 // 613 // Register: AON_PMCTL_O_JTAGUSERCODE 614 // 615 //***************************************************************************** 616 // Field: [31:0] USER_CODE 617 // 618 // 32-bit JTAG USERCODE register feeding main JTAG TAP 619 // Note: This field can be locked by LOCKCFG.LOCK 620 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 621 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF 622 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 623 624 625 #endif // __AON_PMCTL__ 626
