1 /****************************************************************************** 2 * Filename: hw_memmap_h 3 * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) 4 * Revision: 51990 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_MEMMAP_H__ 38 #define __HW_MEMMAP_H__ 39 40 //***************************************************************************** 41 // 42 // The following are defines for the base address of the memories and 43 // peripherals on the CPU_MMAP interface 44 // 45 //***************************************************************************** 46 #define FLASHMEM_BASE 0x00000000 // FLASHMEM 47 #define BROM_BASE 0x10000000 // BROM 48 #define GPRAM_BASE 0x11000000 // GPRAM 49 #define SRAM_BASE 0x20000000 // SRAM 50 #define RFC_RAM_BASE 0x21000000 // RFC_RAM 51 #define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM 52 #define SSI0_BASE 0x40000000 // SSI 53 #define UART0_BASE 0x40001000 // UART 54 #define I2C0_BASE 0x40002000 // I2C 55 #define SSI1_BASE 0x40008000 // SSI 56 #define UART1_BASE 0x4000B000 // UART 57 #define GPT0_BASE 0x40010000 // GPT 58 #define GPT1_BASE 0x40011000 // GPT 59 #define GPT2_BASE 0x40012000 // GPT 60 #define GPT3_BASE 0x40013000 // GPT 61 #define UDMA0_BASE 0x40020000 // UDMA 62 #define I2S0_BASE 0x40021000 // I2S 63 #define GPIO_BASE 0x40022000 // GPIO 64 #define CRYPTO_BASE 0x40024000 // CRYPTO 65 #define PKA_BASE 0x40025000 // PKA 66 #define PKA_RAM_BASE 0x40026000 // PKA_RAM 67 #define PKA_INT_BASE 0x40027000 // PKA_INT 68 #define TRNG_BASE 0x40028000 // TRNG 69 #define FLASH_BASE 0x40030000 // FLASH 70 #define VIMS_BASE 0x40034000 // VIMS 71 #define SRAM_MMR_BASE 0x40035000 // SRAM_MMR 72 #define RFC_PWR_BASE 0x40040000 // RFC_PWR 73 #define RFC_DBELL_BASE 0x40041000 // RFC_DBELL 74 #define RFC_RAT_BASE 0x40043000 // RFC_RAT 75 #define RFC_FSCA_BASE 0x40044000 // RFC_FSCA 76 #define WDT_BASE 0x40080000 // WDT 77 #define IOC_BASE 0x40081000 // IOC 78 #define PRCM_BASE 0x40082000 // PRCM 79 #define EVENT_BASE 0x40083000 // EVENT 80 #define SMPH_BASE 0x40084000 // SMPH 81 #define ADI2_BASE 0x40086000 // ADI 82 #define ADI3_BASE 0x40086200 // ADI 83 #define AON_PMCTL_BASE 0x40090000 // AON_PMCTL 84 #define AON_RTC_BASE 0x40092000 // AON_RTC 85 #define AON_EVENT_BASE 0x40093000 // AON_EVENT 86 #define AON_IOC_BASE 0x40094000 // AON_IOC 87 #define AON_BATMON_BASE 0x40095000 // AON_BATMON 88 #define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM 89 #define AUX_MAC_BASE 0x400C2000 // AUX_MAC 90 #define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 91 #define AUX_TDC_BASE 0x400C4000 // AUX_TDC 92 #define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL 93 #define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF 94 #define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 95 #define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH 96 #define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF 97 #define AUX_DDI0_OSC_BASE 0x400CA000 // DDI 98 #define AUX_ADI4_BASE 0x400CB000 // ADI 99 #define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO 100 #define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO 101 #define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO 102 #define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO 103 #define AUX_RAM_BASE 0x400E0000 // AUX_RAM 104 #define AUX_SCE_BASE 0x400E1000 // AUX_SCE 105 #define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP 106 #define FCFG1_BASE 0x50001000 // FCFG1 107 #define FCFG2_BASE 0x50002000 // FCFG2 108 #ifndef CCFG_BASE 109 #define CCFG_BASE 0x50003000 // CCFG 110 #endif 111 #define CCFG_BASE_DEFAULT 0x50003000 // CCFG 112 #define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base 113 #define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base 114 #define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base 115 #define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base 116 #define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base 117 #define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base 118 #define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base 119 #define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base 120 #define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base 121 #define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base 122 #define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base 123 #define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base 124 #define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base 125 #define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base 126 #define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base 127 #define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base 128 #define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base 129 #define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base 130 #define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base 131 #define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base 132 #define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base 133 #define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base 134 #define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base 135 #define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base 136 #define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base 137 #define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base 138 #define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base 139 #define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base 140 #define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base 141 #define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base 142 #define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base 143 #define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base 144 #define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base 145 #define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base 146 #define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base 147 #define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base 148 #define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base 149 #define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base 150 #define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base 151 #define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base 152 #define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base 153 #define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base 154 #define AUX_TIMER01_NONBUF_BASE \ 155 0x600C7000 // AUX_TIMER01 CPU nonbuf base 156 #define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base 157 #define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base 158 #define AUX_DDI0_OSC_NONBUF_BASE \ 159 0x600CA000 // DDI CPU nonbuf base 160 #define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base 161 #define AUX_AIODIO0_NONBUF_BASE \ 162 0x600CC000 // AUX_AIODIO CPU nonbuf base 163 #define AUX_AIODIO1_NONBUF_BASE \ 164 0x600CD000 // AUX_AIODIO CPU nonbuf base 165 #define AUX_AIODIO2_NONBUF_BASE \ 166 0x600CE000 // AUX_AIODIO CPU nonbuf base 167 #define AUX_AIODIO3_NONBUF_BASE \ 168 0x600CF000 // AUX_AIODIO CPU nonbuf base 169 #define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base 170 #define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base 171 #define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base 172 #define CPU_ITM_BASE 0xE0000000 // CPU_ITM 173 #define CPU_DWT_BASE 0xE0001000 // CPU_DWT 174 #define CPU_FPB_BASE 0xE0002000 // CPU_FPB 175 #define CPU_SCS_BASE 0xE000E000 // CPU_SCS 176 #define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU 177 #define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP 178 #define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE 179 180 #endif // __HW_MEMMAP__ 181
