1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_ADC_H__ 35 #define __HW_ADC_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the ADC register offsets. 40 // 41 //***************************************************************************** 42 #define ADC_O_ADC_CTRL 0x00000000 // ADC control register. 43 #define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting 44 #define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting 45 #define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting 46 #define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting 47 #define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting 48 #define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting 49 #define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting 50 #define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting 51 #define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable 52 // register 53 #define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable 54 // register 55 #define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable 56 // register 57 #define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable 58 // register 59 #define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable 60 // register 61 #define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable 62 // register 63 #define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable 64 // register 65 #define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable 66 // register 67 #define ADC_O_adc_ch0_irq_status \ 68 0x00000044 // Channel 0 interrupt status 69 // register 70 71 #define ADC_O_adc_ch1_irq_status \ 72 0x00000048 // Channel 1 interrupt status 73 // register 74 75 #define ADC_O_adc_ch2_irq_status \ 76 0x0000004C 77 78 #define ADC_O_adc_ch3_irq_status \ 79 0x00000050 // Channel 3 interrupt status 80 // register 81 82 #define ADC_O_adc_ch4_irq_status \ 83 0x00000054 // Channel 4 interrupt status 84 // register 85 86 #define ADC_O_adc_ch5_irq_status \ 87 0x00000058 88 89 #define ADC_O_adc_ch6_irq_status \ 90 0x0000005C // Channel 6 interrupt status 91 // register 92 93 #define ADC_O_adc_ch7_irq_status \ 94 0x00000060 // Channel 7 interrupt status 95 // register 96 97 #define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register 98 #define ADC_O_adc_timer_configuration \ 99 0x00000068 // ADC timer configuration register 100 101 #define ADC_O_adc_timer_current_count \ 102 0x00000070 // ADC timer current count register 103 104 #define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register 105 #define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register 106 #define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register 107 #define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register 108 #define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register 109 #define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register 110 #define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register 111 #define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register 112 #define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register 113 #define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status 114 // register 115 #define ADC_O_adc_ch2_fifo_lvl 0x0000009C 116 #define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status 117 // register 118 #define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status 119 // register 120 #define ADC_O_adc_ch5_fifo_lvl 0x000000A8 121 #define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status 122 // register 123 #define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status 124 // register 125 126 #define ADC_O_ADC_CH_ENABLE 0x000000B8 127 128 //****************************************************************************** 129 // 130 // The following are defines for the bit fields in the ADC_O_ADC_CTRL register. 131 // 132 //****************************************************************************** 133 #define ADC_ADC_CTRL_adc_cap_scale \ 134 0x00000020 // ADC CAP SCALE. 135 136 #define ADC_ADC_CTRL_adc_buf_bypass \ 137 0x00000010 // ADC ANA CIO buffer bypass. 138 // Signal is modelled in ANA TOP. 139 // When '1': ADC buffer is bypassed. 140 141 #define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: 142 // ADC buffer is enabled. 143 #define ADC_ADC_CTRL_adc_core_en \ 144 0x00000004 // ANA ADC core en. This signal act 145 // as glbal enable to ADC CIO. When 146 // 1: ADC core is enabled. 147 148 #define ADC_ADC_CTRL_adc_soft_reset \ 149 0x00000002 // ADC soft reset. When '1' : reset 150 // ADC internal logic. 151 152 #define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC 153 // module is enabled 154 //****************************************************************************** 155 // 156 // The following are defines for the bit fields in the 157 // ADC_O_adc_ch0_gain register. 158 // 159 //****************************************************************************** 160 #define ADC_adc_ch0_gain_adc_channel0_gain_M \ 161 0x00000003 // gain setting for ADC channel 0. 162 // when "00": 1x when "01: 2x when 163 // "10":3x when "11" 4x 164 165 #define ADC_adc_ch0_gain_adc_channel0_gain_S 0 166 //****************************************************************************** 167 // 168 // The following are defines for the bit fields in the 169 // ADC_O_adc_ch1_gain register. 170 // 171 //****************************************************************************** 172 #define ADC_adc_ch1_gain_adc_channel1_gain_M \ 173 0x00000003 // gain setting for ADC channel 1. 174 // when "00": 1x when "01: 2x when 175 // "10":3x when "11" 4x 176 177 #define ADC_adc_ch1_gain_adc_channel1_gain_S 0 178 //****************************************************************************** 179 // 180 // The following are defines for the bit fields in the 181 // ADC_O_adc_ch2_gain register. 182 // 183 //****************************************************************************** 184 #define ADC_adc_ch2_gain_adc_channel2_gain_M \ 185 0x00000003 // gain setting for ADC channel 2. 186 // when "00": 1x when "01: 2x when 187 // "10":3x when "11" 4x 188 189 #define ADC_adc_ch2_gain_adc_channel2_gain_S 0 190 //****************************************************************************** 191 // 192 // The following are defines for the bit fields in the 193 // ADC_O_adc_ch3_gain register. 194 // 195 //****************************************************************************** 196 #define ADC_adc_ch3_gain_adc_channel3_gain_M \ 197 0x00000003 // gain setting for ADC channel 3. 198 // when "00": 1x when "01: 2x when 199 // "10":3x when "11" 4x 200 201 #define ADC_adc_ch3_gain_adc_channel3_gain_S 0 202 //****************************************************************************** 203 // 204 // The following are defines for the bit fields in the 205 // ADC_O_adc_ch4_gain register. 206 // 207 //****************************************************************************** 208 #define ADC_adc_ch4_gain_adc_channel4_gain_M \ 209 0x00000003 // gain setting for ADC channel 4 210 // when "00": 1x when "01: 2x when 211 // "10":3x when "11" 4x 212 213 #define ADC_adc_ch4_gain_adc_channel4_gain_S 0 214 //****************************************************************************** 215 // 216 // The following are defines for the bit fields in the 217 // ADC_O_adc_ch5_gain register. 218 // 219 //****************************************************************************** 220 #define ADC_adc_ch5_gain_adc_channel5_gain_M \ 221 0x00000003 // gain setting for ADC channel 5. 222 // when "00": 1x when "01: 2x when 223 // "10":3x when "11" 4x 224 225 #define ADC_adc_ch5_gain_adc_channel5_gain_S 0 226 //****************************************************************************** 227 // 228 // The following are defines for the bit fields in the 229 // ADC_O_adc_ch6_gain register. 230 // 231 //****************************************************************************** 232 #define ADC_adc_ch6_gain_adc_channel6_gain_M \ 233 0x00000003 // gain setting for ADC channel 6 234 // when "00": 1x when "01: 2x when 235 // "10":3x when "11" 4x 236 237 #define ADC_adc_ch6_gain_adc_channel6_gain_S 0 238 //****************************************************************************** 239 // 240 // The following are defines for the bit fields in the 241 // ADC_O_adc_ch7_gain register. 242 // 243 //****************************************************************************** 244 #define ADC_adc_ch7_gain_adc_channel7_gain_M \ 245 0x00000003 // gain setting for ADC channel 7. 246 // when "00": 1x when "01: 2x when 247 // "10":3x when "11" 4x 248 249 #define ADC_adc_ch7_gain_adc_channel7_gain_S 0 250 //****************************************************************************** 251 // 252 // The following are defines for the bit fields in the 253 // ADC_O_adc_ch0_irq_en register. 254 // 255 //****************************************************************************** 256 #define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ 257 0x0000000F // interrupt enable register for 258 // per ADC channel bit 3: when '1' 259 // -> enable FIFO overflow interrupt 260 // bit 2: when '1' -> enable FIFO 261 // underflow interrupt bit 1: when 262 // "1' -> enable FIFO empty 263 // interrupt bit 0: when "1" -> 264 // enable FIFO full interrupt 265 266 #define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 267 //****************************************************************************** 268 // 269 // The following are defines for the bit fields in the 270 // ADC_O_adc_ch1_irq_en register. 271 // 272 //****************************************************************************** 273 #define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ 274 0x0000000F // interrupt enable register for 275 // per ADC channel bit 3: when '1' 276 // -> enable FIFO overflow interrupt 277 // bit 2: when '1' -> enable FIFO 278 // underflow interrupt bit 1: when 279 // "1' -> enable FIFO empty 280 // interrupt bit 0: when "1" -> 281 // enable FIFO full interrupt 282 283 #define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 284 //****************************************************************************** 285 // 286 // The following are defines for the bit fields in the 287 // ADC_O_adc_ch2_irq_en register. 288 // 289 //****************************************************************************** 290 #define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ 291 0x0000000F // interrupt enable register for 292 // per ADC channel bit 3: when '1' 293 // -> enable FIFO overflow interrupt 294 // bit 2: when '1' -> enable FIFO 295 // underflow interrupt bit 1: when 296 // "1' -> enable FIFO empty 297 // interrupt bit 0: when "1" -> 298 // enable FIFO full interrupt 299 300 #define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 301 //****************************************************************************** 302 // 303 // The following are defines for the bit fields in the 304 // ADC_O_adc_ch3_irq_en register. 305 // 306 //****************************************************************************** 307 #define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ 308 0x0000000F // interrupt enable register for 309 // per ADC channel bit 3: when '1' 310 // -> enable FIFO overflow interrupt 311 // bit 2: when '1' -> enable FIFO 312 // underflow interrupt bit 1: when 313 // "1' -> enable FIFO empty 314 // interrupt bit 0: when "1" -> 315 // enable FIFO full interrupt 316 317 #define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 318 //****************************************************************************** 319 // 320 // The following are defines for the bit fields in the 321 // ADC_O_adc_ch4_irq_en register. 322 // 323 //****************************************************************************** 324 #define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ 325 0x0000000F // interrupt enable register for 326 // per ADC channel bit 3: when '1' 327 // -> enable FIFO overflow interrupt 328 // bit 2: when '1' -> enable FIFO 329 // underflow interrupt bit 1: when 330 // "1' -> enable FIFO empty 331 // interrupt bit 0: when "1" -> 332 // enable FIFO full interrupt 333 334 #define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 335 //****************************************************************************** 336 // 337 // The following are defines for the bit fields in the 338 // ADC_O_adc_ch5_irq_en register. 339 // 340 //****************************************************************************** 341 #define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ 342 0x0000000F // interrupt enable register for 343 // per ADC channel bit 3: when '1' 344 // -> enable FIFO overflow interrupt 345 // bit 2: when '1' -> enable FIFO 346 // underflow interrupt bit 1: when 347 // "1' -> enable FIFO empty 348 // interrupt bit 0: when "1" -> 349 // enable FIFO full interrupt 350 351 #define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 352 //****************************************************************************** 353 // 354 // The following are defines for the bit fields in the 355 // ADC_O_adc_ch6_irq_en register. 356 // 357 //****************************************************************************** 358 #define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ 359 0x0000000F // interrupt enable register for 360 // per ADC channel bit 3: when '1' 361 // -> enable FIFO overflow interrupt 362 // bit 2: when '1' -> enable FIFO 363 // underflow interrupt bit 1: when 364 // "1' -> enable FIFO empty 365 // interrupt bit 0: when "1" -> 366 // enable FIFO full interrupt 367 368 #define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 369 //****************************************************************************** 370 // 371 // The following are defines for the bit fields in the 372 // ADC_O_adc_ch7_irq_en register. 373 // 374 //****************************************************************************** 375 #define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ 376 0x0000000F // interrupt enable register for 377 // per ADC channel bit 3: when '1' 378 // -> enable FIFO overflow interrupt 379 // bit 2: when '1' -> enable FIFO 380 // underflow interrupt bit 1: when 381 // "1' -> enable FIFO empty 382 // interrupt bit 0: when "1" -> 383 // enable FIFO full interrupt 384 385 #define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 386 //****************************************************************************** 387 // 388 // The following are defines for the bit fields in the 389 // ADC_O_adc_ch0_irq_status register. 390 // 391 //****************************************************************************** 392 #define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ 393 0x0000000F // interrupt status register for 394 // per ADC channel. Interrupt status 395 // can be cleared on write. bit 3: 396 // when value '1' is written -> 397 // would clear FIFO overflow 398 // interrupt status in the next 399 // cycle. if same interrupt is set 400 // in the same cycle then interurpt 401 // would be set and clear command 402 // will be ignored. bit 2: when 403 // value '1' is written -> would 404 // clear FIFO underflow interrupt 405 // status in the next cycle. bit 1: 406 // when value '1' is written -> 407 // would clear FIFO empty interrupt 408 // status in the next cycle. bit 0: 409 // when value '1' is written -> 410 // would clear FIFO full interrupt 411 // status in the next cycle. 412 413 #define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 414 //****************************************************************************** 415 // 416 // The following are defines for the bit fields in the 417 // ADC_O_adc_ch1_irq_status register. 418 // 419 //****************************************************************************** 420 #define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ 421 0x0000000F // interrupt status register for 422 // per ADC channel. Interrupt status 423 // can be cleared on write. bit 3: 424 // when value '1' is written -> 425 // would clear FIFO overflow 426 // interrupt status in the next 427 // cycle. if same interrupt is set 428 // in the same cycle then interurpt 429 // would be set and clear command 430 // will be ignored. bit 2: when 431 // value '1' is written -> would 432 // clear FIFO underflow interrupt 433 // status in the next cycle. bit 1: 434 // when value '1' is written -> 435 // would clear FIFO empty interrupt 436 // status in the next cycle. bit 0: 437 // when value '1' is written -> 438 // would clear FIFO full interrupt 439 // status in the next cycle. 440 441 #define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 442 //****************************************************************************** 443 // 444 // The following are defines for the bit fields in the 445 // ADC_O_adc_ch2_irq_status register. 446 // 447 //****************************************************************************** 448 #define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ 449 0x0000000F // interrupt status register for 450 // per ADC channel. Interrupt status 451 // can be cleared on write. bit 3: 452 // when value '1' is written -> 453 // would clear FIFO overflow 454 // interrupt status in the next 455 // cycle. if same interrupt is set 456 // in the same cycle then interurpt 457 // would be set and clear command 458 // will be ignored. bit 2: when 459 // value '1' is written -> would 460 // clear FIFO underflow interrupt 461 // status in the next cycle. bit 1: 462 // when value '1' is written -> 463 // would clear FIFO empty interrupt 464 // status in the next cycle. bit 0: 465 // when value '1' is written -> 466 // would clear FIFO full interrupt 467 // status in the next cycle. 468 469 #define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 470 //****************************************************************************** 471 // 472 // The following are defines for the bit fields in the 473 // ADC_O_adc_ch3_irq_status register. 474 // 475 //****************************************************************************** 476 #define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ 477 0x0000000F // interrupt status register for 478 // per ADC channel. Interrupt status 479 // can be cleared on write. bit 3: 480 // when value '1' is written -> 481 // would clear FIFO overflow 482 // interrupt status in the next 483 // cycle. if same interrupt is set 484 // in the same cycle then interurpt 485 // would be set and clear command 486 // will be ignored. bit 2: when 487 // value '1' is written -> would 488 // clear FIFO underflow interrupt 489 // status in the next cycle. bit 1: 490 // when value '1' is written -> 491 // would clear FIFO empty interrupt 492 // status in the next cycle. bit 0: 493 // when value '1' is written -> 494 // would clear FIFO full interrupt 495 // status in the next cycle. 496 497 #define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 498 //****************************************************************************** 499 // 500 // The following are defines for the bit fields in the 501 // ADC_O_adc_ch4_irq_status register. 502 // 503 //****************************************************************************** 504 #define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ 505 0x0000000F // interrupt status register for 506 // per ADC channel. Interrupt status 507 // can be cleared on write. bit 3: 508 // when value '1' is written -> 509 // would clear FIFO overflow 510 // interrupt status in the next 511 // cycle. if same interrupt is set 512 // in the same cycle then interurpt 513 // would be set and clear command 514 // will be ignored. bit 2: when 515 // value '1' is written -> would 516 // clear FIFO underflow interrupt 517 // status in the next cycle. bit 1: 518 // when value '1' is written -> 519 // would clear FIFO empty interrupt 520 // status in the next cycle. bit 0: 521 // when value '1' is written -> 522 // would clear FIFO full interrupt 523 // status in the next cycle. 524 525 #define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 526 //****************************************************************************** 527 // 528 // The following are defines for the bit fields in the 529 // ADC_O_adc_ch5_irq_status register. 530 // 531 //****************************************************************************** 532 #define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ 533 0x0000000F // interrupt status register for 534 // per ADC channel. Interrupt status 535 // can be cleared on write. bit 3: 536 // when value '1' is written -> 537 // would clear FIFO overflow 538 // interrupt status in the next 539 // cycle. if same interrupt is set 540 // in the same cycle then interurpt 541 // would be set and clear command 542 // will be ignored. bit 2: when 543 // value '1' is written -> would 544 // clear FIFO underflow interrupt 545 // status in the next cycle. bit 1: 546 // when value '1' is written -> 547 // would clear FIFO empty interrupt 548 // status in the next cycle. bit 0: 549 // when value '1' is written -> 550 // would clear FIFO full interrupt 551 // status in the next cycle. 552 553 #define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 554 //****************************************************************************** 555 // 556 // The following are defines for the bit fields in the 557 // ADC_O_adc_ch6_irq_status register. 558 // 559 //****************************************************************************** 560 #define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ 561 0x0000000F // interrupt status register for 562 // per ADC channel. Interrupt status 563 // can be cleared on write. bit 3: 564 // when value '1' is written -> 565 // would clear FIFO overflow 566 // interrupt status in the next 567 // cycle. if same interrupt is set 568 // in the same cycle then interurpt 569 // would be set and clear command 570 // will be ignored. bit 2: when 571 // value '1' is written -> would 572 // clear FIFO underflow interrupt 573 // status in the next cycle. bit 1: 574 // when value '1' is written -> 575 // would clear FIFO empty interrupt 576 // status in the next cycle. bit 0: 577 // when value '1' is written -> 578 // would clear FIFO full interrupt 579 // status in the next cycle. 580 581 #define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 582 //****************************************************************************** 583 // 584 // The following are defines for the bit fields in the 585 // ADC_O_adc_ch7_irq_status register. 586 // 587 //****************************************************************************** 588 #define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ 589 0x0000000F // interrupt status register for 590 // per ADC channel. Interrupt status 591 // can be cleared on write. bit 3: 592 // when value '1' is written -> 593 // would clear FIFO overflow 594 // interrupt status in the next 595 // cycle. if same interrupt is set 596 // in the same cycle then interurpt 597 // would be set and clear command 598 // will be ignored. bit 2: when 599 // value '1' is written -> would 600 // clear FIFO underflow interrupt 601 // status in the next cycle. bit 1: 602 // when value '1' is written -> 603 // would clear FIFO empty interrupt 604 // status in the next cycle. bit 0: 605 // when value '1' is written -> 606 // would clear FIFO full interrupt 607 // status in the next cycle. 608 609 #define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 610 //****************************************************************************** 611 // 612 // The following are defines for the bit fields in the 613 // ADC_O_adc_dma_mode_en register. 614 // 615 //****************************************************************************** 616 #define ADC_adc_dma_mode_en_DMA_MODEenable_M \ 617 0x000000FF // this register enable DMA mode. 618 // when '1' respective ADC channel 619 // is enabled for DMA. When '0' only 620 // interrupt mode is enabled. Bit 0: 621 // channel 0 DMA mode enable. Bit 1: 622 // channel 1 DMA mode enable. Bit 2: 623 // channel 2 DMA mode enable. Bit 3: 624 // channel 3 DMA mode enable. bit 4: 625 // channel 4 DMA mode enable. bit 5: 626 // channel 5 DMA mode enable. bit 6: 627 // channel 6 DMA mode enable. bit 7: 628 // channel 7 DMA mode enable. 629 630 #define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 631 //****************************************************************************** 632 // 633 // The following are defines for the bit fields in the 634 // ADC_O_adc_timer_configuration register. 635 // 636 //****************************************************************************** 637 #define ADC_adc_timer_configuration_timeren \ 638 0x02000000 // when '1' timer is enabled. 639 640 #define ADC_adc_timer_configuration_timerreset \ 641 0x01000000 // when '1' reset timer. 642 643 #define ADC_adc_timer_configuration_timercount_M \ 644 0x00FFFFFF // Timer count configuration. 17 645 // bit counter is supported. Other 646 // MSB's are redundent. 647 648 #define ADC_adc_timer_configuration_timercount_S 0 649 //****************************************************************************** 650 // 651 // The following are defines for the bit fields in the 652 // ADC_O_adc_timer_current_count register. 653 // 654 //****************************************************************************** 655 #define ADC_adc_timer_current_count_timercurrentcount_M \ 656 0x0001FFFF // Timer count configuration 657 658 #define ADC_adc_timer_current_count_timercurrentcount_S 0 659 //****************************************************************************** 660 // 661 // The following are defines for the bit fields in the 662 // ADC_O_channel0FIFODATA register. 663 // 664 //****************************************************************************** 665 #define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ 666 0xFFFFFFFF // read to this register would 667 // return ADC data along with time 668 // stamp information in following 669 // format: bits [13:0] : ADC sample 670 // bits [31:14]: : time stamp per 671 // ADC sample 672 673 #define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 674 //****************************************************************************** 675 // 676 // The following are defines for the bit fields in the 677 // ADC_O_channel1FIFODATA register. 678 // 679 //****************************************************************************** 680 #define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ 681 0xFFFFFFFF // read to this register would 682 // return ADC data along with time 683 // stamp information in following 684 // format: bits [13:0] : ADC sample 685 // bits [31:14]: : time stamp per 686 // ADC sample 687 688 #define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 689 //****************************************************************************** 690 // 691 // The following are defines for the bit fields in the 692 // ADC_O_channel2FIFODATA register. 693 // 694 //****************************************************************************** 695 #define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ 696 0xFFFFFFFF // read to this register would 697 // return ADC data along with time 698 // stamp information in following 699 // format: bits [13:0] : ADC sample 700 // bits [31:14]: : time stamp per 701 // ADC sample 702 703 #define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 704 //****************************************************************************** 705 // 706 // The following are defines for the bit fields in the 707 // ADC_O_channel3FIFODATA register. 708 // 709 //****************************************************************************** 710 #define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ 711 0xFFFFFFFF // read to this register would 712 // return ADC data along with time 713 // stamp information in following 714 // format: bits [13:0] : ADC sample 715 // bits [31:14]: : time stamp per 716 // ADC sample 717 718 #define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 719 //****************************************************************************** 720 // 721 // The following are defines for the bit fields in the 722 // ADC_O_channel4FIFODATA register. 723 // 724 //****************************************************************************** 725 #define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ 726 0xFFFFFFFF // read to this register would 727 // return ADC data along with time 728 // stamp information in following 729 // format: bits [13:0] : ADC sample 730 // bits [31:14]: : time stamp per 731 // ADC sample 732 733 #define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 734 //****************************************************************************** 735 // 736 // The following are defines for the bit fields in the 737 // ADC_O_channel5FIFODATA register. 738 // 739 //****************************************************************************** 740 #define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ 741 0xFFFFFFFF // read to this register would 742 // return ADC data along with time 743 // stamp information in following 744 // format: bits [13:0] : ADC sample 745 // bits [31:14]: : time stamp per 746 // ADC sample 747 748 #define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 749 //****************************************************************************** 750 // 751 // The following are defines for the bit fields in the 752 // ADC_O_channel6FIFODATA register. 753 // 754 //****************************************************************************** 755 #define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ 756 0xFFFFFFFF // read to this register would 757 // return ADC data along with time 758 // stamp information in following 759 // format: bits [13:0] : ADC sample 760 // bits [31:14]: : time stamp per 761 // ADC sample 762 763 #define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 764 //****************************************************************************** 765 // 766 // The following are defines for the bit fields in the 767 // ADC_O_channel7FIFODATA register. 768 // 769 //****************************************************************************** 770 #define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ 771 0xFFFFFFFF // read to this register would 772 // return ADC data along with time 773 // stamp information in following 774 // format: bits [13:0] : ADC sample 775 // bits [31:14]: : time stamp per 776 // ADC sample 777 778 #define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 779 //****************************************************************************** 780 // 781 // The following are defines for the bit fields in the 782 // ADC_O_adc_ch0_fifo_lvl register. 783 // 784 //****************************************************************************** 785 #define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ 786 0x00000007 // This register shows current FIFO 787 // level. FIFO is 4 word wide. 788 // Possible supported levels are : 789 // 0x0 to 0x3 790 791 #define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 792 //****************************************************************************** 793 // 794 // The following are defines for the bit fields in the 795 // ADC_O_adc_ch1_fifo_lvl register. 796 // 797 //****************************************************************************** 798 #define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ 799 0x00000007 // This register shows current FIFO 800 // level. FIFO is 4 word wide. 801 // Possible supported levels are : 802 // 0x0 to 0x3 803 804 #define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 805 //****************************************************************************** 806 // 807 // The following are defines for the bit fields in the 808 // ADC_O_adc_ch2_fifo_lvl register. 809 // 810 //****************************************************************************** 811 #define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ 812 0x00000007 // This register shows current FIFO 813 // level. FIFO is 4 word wide. 814 // Possible supported levels are : 815 // 0x0 to 0x3 816 817 #define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 818 //****************************************************************************** 819 // 820 // The following are defines for the bit fields in the 821 // ADC_O_adc_ch3_fifo_lvl register. 822 // 823 //****************************************************************************** 824 #define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ 825 0x00000007 // This register shows current FIFO 826 // level. FIFO is 4 word wide. 827 // Possible supported levels are : 828 // 0x0 to 0x3 829 830 #define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 831 //****************************************************************************** 832 // 833 // The following are defines for the bit fields in the 834 // ADC_O_adc_ch4_fifo_lvl register. 835 // 836 //****************************************************************************** 837 #define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ 838 0x00000007 // This register shows current FIFO 839 // level. FIFO is 4 word wide. 840 // Possible supported levels are : 841 // 0x0 to 0x3 842 843 #define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 844 //****************************************************************************** 845 // 846 // The following are defines for the bit fields in the 847 // ADC_O_adc_ch5_fifo_lvl register. 848 // 849 //****************************************************************************** 850 #define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ 851 0x00000007 // This register shows current FIFO 852 // level. FIFO is 4 word wide. 853 // Possible supported levels are : 854 // 0x0 to 0x3 855 856 #define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 857 //****************************************************************************** 858 // 859 // The following are defines for the bit fields in the 860 // ADC_O_adc_ch6_fifo_lvl register. 861 // 862 //****************************************************************************** 863 #define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ 864 0x00000007 // This register shows current FIFO 865 // level. FIFO is 4 word wide. 866 // Possible supported levels are : 867 // 0x0 to 0x3 868 869 #define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 870 //****************************************************************************** 871 // 872 // The following are defines for the bit fields in the 873 // ADC_O_adc_ch7_fifo_lvl register. 874 // 875 //****************************************************************************** 876 #define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ 877 0x00000007 // This register shows current FIFO 878 // level. FIFO is 4 word wide. 879 // Possible supported levels are : 880 // 0x0 to 0x3 881 882 #define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 883 884 885 886 #endif // __HW_ADC_H__ 887
