1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 #ifndef DRIVERS_B91_DRIVER_EXT_EXT_RF_H_
20 #define DRIVERS_B91_DRIVER_EXT_EXT_RF_H_
21
22 #include "../../../common/compiler.h"
23 #include "../../../common/types.h"
24
25 #define DMA_RFRX_LEN_HW_INFO 0 // 826x: 8
26 #define DMA_RFRX_OFFSET_HEADER 4 // 826x: 12
27 #define DMA_RFRX_OFFSET_RFLEN 5 // 826x: 13
28 #define DMA_RFRX_OFFSET_DATA 6 // 826x: 14
29
30 #define DMA_RFRX_OFFSET_CRC24(p) (p[DMA_RFRX_OFFSET_RFLEN]+6) //data len:3
31 #define DMA_RFRX_OFFSET_TIME_STAMP(p) (p[DMA_RFRX_OFFSET_RFLEN]+9) //data len:4
32 #define DMA_RFRX_OFFSET_FREQ_OFFSET(p) (p[DMA_RFRX_OFFSET_RFLEN]+13) //data len:2
33 #define DMA_RFRX_OFFSET_RSSI(p) (p[DMA_RFRX_OFFSET_RFLEN]+15) //data len:1, signed
34
35 #define RF_BLE_RF_PAYLOAD_LENGTH_OK(p) (p[5] <= reg_rf_rxtmaxlen)
36 #define RF_BLE_RF_PACKET_CRC_OK(p) ((p[p[5]+5+11] & 0x01) == 0x0)
37 #define RF_BLE_PACKET_VALIDITY_CHECK(p) (RF_BLE_RF_PAYLOAD_LENGTH_OK(p) && RF_BLE_RF_PACKET_CRC_OK(p))
38
39
40
41 typedef enum {
42 RF_ACC_CODE_TRIGGER_AUTO = BIT(0), /**< auto trigger */
43 RF_ACC_CODE_TRIGGER_MANU = BIT(1), /**< manual trigger */
44 } rf_acc_trigger_mode;
45
46
47
48
49 extern signed char ble_txPowerLevel;
50
51 _attribute_ram_code_ void ble_rf_set_rx_dma(unsigned char *buff, unsigned char fifo_byte_size);
52
53 _attribute_ram_code_ void ble_rf_set_tx_dma(unsigned char fifo_dep, unsigned char fifo_byte_size);
54
55 _attribute_ram_code_ void ble_tx_dma_config(void);
56
57 _attribute_ram_code_ void ble_rx_dma_config(void);
58
59 void rf_drv_ble_init(void);
60
61 /**
62 * @brief This function serves to settle adjust for RF Tx.This function for adjust the differ time
63 * when rx_dly enable.
64 * @param txstl_us - adjust TX settle time.
65 * @return none
66 */
rf_tx_settle_adjust(unsigned short txstl_us)67 static inline void rf_tx_settle_adjust(unsigned short txstl_us)
68 {
69 REG_ADDR16(0x80140a04) = txstl_us;
70 }
71
72 /**
73 * @brief This function serves to reset RF BaseBand
74 * @param[in] none.
75 * @return none.
76 */
rf_reset_baseband(void)77 static inline void rf_reset_baseband(void)
78 {
79 REG_ADDR8(0x801404e3) = 0; //rf_reset_baseband,rf reg need re-setting
80 REG_ADDR8(0x801404e3) = BIT(0); //release reset signal
81 }
82
83 /**
84 * @brief This function serves to set RF access code value.
85 * @param[in] ac - the address value.
86 * @return none
87 */
rf_set_ble_access_code_value(unsigned int ac)88 static inline void rf_set_ble_access_code_value (unsigned int ac)
89 {
90 write_reg32 (0x80140808, ac);
91 }
92
93 /**
94 * @brief This function serves to set RF access code.
95 * @param[in] p - the address to access.
96 * @return none
97 */
rf_set_ble_access_code(unsigned char * p)98 static inline void rf_set_ble_access_code (unsigned char *p)
99 {
100 write_reg32 (0x80140808, p[3] | (p[2]<<8) | (p[1]<<16) | (p[0]<<24));
101 }
102
103 /**
104 * @brief This function serves to reset function for RF.
105 * @param none
106 * @return none
107 *******************need driver change
108 */
reset_sn_nesn(void)109 static inline void reset_sn_nesn(void)
110 {
111 REG_ADDR8(0x80140a01) = 0x01;
112 }
113
114 /**
115 * @brief This function serves to set RF access code advantage.
116 * @param none.
117 * @return none.
118 */
rf_set_ble_access_code_adv(void)119 static inline void rf_set_ble_access_code_adv (void)
120 {
121 write_reg32 (0x0140808, 0xd6be898e);
122 }
123
124
125 /**
126 * @brief This function serves to triggle accesscode in coded Phy mode.
127 * @param none.
128 * @return none.
129 */
rf_trigle_codedPhy_accesscode(void)130 static inline void rf_trigle_codedPhy_accesscode(void)
131 {
132 write_reg8(0x140c25,read_reg8(0x140c25)|0x01);
133 }
134
135 /**
136 * @brief This function performs to enable RF Tx.
137 * @param[in] none.
138 * @return none.
139 */
rf_ble_tx_on()140 static inline void rf_ble_tx_on ()
141 {
142 write_reg8 (0x80140a02, 0x45 | BIT(4)); // TX enable
143 }
144
145 /**
146 * @brief This function performs to done RF Tx.
147 * @param[in] none.
148 * @return none.
149 */
rf_ble_tx_done()150 static inline void rf_ble_tx_done ()
151 {
152 write_reg8 (0x80140a02, 0x45);
153 }
154
155
156 /**
157 * @brief This function serves to set RX first timeout value.
158 * @param[in] tm - timeout, unit: uS.
159 * @return none.
160 */
rf_set_1st_rx_timeout(unsigned int tm)161 static inline void rf_set_1st_rx_timeout(unsigned int tm)
162 {
163 reg_rf_ll_rx_fst_timeout = tm;
164 }
165
166
167 /**
168 * @brief This function serves to set RX timeout value.
169 * @param[in] tm - timeout, unit: uS, range: 0 ~ 0xfff
170 * @return none.
171 */
rf_ble_set_rx_timeout(u16 tm)172 static inline void rf_ble_set_rx_timeout(u16 tm)
173 {
174 reg_rf_rx_timeout = tm;
175 }
176
177
178
179 typedef enum{
180 FSM_BTX = 0x81,
181 FSM_BRX = 0x82,
182 FSM_STX = 0x85,
183 FSM_SRX = 0x86,
184 FSM_TX2RX = 0x87,
185 FSM_RX2TX = 0x88,
186 }fsm_mode_e;
187
188
189 /**
190 * @brief This function serves to RF trigger RF state machine.
191 * @param[in] mode - FSM mode.
192 * @param[in] tx_addr - DMA TX buffer, if not TX, must be "NULL"
193 * @param[in] tick - FAM Trigger tick.
194 * @return none.
195 */
196 void rf_start_fsm(fsm_mode_e mode, void* tx_addr, unsigned int tick);
197
198
199 #define rf_set_ble_channel rf_set_ble_chn
200
201
202 /**
203 * @brief This function performs to switch PHY test mode.
204 * @param[in] mode - PHY mode
205 * @return none.
206 */
207 void rf_switchPhyTestMode(rf_mode_e mode);
208
209
210
211
212
213
214
215
216
217
218 //TODO: merge into driver
219 #define STOP_RF_STATE_MACHINE ( REG_ADDR8(0x80140a00) = 0x80 )
220 enum{
221 FLD_RF_SN = BIT(0),
222 };
223
224
225
226 /**
227 * @brief This function serves to enable zb_rt interrupt source.
228 * @return none
229 */
zb_rt_irq_enable(void)230 static inline void zb_rt_irq_enable(void)
231 {
232 plic_interrupt_enable(IRQ15_ZB_RT);
233 }
234
235
236
237
238
239 #if RF_RX_SHORT_MODE_EN//open rx dly
240 //TX settle time
241
242 #define LL_SCAN_TX_SETTLE 63
243 #define LL_SCANRSP_TX_SETTLE 78 //63+15=78
244
245
246 //TODO: need debug
247 #define LL_TX_STL_TIFS_1M 63
248 #define LL_TX_STL_TIFS_2M (LL_TX_STL_TIFS_1M + 24)
249 #define LL_TX_STL_TIFS_CODED (LL_TX_STL_TIFS_1M + 40)
250
251
252 #define LL_TX_STL_ADV_1M 84
253 #define LL_TX_STL_ADV_2M 115
254 #define LL_TX_STL_ADV_CODED 124
255
256 #define LL_SLAVE_TX_SETTLE 86
257 #define LL_SLAVE_TX_STL_2M 117
258 #define LL_SLAVE_TX_STL_CODED 125
259
260 #define LL_MASTER_TX_SETTLE 87
261 #define LL_MASTER_TX_STL_2M 117
262 #define LL_MASTER_TX_STL_CODED 125
263
264 #else// close rx dly
265 #error "add code here"
266 #endif
267
268
269 /* AD convert delay : timing cost on RF analog to digital convert signal process:
270 * Eagle 1M: 20uS 2M: 10uS; 500K(S2): 14uS 125K(S8): 14uS
271 * Jaguar 1M: 20uS 2M: 10uS; 500K(S2): 14uS 125K(S8): 14uS
272 */
273 #define AD_CONVERT_DLY_1M 20
274 #define AD_CONVERT_DLY_2M 10
275 #define AD_CONVERT_DLY_CODED 14
276
277
rf_ble_set_1m_phy(void)278 static inline void rf_ble_set_1m_phy(void)
279 {
280 write_reg8(0x140e3d,0x61);
281 write_reg32(0x140e20,0x23200a16);
282 write_reg8(0x140c20,0xc4);
283 write_reg8(0x140c22,0x00);
284 write_reg8(0x140c4d,0x01);
285 write_reg8(0x140c4e,0x1e);
286 write_reg16(0x140c36,0x0eb7);
287 write_reg16(0x140c38,0x71c4);
288 write_reg8(0x140c73,0x01);
289 #if RF_RX_SHORT_MODE_EN
290 write_reg8(0x140c79,0x38); //default:0x00;RX_DIS_PDET_BLANK
291 #else
292 write_reg8(0x140c79,0x08);
293 #endif
294 write_reg16(0x140cc2,0x4b39);
295 write_reg32(0x140cc4,0x796e6256);
296 write_reg32(0x140800,0x4446081f);
297 write_reg16(0x140804,0x04f5);
298 }
299
300
rf_ble_set_2m_phy(void)301 static inline void rf_ble_set_2m_phy(void)
302 {
303 write_reg8(0x140e3d,0x41);
304 write_reg32(0x140e20,0x26432a06);
305 write_reg8(0x140c20,0xc4);
306 write_reg8(0x140c22,0x01);
307 write_reg8(0x140c4d,0x01);
308 write_reg8(0x140c4e,0x1e);
309 write_reg16(0x140c36,0x0eb7);
310 write_reg16(0x140c38,0x71c4);
311 write_reg8(0x140c73,0x01);
312 #if RF_RX_SHORT_MODE_EN
313 write_reg8(0x140c79,0x30); //default:0x00;RX_DIS_PDET_BLANK
314 #else
315 write_reg8(0x140c79,0x00);
316 #endif
317 write_reg16(0x140cc2,0x4c3b);
318 write_reg32(0x140cc4,0x7a706458);
319 write_reg32(0x140800,0x4446081f);
320 write_reg16(0x140804,0x04e5);
321 }
322
323
324
325
rf_ble_set_coded_phy_common(void)326 static inline void rf_ble_set_coded_phy_common(void)
327 {
328 write_reg8(0x140e3d,0x61);
329 write_reg32(0x140e20,0x23200a16);
330 write_reg8(0x140c20,0xc5);
331 write_reg8(0x140c22,0x00);
332 write_reg8(0x140c4d,0x01);
333 write_reg8(0x140c4e,0xf0);
334 write_reg16(0x140c38,0x7dc8);
335 write_reg8(0x140c73,0x21);
336 #if RF_RX_SHORT_MODE_EN
337 write_reg8(0x140c79,0x30);
338 #else
339 write_reg8(0x140c79,0x00);
340 #endif
341 write_reg16(0x140cc2,0x4836);
342 write_reg32(0x140cc4,0x796e6254);
343 write_reg32(0x140800,0x444a081f);
344 }
345
346
rf_ble_set_coded_phy_s2(void)347 static inline void rf_ble_set_coded_phy_s2(void)
348 {
349 write_reg16(0x140c36,0x0cee);
350 write_reg16(0x140804,0xa4f5);
351 }
352
353
rf_ble_set_coded_phy_s8(void)354 static inline void rf_ble_set_coded_phy_s8(void)
355 {
356 write_reg16(0x140c36,0x0cf6);
357 write_reg16(0x140804,0xb4f5);
358 }
359
360
361 #endif /* DRIVERS_B91_DRIVER_EXT_EXT_RF_H_ */
362
