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Searched refs:reg_hspi_panel_ctrl (Results 1 – 2 of 2) sorted by relevance

/hal_telink-latest/tlsr9/drivers/B91/
Dspi.h866 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN); in hspi_3line_dcx_en()
875 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN); in hspi_3line_dcx_dis()
884 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX); in hspi_set_3line_dcx_data()
893 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX); in hspi_set_3line_dcx_cmd()
902 reg_hspi_panel_ctrl &= (~FLD_HSPI_PANEL_2DATA_LANE); in hspi_set_panel_2data_lane_mode()
903 reg_hspi_panel_ctrl |= (mode & 0xf) << 2; in hspi_set_panel_2data_lane_mode()
/hal_telink-latest/tlsr9/drivers/B91/reg_include/
Dspi_reg.h393 #define reg_hspi_panel_ctrl REG_ADDR8(HSPI_BASE_ADDR+0x22) macro