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Searched refs:pll_clk (Results 1 – 2 of 2) sorted by relevance

/hal_telink-latest/tlsr9/drivers/B91/
Dclock.c50 .pll_clk = 192,
290 sys_clk.pll_clk = (pll >> 8); in clock_init()
293 write_reg8(0x1401fb, sys_clk.pll_clk/48); in clock_init()
313 sys_clk.mspi_clk = sys_clk.pll_clk / mspi_clk_div; in clock_init()
340 sys_clk.cclk = sys_clk.pll_clk / cclk_div; in clock_init()
344 sys_clk.cclk = sys_clk.pll_clk; in clock_init()
Dclock.h64 unsigned short pll_clk; /**< pll clk */ member