Searched refs:PLL_DIV4_TO_CCLK (Results 1 – 1 of 1) sorted by relevance
54 #define CCLK_48M_HCLK_48M_PCLK_24M clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV4_TO_CCLK, CCLK_D…118 PLL_DIV4_TO_CCLK = 4, enumerator