Searched refs:PAD_PLL_DIV (Results 1 – 2 of 2) sorted by relevance
| /hal_telink-latest/tlsr9/drivers/B91/ |
| D | clock.h | 51 #define CCLK_16M_HCLK_16M_PCLK_16M clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV12_TO_CCLK, CCLK…
52 #define CCLK_24M_HCLK_24M_PCLK_24M clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV8_TO_CCLK, CCLK_D…
53 #define CCLK_32M_HCLK_32M_PCLK_16M clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV6_TO_CCLK, CCLK_D…
54 #define CCLK_48M_HCLK_48M_PCLK_24M clock_init(PLL_CLK_192M, PAD_PLL_DIV, PLL_DIV4_TO_CCLK, CCLK_D…
100 PAD_PLL_DIV, enumerator
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| D | clock.c | 337 if(PAD_PLL_DIV == src) in clock_init()
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