1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file usb_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef USB_REG_H 28 #define USB_REG_H 29 #include "../sys.h" 30 31 /******************************* usb registers: 0x100800 ******************************/ 32 #define reg_ctrl_ep_ptr REG_ADDR8(0x100800) 33 #define reg_ctrl_ep_dat REG_ADDR8(0x100801) 34 #define reg_ctrl_ep_ctrl REG_ADDR8(0x100802) 35 enum{ 36 FLD_EP_DAT_ACK = BIT(0), 37 FLD_EP_DAT_STALL = BIT(1), 38 FLD_EP_STA_ACK = BIT(2), 39 FLD_EP_STA_STALL = BIT(3), 40 }; 41 42 #define reg_ctrl_ep_irq_sta REG_ADDR8(0x100803) 43 enum{ 44 FLD_CTRL_EP_IRQ_TRANS = BIT_RNG(0,3), 45 FLD_CTRL_EP_IRQ_SETUP = BIT(4), 46 FLD_CTRL_EP_IRQ_DATA = BIT(5), 47 FLD_CTRL_EP_IRQ_STA = BIT(6), 48 FLD_CTRL_EP_IRQ_INTF = BIT(7), 49 }; 50 51 #define reg_ctrl_ep_irq_mode REG_ADDR8(0x100804) 52 enum{ 53 FLD_CTRL_EP_AUTO_ADDR = BIT(0), 54 FLD_CTRL_EP_AUTO_CFG = BIT(1), 55 FLD_CTRL_EP_AUTO_INTF = BIT(2), 56 FLD_CTRL_EP_AUTO_STA = BIT(3), 57 FLD_CTRL_EP_AUTO_SYN = BIT(4), 58 FLD_CTRL_EP_AUTO_DESC = BIT(5), 59 FLD_CTRL_EP_AUTO_FEAT = BIT(6), 60 FLD_CTRL_EP_AUTO_STD = BIT(7), 61 }; 62 63 #define reg_usb_ctrl REG_ADDR8(0x100805) 64 enum{ 65 FLD_USB_CTRL_AUTO_CLK = BIT(0), 66 FLD_USB_CTRL_LOW_SPD = BIT(1), 67 FLD_USB_CTRL_LOW_JITT = BIT(2), 68 FLD_USB_CTRL_TST_MODE = BIT(3), 69 }; 70 71 #define reg_usb_cycl_cali REG_ADDR16(0x100806) 72 #define reg_usb_cych_cali REG_ADDR16(0x100807) 73 #define reg_usb_mdev REG_ADDR8(0x10080a) 74 enum{ 75 FLD_USB_MDEV_SELF_PWR = BIT(0), 76 FLD_USB_MDEV_SUSP_STA = BIT(1), 77 FLD_USB_MDEV_WAKE_FEA = BIT(2), 78 FLD_USB_MDEV_VEND_CMD = BIT(3), 79 FLD_USB_MDEV_VEND_DIS = BIT(4), 80 }; 81 82 #define reg_usb_host_conn REG_ADDR8(0x10080b) 83 #define reg_usb_sups_cyc_cali REG_ADDR8(0x10080c) 84 #define reg_usb_intf_alt REG_ADDR8(0x10080d) 85 #define reg_usb_edp_en REG_ADDR8(0x10080e) 86 typedef enum{ 87 FLD_USB_EDP8_EN = BIT(0), // printer 88 FLD_USB_EDP1_EN = BIT(1), // keyboard 89 FLD_USB_EDP2_EN = BIT(2), // mouse 90 FLD_USB_EDP3_EN = BIT(3), 91 FLD_USB_EDP4_EN = BIT(4), 92 FLD_USB_EDP5_EN = BIT(5), // printer 93 FLD_USB_EDP6_EN = BIT(6), // audio 94 FLD_USB_EDP7_EN = BIT(7), // audio 95 }usb_ep_en_e; 96 97 #define reg_usb_irq_mask REG_ADDR8(0x10080f) 98 enum{ 99 FLD_USB_IRQ_RESET_MASK = BIT(0), 100 FLD_USB_IRQ_250US_MASK = BIT(1), 101 FLD_USB_IRQ_SUSPEND_MASK = BIT(2), 102 FLD_USB_IRQ_RESET_LVL = BIT(3), 103 FLD_USB_IRQ_250US_LVL = BIT(4), 104 FLD_USB_IRQ_RESET_O = BIT(5), 105 FLD_USB_IRQ_250US_O = BIT(6), 106 FLD_USB_IRQ_SUSPEND_O = BIT(7), 107 }; 108 109 #define reg_usb_ep8123_ptr REG_ADDR32(0x100810) 110 #define reg_usb_ep8_ptr REG_ADDR8(0x100810) 111 #define reg_usb_ep1_ptr REG_ADDR8(0x100811) 112 #define reg_usb_ep2_ptr REG_ADDR8(0x100812) 113 #define reg_usb_ep3_ptr REG_ADDR8(0x100813) 114 #define reg_usb_ep4567_ptr REG_ADDR32(0x100814) 115 #define reg_usb_ep4_ptr REG_ADDR8(0x100814) 116 #define reg_usb_ep5_ptr REG_ADDR8(0x100815) 117 #define reg_usb_ep6_ptr REG_ADDR8(0x100816) 118 #define reg_usb_ep7_ptr REG_ADDR8(0x100817) 119 #define reg_usb_ep_ptr(i) REG_ADDR8(0x100810+((i) & 0x07)) 120 121 #define reg_usb_ep8123_dat REG_ADDR32(0x100818) 122 #define reg_usb_ep8_dat REG_ADDR8(0x100818) 123 #define reg_usb_ep1_dat REG_ADDR8(0x100819) 124 #define reg_usb_ep2_dat REG_ADDR8(0x10081a) 125 #define reg_usb_ep3_dat REG_ADDR8(0x10081b) 126 #define reg_usb_ep4567_dat REG_ADDR32(0x10081c) 127 #define reg_usb_ep4_dat REG_ADDR8(0x10081c) 128 #define reg_usb_ep5_dat REG_ADDR8(0x10081d) 129 #define reg_usb_ep6_dat REG_ADDR8(0x10081e) 130 #define reg_usb_ep7_dat REG_ADDR8(0x10081f) 131 #define reg_usb_ep_dat(i) REG_ADDR8(0x100818+((i) & 0x07)) 132 133 #define reg_usb_ep8_ctrl REG_ADDR8(0x100820) 134 #define reg_usb_ep1_ctrl REG_ADDR8(0x100821) 135 #define reg_usb_ep2_ctrl REG_ADDR8(0x100822) 136 #define reg_usb_ep3_ctrl REG_ADDR8(0x100823) 137 #define reg_usb_ep4_ctrl REG_ADDR8(0x100824) 138 #define reg_usb_ep5_ctrl REG_ADDR8(0x100825) 139 #define reg_usb_ep6_ctrl REG_ADDR8(0x100826) 140 #define reg_usb_ep7_ctrl REG_ADDR8(0x100827) 141 #define reg_usb_ep_ctrl(i) REG_ADDR8(0x100820+((i) & 0x07)) 142 143 enum{ 144 FLD_USB_EP_BUSY = BIT(0), 145 FLD_USB_EP_STALL = BIT(1), 146 FLD_USB_EP_DAT0 = BIT(2), 147 FLD_USB_EP_DAT1 = BIT(3), 148 FLD_USB_EP_MONO = BIT(6), 149 FLD_USB_EP_EOF_ISO = BIT(7), 150 }; 151 152 #define reg_usb_ep8123_buf_addr REG_ADDR32(0x100828) 153 #define reg_usb_ep8_buf_addr REG_ADDR8(0x100828) 154 #define reg_usb_ep1_buf_addr REG_ADDR8(0x100829) 155 #define reg_usb_ep2_buf_addr REG_ADDR8(0x10082a) 156 #define reg_usb_ep3_buf_addr REG_ADDR8(0x10082b) 157 #define reg_usb_ep4567_buf_addr REG_ADDR32(0x10082c) 158 #define reg_usb_ep4_buf_addr REG_ADDR8(0x10082c) 159 #define reg_usb_ep5_buf_addr REG_ADDR8(0x10082d) 160 #define reg_usb_ep6_buf_addr REG_ADDR8(0x10082e) 161 #define reg_usb_ep7_buf_addr REG_ADDR8(0x10082f) 162 #define reg_usb_ep_buf_addr(i) REG_ADDR8(0x100828+((i) & 0x07)) 163 164 165 #define reg_usb_ram_ctrl REG_ADDR8(0x100830) 166 167 enum{ 168 FLD_USB_CEN_PWR_DN = BIT(0), 169 FLD_USB_CLK_PWR_DN = BIT(1), 170 FLD_USB_WEN_PWR_DN = BIT(3), 171 FLD_USB_CEN_FUNC = BIT(4), 172 }; 173 174 #define reg_usb_iso_mode REG_ADDR8(0x100838) 175 176 #define reg_usb_ep_irq_status REG_ADDR8(0x100839) 177 #define reg_usb_ep_irq_mask REG_ADDR8(0x10083a) 178 typedef enum{ 179 FLD_USB_EDP8_IRQ = BIT(0), 180 FLD_USB_EDP1_IRQ = BIT(1), 181 FLD_USB_EDP2_IRQ = BIT(2), 182 FLD_USB_EDP3_IRQ = BIT(3), 183 FLD_USB_EDP4_IRQ = BIT(4), 184 FLD_USB_EDP5_IRQ = BIT(5), 185 FLD_USB_EDP6_IRQ = BIT(6), 186 FLD_USB_EDP7_IRQ = BIT(7), 187 }usb_ep_irq_e ; 188 189 190 #define reg_usb_ep8_send_max REG_ADDR8(0x10083b) 191 #define reg_usb_ep8_send_thre REG_ADDR8(0x10083c) 192 #define reg_usb_ep8_fifo_mode REG_ADDR8(0x10083d) 193 enum{ 194 FLD_USB_ENP8_FIFO_MODE = BIT(0), 195 FLD_USB_ENP8_FULL_FLAG = BIT(1), 196 }; 197 198 #define reg_usb_ep_max_size REG_ADDR8(0x10083e) 199 #define reg_usb_ep_tick REG_ADDR8(0x10083f) 200 201 #define reg_usb_mic_dat0 REG_ADDR16(0x1800) 202 #define reg_usb_mic_dat1 REG_ADDR16(0x1802) 203 204 #endif 205
