1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file rf_reg.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #ifndef RF_REG_H 28 #define RF_REG_H 29 #include "../sys.h" 30 31 ///******************************* RF ******************************/ 32 #define APBADDR 0x140000 33 #define BBADDR APBADDR+0x800 //0x140800 34 #define RADIOADDR APBADDR+0xe00 //0x140e00 35 #define MODEMADDR APBADDR+0xc00 //0x140c00 36 #define CHNADDR 0x100400 37 #define APBRG_BASE 0x140000 38 #define APBRG_APB_BASE (APBRG_BASE+0x0000) 39 40 41 #define REG_TL_RADIO_BASE_ADDR (APBRG_BASE+0x0e00) 42 43 44 #define reg_rf_bb_auto_ctrl REG_ADDR8(0x10050c) 45 46 enum{ 47 FLD_RF_TX_MULTI_EN = BIT(0), 48 FLD_RF_RX_MULTI_EN = BIT(1), 49 FLD_RF_CH_0_RNUM_EN_BK = BIT(2), 50 FLD_RF_CH_1_RNUM_EN_BK = BIT(3), 51 FLD_RF_CH1_RX_ERR_EN = BIT(4), 52 FLD_RF_DMA_REQ_D1_EN = BIT(5), 53 }; 54 #define reg_rf_bb_tx_chn_dep REG_ADDR8(0x1004f3) 55 #define reg_rf_bb_tx_size REG_ADDR8(0x1004f2) 56 57 #define reg_rf_dma_rx_wptr REG_ADDR8(0x001004f4) 58 #define reg_rf_dma_rx_rptr REG_ADDR8(0x001004f5) 59 60 #define reg_rf_dma_tx_rptr(i) REG_ADDR8(0x00100501 + (i << 1)) 61 #define reg_rf_dma_tx_wptr(i) REG_ADDR8(0x00100500 + (i << 1)) 62 63 #define reg_rf_bb_rx_size REG_ADDR8(CHNADDR+0xf6) 64 65 66 67 #define reg_rf_rx_wptr_mask REG_ADDR8(CHNADDR+0x10d) 68 69 70 71 //****************************** RF_Register_list ******************************/ 72 #define REG_BASEBAND_BASE_ADDR 0x0140800 73 74 75 #define reg_rf_tx_mode1 REG_ADDR8(REG_BASEBAND_BASE_ADDR) 76 enum{ 77 FLD_RF_DMA_EN = BIT(0), 78 FLD_RF_CRC_EN = BIT(1), 79 FLD_RF_TX_FMT = BIT_RNG(2,3), 80 FLD_RF_TX_XOR_MODE = BIT(4), 81 FLD_RF_TX_TEST_DATA = BIT(5), 82 FLD_RF_TX_TEST_EN = BIT(6), 83 FLD_RF_BB_DEC = BIT(7), 84 }; 85 86 87 #define reg_rf_tx_mode2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x01) 88 enum{ 89 FLD_RF_ZB_PN_EN = BIT(0), 90 FLD_RF_RESERVED0 = BIT_RNG(1,2), 91 FLD_RF_V_PN_EN = BIT(3), 92 FLD_RF_RESERVED1 = BIT_RNG(4,5), 93 FLD_RF_TX_OUT_PLR = BIT(6), 94 }; 95 96 97 #define reg_rf_preamble_trail REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x02) 98 enum{ 99 FLD_RF_PREAMBLE_LEN = BIT_RNG(0,4), 100 FLD_RF_TRAILER_LEN = BIT_RNG(5,7), 101 }; 102 103 104 #define reg_rf_bbdbg REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x03) 105 enum{ 106 FLD_RF_SLOW_EN = BIT(0), 107 FLD_RF_SLOW_SEL = BIT(1), 108 FLD_RF_XMODE_EN = BIT(2), 109 FLD_RF_REV_ORDER = BIT(3), 110 FLD_RF_TX_MODE = BIT(4), 111 FLD_RF_R_DBG_SEL0 = BIT(5), 112 FLD_RF_MODEM1M_PAT = BIT(6), 113 FLD_RF_R_DBG_SEL1 = BIT(7), 114 }; 115 116 117 #define reg_rf_format REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x04) 118 enum{ 119 FLD_RF_HEAD_MODE = BIT_RNG(0,1), 120 FLD_RF_CRC_MODE = BIT_RNG(2,3), 121 FLD_RF_BLE_1M = BIT(4), 122 FLD_RF_BLE_WT = BIT(5), 123 FLD_RF_TX_NOACK = BIT(6), 124 FLD_RF_PN_AUTO = BIT(7), 125 }; 126 127 128 //#define reg_rf_acclen REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x05) 129 #define reg_rf_acc_len REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x05) 130 enum{ 131 FLD_RF_ACC_LEN = BIT_RNG(0,2), 132 FLD_RF_LR_TX_SEL = BIT(4), 133 FLD_RF_BLE_LR = BIT(5), 134 }; 135 136 137 138 #define reg_rf_sblen REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x06) 139 140 141 #define reg_rf_rxchn REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x07) 142 enum{ 143 FLD_RF_TEST_TXON = BIT(6), 144 FLD_RF_TEST_TXON_EN = BIT(7), 145 }; 146 147 #define reg_rf_access_code REG_ADDR32(REG_BASEBAND_BASE_ADDR+0x08) 148 #define reg_rf_access_0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x08) 149 #define reg_rf_access_1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x09) 150 #define reg_rf_access_2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x0a) 151 #define reg_rf_access_3 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x0b) 152 #define reg_rf_access_4 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x0c) 153 154 155 #define reg_rf_pn REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x0d) 156 enum{ 157 FLD_RF_PN_INIT = BIT_RNG(0,5), 158 }; 159 160 161 #define reg_rf_access_5 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x10) 162 #define reg_rf_access_6 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x11) 163 #define reg_rf_access_7 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x12) 164 #define reg_rf_access_8 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x13) 165 #define reg_rf_access_9 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x14) 166 #define reg_rf_access_10 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x18) 167 #define reg_rf_access_11 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x19) 168 #define reg_rf_access_12 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x1a) 169 #define reg_rf_access_13 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x1b) 170 #define reg_rf_access_code_base_pipe0 0x140808 171 #define reg_rf_access_code_base_pipe2 0x140818 172 173 #define reg_rf_txfifo REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x1c) 174 enum{ 175 FLD_RF_TX_FIFO_FULL = BIT(0), 176 FLD_RF_TX_ACT_2D = BIT(1), 177 }; 178 179 180 #define reg_rf_rxgth1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x21) 181 enum{ 182 FLD_RF_R_PILOT_LEN_O = BIT_RNG(0,3), 183 FLD_RF_R_ZB_SFD_O = BIT(4), 184 FLD_RF_R_PKTLEN_O = BIT(5), 185 FLD_RF_R_SN_LEN_O = BIT(6), 186 FLD_RF_R_LEN_0_EN_O = BIT(7), 187 }; 188 189 190 #define reg_rf_rxsfd0_num REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x22) 191 enum{ 192 FLD_RF_RXCHN_MAN_EN = BIT(3), 193 FLD_RF_RXCHN_MAN = BIT_RNG(4,6), 194 }; 195 196 197 #define reg_rf_crc_init0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x24) 198 #define reg_rf_crc_init1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x25) 199 #define reg_rf_crc_init2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x26) 200 201 202 #define reg_rf_ctrl_0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x27) 203 enum{ 204 FLD_RF_H1M_ODD = BIT(0), 205 FLD_RF_REV_ZB_SAMP = BIT(1), 206 FLD_RF_SFD_LAST_CHIP = BIT(2), 207 }; 208 209 210 #define reg_rf_rxmode REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x28) 211 enum{ 212 FLD_RF_RX_ENABLE = BIT(0), 213 }; 214 215 216 #define reg_rf_rxclk_on REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x2a) 217 enum{ 218 FLD_RF_CLKON_O = BIT_RNG(0,1), 219 }; 220 221 222 #define reg_rf_rxclk_auto REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x2b) 223 enum{ 224 FLD_RF_CLK_AUTO = BIT_RNG(0,1), 225 }; 226 227 228 #define reg_rf_rxdma_hs REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x2c) 229 enum{ 230 FLD_RF_RXDMA_HS = BIT(0), 231 }; 232 233 234 #define reg_rf_rxtcrcpkt REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x30) 235 enum{ 236 FLD_RF_FILTER_CRC_PKT = BIT(0), 237 FLD_RF_EN_TS_RX = BIT(2), 238 FLD_RF_EN_TS_TX = BIT(3), 239 FLD_RF_LEN_SET_O = BIT_RNG(4,5), 240 }; 241 242 243 #define reg_rf_rxtmaxlen REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x31) 244 245 246 #define reg_rf_rxlatf REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x33) 247 enum{ 248 FLD_RF_R_LATF_CNT_O = BIT_RNG(0,3), 249 FLD_RF_R_LATF_AT_END_O = BIT(4), 250 }; 251 252 253 #define reg_rf_bank_cnt REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x34) 254 enum{ 255 FLD_RF_BANK_CNT = BIT_RNG(0,2), 256 }; 257 258 259 #define reg_rf_rxsupp REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x38) 260 enum{ 261 FLD_RF_RX_SUPP_D_EN = BIT(0), 262 FLD_RF_RX_SUPP_A_EN = BIT(1), 263 FLD_RF_TX_SUPP_D_EN = BIT(2), 264 FLD_RF_TX_SUPP_A_EN = BIT(3), 265 FLD_RF_ANT_NUM = BIT_RNG(4,7), 266 }; 267 268 269 #define reg_rf_tx_antoffset REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x39) 270 #define reg_rf_rx_antoffset REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3a) 271 #define reg_rf_samp_offset REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3b) 272 273 274 #define reg_rf_man_ant_slot REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3c) 275 enum{ 276 FLD_RF_ANT_SEL_MAN = BIT_RNG(0,2), 277 FLD_RF_ANT_SEL_MAN_EN = BIT(3), 278 FLD_RF_SLOT_1US_MAN_EN = BIT(4), 279 FLD_RF_SLOT_1US_MAN = BIT(5), 280 FLD_RF_ANT_PAT = BIT_RNG(6,7), 281 }; 282 283 284 #define reg_rf_sof_offset REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3d) 285 enum{ 286 FLD_RF_ANT_SOF_OFFSET = BIT_RNG(0,1), 287 FLD_RF_SAMP_SOF_OFFSET = BIT_RNG(2,3), 288 FLD_RF_SUPP_MODE = BIT_RNG(4,6), 289 }; 290 291 292 #define reg_rf_mode_ctrl0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3e) 293 enum{ 294 FLD_RF_INTV_MODE = BIT_RNG(0,1), 295 FLD_RF_IQ_SAMP_EN = BIT(2), 296 FLD_RF_IQ_SAMP_INTERVAL = BIT_RNG(4,7), 297 }; 298 299 300 #define reg_rf_iq_samp_start REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x3f) 301 302 303 #define reg_rf_dec_err REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x40) 304 enum{ 305 FLD_RF_SS = BIT_RNG(0,2), 306 FLD_RF_PKT_DEC_ERR = BIT_RNG(4,7), 307 }; 308 309 #define reg_rf_timestamp REG_ADDR32(REG_BASEBAND_BASE_ADDR+0x50) 310 #define reg_rf_tstamp0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x50) 311 enum{ 312 FLD_RF_R_TSTAMP0 = BIT_RNG(0,7), 313 }; 314 315 316 #define reg_rf_tstamp1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x51) 317 enum{ 318 FLD_RF_R_TSTAMP1 = BIT_RNG(0,7), 319 }; 320 321 322 #define reg_rf_tstamp2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x52) 323 enum{ 324 FLD_RF_R_TSTAMP2 = BIT_RNG(0,7), 325 }; 326 327 328 #define reg_rf_tstamp3 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x53) 329 enum{ 330 FLD_RF_R_TSTAMP3 = BIT_RNG(0,7), 331 }; 332 333 334 #define reg_rf_ant_lut_0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x68) 335 enum{ 336 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 337 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 338 }; 339 340 #if 0 341 #define reg_rf_ant_lut_1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x69) 342 enum{ 343 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 344 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 345 }; 346 347 348 #define reg_rf_ant_lut_2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6a) 349 enum{ 350 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 351 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 352 }; 353 354 355 #define reg_rf_ant_lut_3 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6b) 356 enum{ 357 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 358 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 359 }; 360 361 362 #define reg_rf_ant_lut_4 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6c) 363 enum{ 364 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 365 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 366 }; 367 368 369 #define reg_rf_ant_lut_5 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6d) 370 enum{ 371 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 372 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 373 }; 374 375 376 #define reg_rf_ant_lut_6 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6e) 377 enum{ 378 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 379 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 380 }; 381 382 383 #define reg_rf_ant_lut_7 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x6f) 384 enum{ 385 FLD_RF_ANT_LUT0 = BIT_RNG(0,2), 386 FLD_RF_ANT_LUT1 = BIT_RNG(4,6), 387 }; 388 #endif 389 390 #define reg_rf_rxdma_adr 0x140880 391 #define reg_rf_rxdma_fifo0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x80) 392 enum{ 393 FLD_RF_RXDMA_FIFO0 = BIT_RNG(0,7), 394 }; 395 396 397 #define reg_rf_rxdma_fifo1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x81) 398 enum{ 399 FLD_RF_RXDMA_FIFO1 = BIT_RNG(0,7), 400 }; 401 402 403 #define reg_rf_rxdma_fifo2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x82) 404 enum{ 405 FLD_RF_RXDMA_FIFO2 = BIT_RNG(0,7), 406 }; 407 408 409 #define reg_rf_rxdma_fifo3 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x83) 410 enum{ 411 FLD_RF_RXDMA_FIFO3 = BIT_RNG(0,7), 412 }; 413 414 #define reg_rf_txdma_adr 0x140884 415 #define reg_rf_txdma_fifo0 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x84) 416 enum{ 417 FLD_RF_TXDMA_FIFO0 = BIT_RNG(0,7), 418 }; 419 420 421 #define reg_rf_txdma_fifo1 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x85) 422 enum{ 423 FLD_RF_TXDMA_FIFO1 = BIT_RNG(0,7), 424 }; 425 426 427 #define reg_rf_txdma_fifo2 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x86) 428 enum{ 429 FLD_RF_TXDMA_FIFO2 = BIT_RNG(0,7), 430 }; 431 432 433 #define reg_rf_txdma_fifo3 REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x87) 434 enum{ 435 FLD_RF_TXDMA_FIFO3 = BIT_RNG(0,7), 436 }; 437 438 439 440 /** 441 * BB_LL 442 */ 443 #define REG_BB_LL_BASE_ADDR 0x0140a00 444 445 446 #define reg_rf_ll_cmd REG_ADDR8(REG_BB_LL_BASE_ADDR) 447 enum{ 448 FLD_RF_R_CMD = BIT_RNG(0,3), 449 FLD_RF_R_STOP = 0, 450 FLD_RF_R_BTX = 1, 451 FLD_RF_R_BRX = 2, 452 FLD_RF_R_PTX = 3, 453 FLD_RF_R_PRX = 4, 454 FLD_RF_R_STX = 5, 455 FLD_RF_R_SRX = 6, 456 FLD_RF_R_STR = 7, 457 FLD_RF_R_SRT = 8, 458 FLD_RF_R_CMD_TRIG = BIT(7), 459 }; 460 461 462 #define reg_rf_ll_rest_pid REG_ADDR8(REG_BB_LL_BASE_ADDR+0x01) 463 enum{ 464 FLD_RF_R_RESET_PID_0 = BIT(0), 465 FLD_RF_R_RESET_PID_1 = BIT(1), 466 FLD_RF_R_RESET_PID_2 = BIT(2), 467 FLD_RF_R_RESET_PID_3 = BIT(3), 468 FLD_RF_R_RESET_PID_4 = BIT(4), 469 FLD_RF_R_RESET_PID_5 = BIT(5), 470 }; 471 472 473 #define reg_rf_ll_ctrl0 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x02) 474 enum{ 475 FLD_RF_R_MD_EN = BIT(0), 476 FLD_RF_R_ID_EN = BIT(1), 477 FLD_RF_R_RX_NOACK_MAN = BIT(2), 478 FLD_RF_R_RX_NOACK_MAN_EN = BIT(3), 479 FLD_RF_R_TX_EN_MAN = BIT(4), 480 FLD_RF_R_RX_EN_MAN = BIT(5), 481 FLD_RF_R_TX_TRIQ_AUTO_EN = BIT(6), 482 FLD_RF_R_S_TX_TIMEOUT_EN = BIT(7), 483 }; 484 485 486 #define reg_rf_ll_ctrl_1 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x03) 487 488 enum{ 489 FLD_RF_FSM_TIMEOUT_EN = BIT(0), 490 FLD_RF_RX_FIRST_TIMEOUT_EN = BIT(1), 491 FLD_RF_RX_TIMEOUT_EN = BIT(2), 492 FLD_RF_CRC_2_EN = BIT(3), 493 494 //BLE mode 495 FLD_RF_BRX_SN_INIT = BIT(4), 496 FLD_RF_BRX_NESN_INIT = BIT(5), 497 FLD_RF_BTX_SN_INIT = BIT(6), 498 FLD_RF_BTX_NESN_INIT = BIT(7), 499 }; 500 501 #define FSM_TIMEOUT_ENABLE ( reg_rf_ll_ctrl_1 |= FLD_RF_FSM_TIMEOUT_EN ) 502 #define FSM_TIMEOUT_DISABLE ( reg_rf_ll_ctrl_1 &= (~FLD_RF_FSM_TIMEOUT_EN) ) 503 504 #define reg_rf_ll_tx_stl REG_ADDR16(REG_BB_LL_BASE_ADDR+0x04) 505 506 #define reg_rf_ll_tx_stl_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x04) 507 508 509 #define reg_rf_ll_tx_stl_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x05) 510 enum{ 511 FLD_RF_R_T_TXSTL_H = BIT_RNG(0,3), 512 }; 513 514 515 #define reg_rf_ll_rxwait_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x06) 516 517 518 #define reg_rf_ll_rxwait_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x07) 519 enum{ 520 FLD_RF_R_T_RXWAIT_H = BIT_RNG(0,3), 521 }; 522 523 524 #define reg_rf_ll_rx_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0a) 525 526 #define reg_rf_rx_timeout REG_ADDR16(REG_BB_LL_BASE_ADDR+0x0a) 527 528 #define reg_rf_ll_rx_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0b) 529 enum{ 530 FLD_RF_R_T_RX_H = BIT_RNG(0,3), 531 }; 532 533 534 #define reg_rf_ll_rxstl_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0c) 535 536 537 #define reg_rf_ll_rxstl_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0d) 538 enum{ 539 FLD_RF_R_T_RXSTL_H = BIT_RNG(0,3), 540 }; 541 542 543 #define reg_rf_ll_txwait_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0e) 544 545 546 #define reg_rf_ll_txwait_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x0f) 547 enum{ 548 FLD_RF_R_T_TXWAIT_H = BIT_RNG(0,3), 549 }; 550 551 552 #define reg_rf_ll_ard_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x10) 553 554 555 #define reg_rf_ll_ard_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x11) 556 enum{ 557 FLD_RF_R_T_ARD_H = BIT_RNG(0,3), 558 }; 559 560 561 #define reg_rf_t_coex_t1 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x12) 562 #define reg_rf_t_coex_t2 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x13) 563 #define reg_rf_ll_max_reset_cnt REG_ADDR8(REG_BB_LL_BASE_ADDR+0x14) 564 565 566 #define reg_rf_ll_ctrl2 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x15) 567 enum{ 568 FLD_RF_R_TXCHN_MAN = BIT_RNG(0,2), 569 FLD_RF_R_NOACK_RECNT_EN = BIT(3), 570 FLD_RF_R_TXCHN_MAN_EN = BIT(4), 571 FLD_RF_R_NOACK_REV_EN = BIT(5), 572 FLD_RF_R_RXIRQ_REPORT_ALL = BIT(6), 573 FLD_RF_R_REP_SN_PID_EN = BIT(7), 574 }; 575 576 577 #define reg_rf_ll_ctrl3 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x16) 578 enum{ 579 FLD_RF_R_TX_EN_DLY_EN = BIT(0), 580 FLD_RF_R_PLL_RESET_EN = BIT(1), 581 FLD_RF_R_CMD_SCHDULE_EN = BIT(2), 582 FLD_RF_R_PLL_EN_MAN = BIT(3), 583 FLD_RF_R_T_TX_EN_DLY = BIT_RNG(4,7), 584 }; 585 586 587 #define reg_rf_ll_pll_reset REG_ADDR8(REG_BB_LL_BASE_ADDR+0x17) 588 #define reg_rf_ll_cmd_schedule REG_ADDR32(REG_BB_LL_BASE_ADDR+0x18) 589 #define reg_rf_ll_cmd_schedule0 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x18) 590 #define reg_rf_ll_cmd_schedule1 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x19) 591 #define reg_rf_ll_cmd_schedule2 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1a) 592 #define reg_rf_ll_cmd_schedule3 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1b) 593 #define reg_rf_ll_irq_mask_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1c) 594 #define reg_rf_ll_irq_mask_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1d) 595 #define reg_rf_irq_mask REG_ADDR16(REG_BB_LL_BASE_ADDR+0x1c) 596 597 598 #define reg_rf_ll_tx_id REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1e) 599 enum{ 600 FLD_RF_R_TX_ID = BIT_RNG(0,6), 601 }; 602 603 604 #define reg_rf_ll_tx_committed REG_ADDR8(REG_BB_LL_BASE_ADDR+0x1f) 605 enum{ 606 FLD_RF_R_TX_COMMITTED = BIT_RNG(0,5), 607 }; 608 609 610 611 #define reg_rf_irq_status REG_ADDR16(REG_BB_LL_BASE_ADDR+0x20) 612 613 typedef enum{ 614 FLD_RF_IRQ_RX = BIT(0), 615 FLD_RF_IRQ_TX = BIT(1), 616 FLD_RF_IRQ_RX_TIMEOUT = BIT(2), 617 FLD_RF_IRQ_RX_FIFO_FULL = BIT(3), 618 FLD_RF_IRQ_RX_CRC_2 = BIT(4), 619 FLD_RF_IRQ_CMD_DONE = BIT(5), 620 FLD_RF_IRQ_FSM_TIMEOUT = BIT(6), 621 FLD_RF_IRQ_TX_RETRYCNT = BIT(7), 622 FLD_RF_IRQ_TX_DS = BIT(8), 623 FLD_RF_IRQ_RX_DR = BIT(9), 624 FLD_RF_IRQ_FIRST_TIMEOUT = BIT(10), 625 FLD_RF_IRQ_INVALID_PID = BIT(11), 626 FLD_RF_IRQ_STX_TIMEOUT = BIT(12), 627 FLD_RF_IRQ_WIFI_DENY = BIT(13), 628 FLD_RF_IRQ_SUPP_OF = BIT(14), 629 FLD_RF_IRQ_RXDMA_OF = BIT(15), 630 FLD_RF_IRQ_ALL = 0X1FFF, 631 }rf_irq_e; 632 633 634 635 #define reg_rf_ll_pid_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x22) 636 enum{ 637 FLD_RF_PID0 = BIT_RNG(0,1), 638 FLD_RF_PID1 = BIT_RNG(2,3), 639 FLD_RF_PID2 = BIT_RNG(4,5), 640 FLD_RF_PID3 = BIT_RNG(6,7), 641 }; 642 643 644 #define reg_rf_ll_pid_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x23) 645 enum{ 646 FLD_RF_PID4 = BIT_RNG(0,1), 647 FLD_RF_PID5 = BIT_RNG(2,3), 648 FLD_RF_NESN = BIT(4), 649 }; 650 651 652 #define reg_rf_ll_2d_sclk REG_ADDR8(REG_BB_LL_BASE_ADDR+0x24) 653 typedef enum { 654 FLD_RF_STATE_MACHINE_IDLE = 0, /**< idle */ 655 FLD_RF_STATE_MACHINE_TX_SETTLE, /**< tx settle*/ 656 FLD_RF_STATE_MACHINE_TX, /**< tx */ 657 FLD_RF_STATE_MACHINE_RX_WAIT, /**< rx wait */ 658 FLD_RF_STATE_MACHINE_RX, /**< rx */ 659 FLD_RF_STATE_MACHINE_TX_WAIT, /**< tx wait */ 660 } state_machine_status_e; 661 662 663 #define reg_rf_ll_retry_cnt REG_ADDR8(REG_BB_LL_BASE_ADDR+0x25) 664 enum{ 665 FLD_RF_LL_RETRY_CNT = BIT_RNG(0,7), 666 }; 667 668 669 #define reg_rf_ll_cnt0 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x26) 670 enum{ 671 FLD_RF_CRC_CNT = BIT_RNG(0,3), 672 FLD_RF_NAK_CNT = BIT_RNG(4,7), 673 }; 674 675 676 #define reg_rf_ll_cnt1 REG_ADDR8(REG_BB_LL_BASE_ADDR+0x27) 677 enum{ 678 FLD_RF_OLD_CNT = BIT_RNG(0,3), 679 FLD_RF_ID_CNT = BIT_RNG(4,7), 680 }; 681 682 #define reg_rf_ll_rx_fst_timeout REG_ADDR32(REG_BB_LL_BASE_ADDR+0x28) 683 #define reg_rf_ll_rx_fst_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x28) 684 #define reg_rf_ll_rx_fst_m REG_ADDR8(REG_BB_LL_BASE_ADDR+0x29) 685 #define reg_rf_ll_rx_fst_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x2a) 686 687 #define reg_rf_ll_fsm_timeout REG_ADDR32(REG_BB_LL_BASE_ADDR+0x2c) 688 #define reg_rf_ll_fsm_timeout_l REG_ADDR8(REG_BB_LL_BASE_ADDR+0x2c) 689 #define reg_rf_ll_fsm_timeout_m REG_ADDR8(REG_BB_LL_BASE_ADDR+0x2d) 690 #define reg_rf_ll_fsm_timeout_h REG_ADDR8(REG_BB_LL_BASE_ADDR+0x2e) 691 692 #define reg_rf_fsm_timeout REG_ADDR32(0x80140a2c) 693 694 #define reg_rf_coex_enable REG_ADDR8(REG_BB_LL_BASE_ADDR+0x30) 695 enum{ 696 FLD_RF_COEX_EN = BIT(0), 697 FLD_RF_COEX_WF_DN_POL = BIT(1), 698 FLD_RF_COEX_STATUS = BIT(2), 699 FLD_RF_COEX_TRX_POL = BIT(3), 700 FLD_RF_TRX_PRIO = BIT(4), 701 FLD_RF_TX_PRIO = BIT(5), 702 FLD_RF_RX_PRIO = BIT(6), 703 }; 704 #define CLEAR_ALL_RFIRQ_STATUS (reg_rf_irq_status = 0xffff) 705 #define REG_TL_MODEM_BASE_ADDR 0x140c00//140c00 706 707 #define reg_rf_modem_mode_cfg_rx1_0 REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x20) 708 enum 709 { 710 FLD_RF_LR_MODE = BIT(0), 711 FLD_RF_BT_BLE_SEL_AUTO = BIT(1), 712 FLD_RF_BT_BLE_SEL_EN_RX = BIT(2), 713 FLD_RF_CONT_MODE = BIT(3), 714 FLD_RF_NTL_CV = BIT(4), 715 FLD_RF_RX_DATA_CLK_DBG = BIT(5), 716 FLD_RF_LR_TRIG_MODE = BIT(6), 717 FLD_RF_FDC_DBG_SEL = BIT(7), 718 719 }; 720 #define reg_rf_modem_mode_ctrl_tx1_0 REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x22) 721 enum 722 { 723 FLD_RF_BLE_MODEM_TX = BIT(0), 724 }; 725 726 #define reg_rf_modem_rx_ctrl_0 REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x4c) 727 enum 728 { 729 FLD_RF_RX_ACC_LNE = BIT_RNG(0,2), 730 FLD_RF_RX_CRC_EN = BIT(3), 731 FLD_RF_SFD0_NUM = BIT_RNG(4,6), 732 }; 733 734 #define reg_rf_modem_sync_thre_ble REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x4e) 735 736 #define reg_rf_agc_rssi_lat REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x5d) 737 738 #define reg_rf_tx_tl_ctrl REG_ADDR8(REG_TL_MODEM_BASE_ADDR+0x9a) 739 enum 740 { 741 FLD_RF_TX_TP_EN = BIT(0), 742 FLD_RF_TX_IQ_EN = BIT(1), 743 FLD_RF_TX_MPSK_EN = BIT(2), 744 FLD_RF_TX_TP_ALIGN = BIT(3), 745 746 }; 747 748 #define reg_rf_mode_cfg_rx1_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x20) 749 enum 750 { 751 FLD_RF_BW_CODE = BIT_RNG(1,3), 752 FLD_RF_SC_CODE = BIT(4), 753 }; 754 755 #define reg_rf_mode_cfg_rx1_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x21) 756 enum 757 { 758 FLD_RF_MODE_VANT_RX = BIT(1), 759 FLD_RF_FE_RTRIM_RX = BIT_RNG(2,4), 760 FLD_RF_IF_FREQ = BIT_RNG(5,6), 761 762 }; 763 764 #define reg_rf_mode_cfg_tx1_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x22) 765 enum 766 { 767 FLD_RF_BLE_MODE_TX = BIT(0), 768 FLD_RF_VCO_TRIM_KVM = BIT_RNG(1,3), 769 FLD_RF_HPMC_EXP_DIFF_COUNT_L = BIT_RNG(4,7), 770 }; 771 772 #define reg_rf_mode_cfg_tx1_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x23) 773 enum 774 { 775 FLD_RF_HPMC_EXP_DIFF_COUNT_H = BIT_RNG(0,4), 776 FLD_RF_DAC_TRIM_CFBK = BIT_RNG(5,6), 777 778 }; 779 780 #define reg_rf_mode_cfg_txrx_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x26) 781 enum 782 { 783 FLD_RF_DIS_CLK_DIG_O = BIT(0), 784 FLD_RF_VANT_PULLDN = BIT(1), 785 FLD_RF_GF_BT = BIT(2), 786 FLD_RF_LDO_ANT_TRIM = BIT_RNG(3,5), 787 FLD_RF_CBPF_TYPE = BIT(6), 788 FLD_RF_TX_PA_PWR_L = BIT(7), 789 }; 790 791 792 #define reg_rf_mode_cfg_txrx_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x27) 793 794 enum 795 { 796 FLD_RF_TX_PA_PWR_H = BIT_RNG(0,4), 797 }; 798 799 #define reg_rf_burst_cfg_txrx_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x28) 800 enum 801 { 802 FLD_RF_CHNL_NUM = BIT_RNG(0,7), 803 }; 804 805 #define reg_rf_burst_cfg_txrx_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x29) 806 enum 807 { 808 FLD_RF_CH_NUMLL_SEL = BIT(0), 809 FLD_RF_TX_EN_PIF = BIT(1), 810 FLD_RF_RX_EN_PIF = BIT(2), 811 FLD_RF_RX_TIM_SRQ_SEL_TESQ = BIT(3), 812 FLD_RF_TX_TIM_SRQ_SEL_TESQ = BIT(4), 813 FLD_RF_FE_CTRIM = BIT_RNG(5,7), 814 }; 815 816 #define reg_rf_mode_cfg_tx3_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x3c) 817 enum 818 { 819 FLD_RF_MODE_CFG_TX3 = BIT_RNG(0,5), 820 FLD_RF_MODE_VANT_TX_BLE = BIT(6), 821 FLD_RF_TX_IQ_MODE_EN_BLE = BIT(7), 822 }; 823 824 825 826 #define reg_rf_mode_cfg_tx3_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x3d) 827 enum 828 { 829 FLD_RF_LDO_ANT_TRIM_BLE = BIT_RNG(0,2), 830 FLD_RF_BT_BLE_SEL_EN = BIT(3), 831 FLD_RF_TXC_PWR_SRL = BIT(4), 832 FLD_RF_BW_CODE_BLE = BIT_RNG(5,7), 833 834 }; 835 836 #define reg_rf_txrx_dbg3_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x44) 837 enum 838 { 839 FLD_RF_CHNL_FREQ_DIRECT = BIT(0), 840 FLD_RF_CHNL_FREQ_L = BIT_RNG(1,7), 841 }; 842 843 #define reg_rf_txrx_dbg3_1 REG_ADDR8(REG_TL_RADIO_BASE_ADDR+0x45) 844 enum 845 { 846 FLD_RF_CHNL_FREQ_H = BIT_RNG(0,5), 847 FLD_RF_DSN_DITHER_DISABLE = BIT(6), 848 FLD_RF_DSM_INT_MODE = BIT(7), 849 }; 850 851 #endif 852
