Home
last modified time | relevance | path

Searched refs:BM_CLR (Results 1 – 16 of 16) sorted by relevance

/hal_telink-3.7.0/tlsr9/drivers/B91/
Dgpio.c101 BM_CLR(reg_gpio_ie(pin), bit); in gpio_input_dis()
165 {BM_CLR(reg_gpio_ds(pin), bit);} in gpio_ds_dis()
257 BM_CLR(reg_gpio_pol(pin), pin & 0xff); in gpio_set_irq()
258 BM_CLR(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO); in gpio_set_irq()
262 BM_CLR(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO); in gpio_set_irq()
265 BM_CLR(reg_gpio_pol(pin), pin & 0xff); in gpio_set_irq()
291 BM_CLR(reg_gpio_pol(pin), pin & 0xff); in gpio_set_gpio2risc0_irq()
292 BM_CLR(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO2RISC0); in gpio_set_gpio2risc0_irq()
296 BM_CLR(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO2RISC0); in gpio_set_gpio2risc0_irq()
299 BM_CLR(reg_gpio_pol(pin), pin & 0xff); in gpio_set_gpio2risc0_irq()
[all …]
Dspi.h455 BM_CLR(reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN); in spi_cmd_dis()
473 BM_CLR(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT); in hspi_cmd_fmt_dis()
492 BM_CLR(reg_spi_mode2(spi_sel), FLD_HSPI_QUAD); in hspi_quad_mode_dis()
512 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_DUAL); in spi_dual_mode_dis()
532 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_3LINE); in spi_3line_mode_dis()
551 BM_CLR( reg_hspi_xip_ctrl, FLD_HSPI_ADDR_FMT); in hspi_addr_fmt_dis()
583 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_TX_DMA_EN); in spi_tx_dma_dis()
603 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_RX_DMA_EN); in spi_rx_dma_dis()
677 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_EN); in hspi_addr_dis()
705 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_MODE); in hspi_xip_seq_mode_dis()
[all …]
Dpwm.h232 BM_CLR(reg_pwm0_enable, BIT(0)); in pwm_stop()
235 BM_CLR(reg_pwm_enable, BIT(id)); in pwm_stop()
256 BM_CLR(reg_pwm_invert, BIT(id)); in pwm_invert_dis()
276 BM_CLR(reg_pwm_n_invert, BIT(id)); in pwm_n_invert_dis()
296 BM_CLR(reg_pwm_pol, BIT(id)); in pwm_set_polarity_dis()
556 BM_CLR(reg_pwm_mode32k, pwm_32K_en_chn); in pwm_32k_chn_dis()
Dgpio.h198 BM_CLR(reg_gpio_func(pin), bit); in gpio_function_dis()
224 BM_CLR(reg_gpio_out(pin), bit); in gpio_set_low_level()
294 BM_CLR(reg_gpio_oen(pin), bit); in gpio_output_en()
365 BM_CLR(reg_gpio_irq_en(pin), pin & 0xff); in gpio_irq_dis()
384 BM_CLR(reg_gpio_irq_risc0_en(pin), pin & 0xff); in gpio_gpio2risc0_irq_dis()
403 BM_CLR(reg_gpio_irq_risc1_en(pin), pin & 0xff); in gpio_gpio2risc1_irq_dis()
Dwatchdog.h47 BM_CLR(reg_tmr_ctrl2, FLD_TMR_WD_EN); in wd_stop()
Daudio.c622 BM_CLR(reg_audio_codec_dac_ctr,FLD_AUDIO_CODEC_DAC_SB); //active DAC power in audio_codec_dac_config()
627 …BM_CLR(reg_audio_codec_dac_ctr,FLD_AUDIO_CODEC_DAC_SB|FLD_AUDIO_CODEC_DAC_LEFT_ONLY);//active DAC … in audio_codec_dac_config()
630 …BM_CLR(reg_audio_codec_vic_ctr,FLD_AUDIO_CODEC_SB|FLD_AUDIO_CODEC_SB_ANALOG|FLD_AUDIO_CODEC_SLEEP_… in audio_codec_dac_config()
652 BM_CLR(reg_audio_codec_dac_ctr,FLD_AUDIO_CODEC_DAC_SOFT_MUTE); /*dac mute*/ in audio_codec_dac_config()
717 BM_CLR(reg_audio_codec_adc12_ctr,FLD_AUDIO_CODEC_ADC1_SB);/*active anc0 channel,mono .*/ in audio_codec_adc_config()
721 …BM_CLR(reg_audio_codec_adc12_ctr,FLD_AUDIO_CODEC_ADC1_SB|FLD_AUDIO_CODEC_ADC2_SB);/*active adc0 an… in audio_codec_adc_config()
723 …BM_CLR(reg_audio_codec_vic_ctr,FLD_AUDIO_CODEC_SB|FLD_AUDIO_CODEC_SB_ANALOG|FLD_AUDIO_CODEC_SLEEP_… in audio_codec_adc_config()
770 BM_CLR(reg_audio_codec_adc2_ctr,FLD_AUDIO_CODEC_ADC12_SB); in audio_codec_adc_config()
776 BM_CLR(reg_audio_codec_adc12_ctr,FLD_AUDIO_CODEC_ADC12_SOFT_MUTE);/*adc unmute*/ in audio_codec_adc_config()
1141 BM_CLR(reg_audio_codec_dac_ctr,FLD_AUDIO_CODEC_DAC_SOFT_MUTE);//dac unmute in audio_resume_out_path()
[all …]
Dusbhw.c44 BM_CLR(reg_ctrl_ep_irq_mode, m); in usbhw_enable_manual_interrupt()
Dpke.h185 BM_CLR(reg_pke_conf, mask); in pke_clr_irq_mask()
237 BM_CLR(reg_pke_conf, FLD_PKE_CONF_PARTIAL_RADIX); in pke_set_operand_width()
239 BM_CLR(reg_pke_conf, FLD_PKE_CONF_BASE_RADIX); in pke_set_operand_width()
Dswire.h83 BM_CLR(reg_swire_id, FLD_SWIRE_FIFO_MODE); in swire_fifo_mode_dis()
Ddma.h155 BM_CLR(reg_dma_ctrl(chn),BIT_RNG(4,31)); in dma_config()
177 BM_CLR(reg_dma_ctr0(chn),BIT(0)); in dma_chn_dis()
Daudio.h441 BM_CLR(reg_dmic_clk_set,BIT(0));//set dmic_div in audio_set_codec_clk()
462 BM_CLR(reg_i2s_step,FLD_I2S_CLK_EN); in audio_i2s_clk_dis()
482 BM_CLR(reg_dmic_step,FLD_DMIC_SEL); in audio_codec_clk_dis()
650 BM_CLR(reg_i2s_cfg,FLD_AUDIO_I2S_LRSWAP); in audio_invert_data_dis()
Dpwm.c60 BM_CLR(reg_gpio_pad_mul_sel, BIT(3)); in pwm_set_pin()
Dpm.c460 BM_CLR(reg_system_irq_mask,BIT(0)); in pm_sleep_wakeup()
462 BM_CLR(reg_system_ctrl,FLD_SYSTEM_32K_TRACK_EN);//disable 32k track in pm_sleep_wakeup()
468 BM_CLR(reg_system_irq_mask,BIT(0)); in pm_sleep_wakeup()
469 …BM_CLR(reg_system_ctrl,FLD_SYSTEM_TIMER_EN | FLD_SYSTEM_TIMER_AUTO | FLD_SYSTEM_32K_TRACK_EN);//di… in pm_sleep_wakeup()
Dusbhw.h91 BM_CLR(reg_ctrl_ep_irq_sta, ep); in usbhw_clr_ctrl_ep_irq()
Drf.h301 BM_CLR(reg_rf_irq_mask,mask); in rf_clr_irq_mask()
/hal_telink-3.7.0/tlsr9/common/
Dbit.h40 #define BM_CLR(x, mask) ( (x) &= ~(mask) ) macro