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Searched refs:BIT_RNG (Results 1 – 23 of 23) sorted by relevance

/hal_telink-3.7.0/tlsr9/drivers/B91/reg_include/
Dadc_reg.h39 FLD_ADC_VREF_CHN_M = BIT_RNG(0,1),
43 FLD_ADC_AIN_NEGATIVE = BIT_RNG(0,3),
44 FLD_ADC_AIN_POSITIVE = BIT_RNG(4,7),
48 FLD_ADC_RES_M = BIT_RNG(0,1),
53 FLD_ADC_TSAMPLE_CYCLE_CHN_M = BIT_RNG(0,3),
57 FLD_R_MAX_MC0 = BIT_RNG(0,7),//0xef<7:0> r_max_mc[7:0]
61 FLD_R_MAX_S = BIT_RNG(0,3),//0xf1<3:0> r_max_s
62 FLD_R_MAX_MC1 = BIT_RNG(6,7),//0xf1<7:6> r_max_mc[9:8]
67 FLD_ADC_MAX_SCNT = BIT_RNG(4,5),
75 FLD_ADC_SAMPLE_CLK_DIV = BIT_RNG(0,2),
[all …]
Drf_reg.h79 FLD_RF_TX_FMT = BIT_RNG(2,3),
90 FLD_RF_RESERVED0 = BIT_RNG(1,2),
92 FLD_RF_RESERVED1 = BIT_RNG(4,5),
99 FLD_RF_PREAMBLE_LEN = BIT_RNG(0,4),
100 FLD_RF_TRAILER_LEN = BIT_RNG(5,7),
119 FLD_RF_HEAD_MODE = BIT_RNG(0,1),
120 FLD_RF_CRC_MODE = BIT_RNG(2,3),
131 FLD_RF_ACC_LEN = BIT_RNG(0,2),
157 FLD_RF_PN_INIT = BIT_RNG(0,5),
182 FLD_RF_R_PILOT_LEN_O = BIT_RNG(0,3),
[all …]
Ddma_reg.h41 #define FLD_DMA_CHANNEL_NUM = BIT_RNG(0,3),
42 #define FLD_DMA_FIFO_DEPTH = BIT_RNG(4,9),
43 #define FLD_DMA_REQ_NUM = BIT_RNG(10,14),
54 FLD_DMA_CHANNEL_DST_REQ_SEL = BIT_RNG(4,8),
55 FLD_DMA_CHANNEL_SRC_REQ_SEL = BIT_RNG(9,13),
56 FLD_DMA_CHANNEL_DST_ADDR_CTRL = BIT_RNG(14,15),
57 FLD_DMA_CHANNEL_SRC_ADDR_CTRL = BIT_RNG(16,17),
60 FLD_DMA_CHANNEL_DST_WIDTH = BIT_RNG(20,21),
61 FLD_DMA_CHANNEL_SRC_WIDTH = BIT_RNG(22,23),
89 FLD_DMA_SRC_BURST_SIZE = BIT_RNG(0,2),
[all …]
Dmspi_reg.h38 FLD_MSPI_DATA_LINE = BIT_RNG(2,3),
49 FLD_MSPI_TIMEOUT_CNT = BIT_RNG(0,2),
50 FLD_MSPI_CS2SCL_CNT = BIT_RNG(3,4),
51 FLD_MSPI_CS2CS_CNT = BIT_RNG(5,7),
57 …FLD_MSPI_MULTIBOOT_ADDR_OFFSET = BIT_RNG(0,2),/**<mutiboot address offset option, 0:0k; 1:128k; …
62 FLD_MSPI_PROGRAM_SPACE_SIZE = BIT_RNG(0,6),/**< program space size = mspi_set_h*4k*/
67 FLD_MSPI_RD_CMD = BIT_RNG(0,7), /**< xip read command */
72 FLD_MSPI_DUMMY = BIT_RNG(0,3),/**< dummy cycle = FLD_MSPI_DUMMY + 1 */
73 FLD_MSPI_DAT_LINE = BIT_RNG(4,5),/**< 0:single line; 1: dual line; 2:quad line; 3:quad line */
Duart_reg.h43 FLD_UART_CLK_DIV = BIT_RNG(0,14),
50 FLD_UART_BPWC_O = BIT_RNG(0,3),
62 FLD_UART_STOP_SEL = BIT_RNG(4,5),
71 FLD_UART_RTS_TRIQ_LEV = BIT_RNG(0,3),
81 FLD_UART_RX_IRQ_TRIQ_LEV = BIT_RNG(0,3),
82 FLD_UART_TX_IRQ_TRIQ_LEV = BIT_RNG(4,7),
88 FLD_UART_TIMEOUT_BW = BIT_RNG(0,7),
94 FLD_UART_TIMEOUT_MUL = BIT_RNG(0,1),
106 FLD_UART_RX_BUF_CNT = BIT_RNG(0,3),
107 FLD_UART_TX_BUF_CNT = BIT_RNG(4,7),
[all …]
Di2c_reg.h56 FLD_I2C_ID = BIT_RNG(1,7),
73 FLD_I2C_MST_P = BIT_RNG(3,5),
74 FLD_I2C_SS = BIT_RNG(6,7),
139 FLD_I2C_RX_IRQ_TRIG_LEV = BIT_RNG(0,3),
140 FLD_I2C_TX_IRQ_TRIG_LEV = BIT_RNG(4,7),
172 FLD_I2C_BUF0 = BIT_RNG(0,7),
182 FLD_I2C_BUF1 = BIT_RNG(0,7),
192 FLD_I2C_BUF2 = BIT_RNG(0,7),
202 FLD_I2C_BUF3 = BIT_RNG(0,7),
213 FLD_I2C_RX_BUFCNT = BIT_RNG(0,3),
[all …]
Daudio_reg.h47 FLD_AUDIO_I2S_FORMAT = BIT_RNG(0,1),
48 FLD_AUDIO_I2S_WL = BIT_RNG(2,3),
64 FLD_AUDIO_I2S_CMODE = BIT_RNG(0,1),
72 FLD_AUDIO_I2S_I2S_AIN0_COME = BIT_RNG(0,1),
73 FLD_AUDIO_I2S_I2S_AIN1_COME = BIT_RNG(2,3),
74 FLD_AUDIO_I2S_I2S_AOUT_COME = BIT_RNG(4,6),
81 FLD_AUDIO_AIN0_SEL = BIT_RNG(0,1),
82 FLD_AUDIO_AOUT0_SEL = BIT_RNG(2,3),
83 FLD_AUDIO_AIN1_SEL = BIT_RNG(4,5),
84 FLD_AUDIO_AOUT1_SEL = BIT_RNG(6,7),
[all …]
Dspi_reg.h58 FLD_SPI_CS2SCLK = BIT_RNG(0,1),
62 FLD_SPI_MODE_WORK_MODE = BIT_RNG(5,6),
87 FLD_SPI_CSHT =BIT_RNG(4,7),
144 FLD_SPI_DUMMY_CNT = BIT_RNG(0,3),
145 FLD_SPI_TRANSMODE =BIT_RNG(4,7),
227 FLD_SPI_RXF_NUM = BIT_RNG(0,3),
228 FLD_SPI_TXF_NUM = BIT_RNG(4,7),
242 FLD_SPI_FIFO_STA_RESERVED = BIT_RNG(0,1),
262 FLD_SPI_STATE_RESERVED =BIT_RNG(0,1),
281 FLD_HSPI_HSPI_STATUS_RESERVED =BIT_RNG(2,3),
[all …]
Dpke_reg.h46 FLD_PKE_CONF_PARTIAL_RADIX = BIT_RNG(16,23),
47 FLD_PKE_CONF_BASE_RADIX = BIT_RNG(24,26),
59 FLD_PKE_RT_CODE_STOP_LOG = BIT_RNG(0,3),
70 FLD_PKE_EXE_CONF_ME_SCA_EN = BIT_RNG(8,9),
Dmdec_reg.h40 FLD_CLS_MDEC = BIT_RNG(0,4),
41 FLD_RSVD = BIT_RNG(5,6),
Dsoc.h135 FLD_CLK_SCLK_DIV = BIT_RNG(0,3),
136 FLD_CLK_SCLK_SEL = BIT_RNG(4,6),
142 FLD_CLK_MSPI_DIV = BIT_RNG(4,7),
147 FLD_I2S_STEP = BIT_RNG(0,6),
156 FLD_DMIC_STEP = BIT_RNG(0,6),
180 FLD_MDEC_RSVD = BIT_RNG(5,7),
Dswire_reg.h53 FLD_SWIRE_CLK_DIV = BIT_RNG(0,6),
58 FLD_SWIRE_ID_VALID = BIT_RNG(0,4),
Dtimer_reg.h36 FLD_TMR0_MODE = BIT_RNG(0,1),
39 FLD_TMR1_MODE = BIT_RNG(4,5),
Dpwm_reg.h162 #define FLD_PWM_CMP = BIT_RNG(0,15),
163 #define FLD_PWM_MAX = BIT_RNG(16,31),
277 FLD_PWM0_FIFO_NUM_OF_TRIGGLE_LEVEL = BIT_RNG(0,3),
289 FLD_PWM0_IR_FIFO_DATA_NUM = BIT_RNG(0,3),
Dstimer_reg.h39 FLD_SYSTEM_IRQ_MASK = BIT_RNG(0,2),
56 FLD_SYSTEM_32K_CAL_MODE = BIT_RNG(4,7),
Dusb_reg.h44 FLD_CTRL_EP_IRQ_TRANS = BIT_RNG(0,3),
/hal_telink-3.7.0/tlsr9/drivers/B91/
Dusbhw.h421 reg_gpio_func_mux(GPIO_PA5)=reg_gpio_func_mux(GPIO_PA5)&(~BIT_RNG(2,3)); in usb_set_pin_en()
423 reg_gpio_func_mux(GPIO_PA6)=reg_gpio_func_mux(GPIO_PA6)&(~BIT_RNG(4,5)); in usb_set_pin_en()
Ddma.h155 BM_CLR(reg_dma_ctrl(chn),BIT_RNG(4,31)); in dma_config()
188 reg_dma_ctr0(chn) = (reg_dma_ctr0(chn) | BIT_RNG(1,3)) & (~(mask)); in dma_set_irq_mask()
Daudio.c262 unsigned char mask =(unsigned char) ~BIT_RNG(start_bit , start_bit+1); in audio_i2s_set_pin_mux()
349 reg_gpio_pb_fuc_h=reg_gpio_pb_fuc_h&(~BIT_RNG(0,1)); in audio_set_dmic_pin()
350 reg_gpio_pb_fuc_l=(reg_gpio_pb_fuc_l&(~BIT_RNG(4,7))); in audio_set_dmic_pin()
356 reg_gpio_pc_fuc_l=(reg_gpio_pc_fuc_l&(~BIT_RNG(2,7)))|((2<<2)|(2<<4)|(2<<6)); in audio_set_dmic_pin()
362 reg_gpio_pd_fuc_h=(reg_gpio_pd_fuc_h&(~BIT_RNG(0,5)))|((1<<0)|(1<<2)|(1<<4)); in audio_set_dmic_pin()
368 reg_gpio_pb_fuc_l=(reg_gpio_pb_fuc_l&(~BIT_RNG(4,7))); in audio_set_dmic_pin()
374 reg_gpio_pc_fuc_l=(reg_gpio_pc_fuc_l&(~BIT_RNG(2,5)))|((2<<2)|(2<<4)); in audio_set_dmic_pin()
379 reg_gpio_pd_fuc_h=(reg_gpio_pd_fuc_h&(~BIT_RNG(0,3)))|((1<<0)|(1<<2)); in audio_set_dmic_pin()
Dpwm.c56 unsigned char mask =(unsigned char) ~BIT_RNG(start_bit , start_bit+1); in pwm_set_pin()
Ds7816.c136 reg_gpio_func_mux(clk_pin)=(reg_gpio_func_mux(clk_pin)&(~BIT_RNG(0,1)))|BIT(0); in s7816_set_pin()
Dspi.c110 unsigned char mask = (unsigned char)~BIT_RNG(start_bit, start_bit + 1); in hspi_set_pin_mux()
165 unsigned char mask = (unsigned char)~BIT_RNG(start_bit, start_bit + 1); in pspi_set_pin_mux()
/hal_telink-3.7.0/tlsr9/common/
Dbit.h34 #define BIT_RNG(s, e) (BIT_MASK_LEN((e)-(s)+1) << (s)) macro