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/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/drivers/B91/ext_driver/
Dext_gpio.h44 static inline unsigned int gpio_read_cache(gpio_pin_e pin, unsigned char *p) in gpio_read_cache() argument
46 return p[pin>>8] & (pin & 0xff); in gpio_read_cache()
54 static inline void gpio_read_all(unsigned char *p) in gpio_read_all() argument
56 p[0] = REG_ADDR8(0x140300); in gpio_read_all()
57 p[1] = REG_ADDR8(0x140308); in gpio_read_all()
58 p[2] = REG_ADDR8(0x140310); in gpio_read_all()
59 p[3] = REG_ADDR8(0x140318); in gpio_read_all()
60 p[4] = REG_ADDR8(0x140320); in gpio_read_all()
Dext_rf.h30 #define DMA_RFRX_OFFSET_CRC24(p) (p[DMA_RFRX_OFFSET_RFLEN]+6) //data len:3 argument
31 #define DMA_RFRX_OFFSET_TIME_STAMP(p) (p[DMA_RFRX_OFFSET_RFLEN]+9) //data len:4 argument
32 #define DMA_RFRX_OFFSET_FREQ_OFFSET(p) (p[DMA_RFRX_OFFSET_RFLEN]+13) //data len:2 argument
33 #define DMA_RFRX_OFFSET_RSSI(p) (p[DMA_RFRX_OFFSET_RFLEN]+15) //data len:1, signed argument
35 #define RF_BLE_RF_PAYLOAD_LENGTH_OK(p) (p[5] <= reg_rf_rxtmaxlen) argument
36 #define RF_BLE_RF_PACKET_CRC_OK(p) ((p[p[5]+5+11] & 0x01) == 0x0) argument
37 #define RF_BLE_PACKET_VALIDITY_CHECK(p) (RF_BLE_RF_PAYLOAD_LENGTH_OK(p) && RF_BLE_RF_PACKET_CRC… argument
98 static inline void rf_set_ble_access_code (unsigned char *p) in rf_set_ble_access_code() argument
100 write_reg32 (0x80140808, p[3] | (p[2]<<8) | (p[1]<<16) | (p[0]<<24)); in rf_set_ble_access_code()
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/drivers/B91/
Drf.h53 #define rf_ble_dma_rx_offset_crc24(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN]+6) //data len:3 argument
54 #define rf_ble_dma_rx_offset_time_stamp(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN]+9) //data len:4 argument
55 #define rf_ble_dma_rx_offset_freq_offset(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN]+13) //data len:2 argument
56 #define rf_ble_dma_rx_offset_rssi(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN]+15) //data len:1, signed argument
57 #define rf_ble_packet_length_ok(p) (p[5] <= reg_rf_rxtmaxlen) //dma_len must 4 byte alig… argument
58 #define rf_ble_packet_crc_ok(p) ((p[(p[5]+5 + 11)] & 0x01) == 0x0) argument
77 #define rf_pri_esb_dma_rx_offset_crc(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN]+5) //data len:2 argument
78 #define rf_pri_esb_dma_rx_offset_time_stamp(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN]+7) //data l… argument
79 #define rf_pri_esb_dma_rx_offset_freq_offset(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN]+11) //data … argument
80 #define rf_pri_esb_dma_rx_offset_rssi(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN]+13) //data len:1,… argument
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Dpke.c769 unsigned int *a_high, *a_low, *p; in pke_mod() local
789 p = (unsigned int *)reg_pke_a_ram(1); in pke_mod()
796 memcpy(p, a+bWordLen-1, tmpLen<<2); in pke_mod()
797 div2n_u32(p, tmpLen, bitLen); in pke_mod()
800 memset(p+tmpLen, 0, (bWordLen-tmpLen)<<2); in pke_mod()
803 if(big_integer_compare(p, bWordLen, b, bWordLen) >= 0) in pke_mod()
805 sub_u32(p, b, a_high, bWordLen); in pke_mod()
809 memcpy(a_high, p, bWordLen<<2); in pke_mod()
840 memset(p, 0, bWordLen<<2); in pke_mod()
843 p[bWordLen-1] = 1<<(bitLen); in pke_mod()
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Dgpio.h263 static inline void gpio_get_level_all(unsigned char *p) in gpio_get_level_all() argument
265 p[0] = reg_gpio_pa_in; in gpio_get_level_all()
266 p[1] = reg_gpio_pb_in; in gpio_get_level_all()
267 p[2] = reg_gpio_pc_in; in gpio_get_level_all()
268 p[3] = reg_gpio_pd_in; in gpio_get_level_all()
269 p[4] = reg_gpio_pe_in; in gpio_get_level_all()
Demi.h138 void rf_phy_test_prbs9 (unsigned char *p, int n);
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/ble/vendor/controller/
Db91_bt.c36 #define BYTES_TO_UINT16(n, p) {n = ((u16)(p)[0] + ((u16)(p)[1]<<8));} argument
37 #define BSTREAM_TO_UINT16(n, p) {BYTES_TO_UINT16(n, p); p += 2;} argument
74 u8 *p = bltHci_txfifo.p + (bltHci_txfifo.rptr & bltHci_txfifo.mask) * bltHci_txfifo.size; in b91_bt_hci_tx_handler() local
75 if(p) in b91_bt_hci_tx_handler()
78 BSTREAM_TO_UINT16(len, p); in b91_bt_hci_tx_handler()
84 b91_ctrl.callbacks.host_read_packet(p, len); in b91_bt_hci_tx_handler()
109 u8 *p = bltHci_rxfifo.p + (bltHci_rxfifo.rptr & bltHci_rxfifo.mask) * bltHci_rxfifo.size; in b91_bt_hci_rx_handler() local
110 if(p) in b91_bt_hci_rx_handler()
113 blc_hci_handler(&p[0], 0); in b91_bt_hci_rx_handler()
182 u8 *p = bltHci_rxfifo.p + (bltHci_rxfifo.wptr & bltHci_rxfifo.mask) * bltHci_rxfifo.size; in b91_bt_host_send_packet() local
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/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/ble/common/
Dutility.c25 void swapN(unsigned char *p, int n) in swapN() argument
30 c = p[i]; in swapN()
31 p[i] = p[n - 1 - i]; in swapN()
32 p[n - 1 - i] = c; in swapN()
86 void my_fifo_init (my_fifo_t *f, int s, u8 n, u8 *p) in my_fifo_init() argument
92 f->p = p; in my_fifo_init()
99 return f->p + (f->wptr & (f->num-1)) * f->size; in my_fifo_wptr()
108 return f->p + (f->wptr & (f->num-1)) * f->size; in my_fifo_wptr_v2()
118 int my_fifo_push (my_fifo_t *f, u8 *p, int n) in my_fifo_push() argument
129 u8 *pd = f->p + (f->wptr++ & (f->num-1)) * f->size; in my_fifo_push()
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Dutility.h118 void swapN (unsigned char *p, int n);
166 u8* p; member
169 void my_fifo_init (my_fifo_t *f, int s, u8 n, u8 *p);
173 int my_fifo_push (my_fifo_t *f, u8 *p, int n);
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/ble/stack/ble/hci/
Dhci.h64 u8* p; member
119 typedef int (*hci_data_handler_t) (u16 conn, u8 * p);
188 int blc_hci_handler (u8 *p, int n);
264 int blc_hci_sendACLData2Host (u16 handle, u8 *p);
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/common/
Dfifo.h35 unsigned char* p; member
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/ble/stack/ble/controller/ll/
Dll.h26 typedef void (*blt_event_callback_t)(u8 e, u8 *p, int n);
60 void blc_ll_registerTelinkControllerEventCallback (u8 e, blt_event_callback_t p);