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/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/drivers/B91/reg_include/
Duart_reg.h33 #define reg_uart_data_buf_adr(i) (0x140080+(i)*0x40) //uart(i) argument
35 #define reg_uart_data_buf(i,j) REG_ADDR8(reg_uart_data_buf_adr(i)+(j)) //uart(i)_buf(j) argument
36 #define reg_uart_data_hword_buf(i,j) REG_ADDR16(reg_uart_data_buf_adr(i)+(j)*2) argument
38 #define reg_uart_data_word_buf(i) REG_ADDR32(reg_uart_data_buf_adr(i)) //uart(i) argument
40 #define reg_uart_clk_div(i) REG_ADDR16(0x140084+(i)*0x40) argument
47 #define reg_uart_ctrl0(i) REG_ADDR8(0x140086+(i)*0x40) argument
55 #define reg_uart_ctrl1(i) REG_ADDR8(0x140087+(i)*0x40) argument
68 #define reg_uart_ctrl2(i) REG_ADDR16(0x140088+(i)*0x40) argument
78 #define reg_uart_ctrl3(i) REG_ADDR8(0x140089+(i)*0x40) argument
85 #define reg_uart_rx_timeout0(i) REG_ADDR8(0x14008a+(i)*0x40) argument
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Dspi_reg.h42 #define reg_spi_data_buf_adr(i) 0x140048+(i)*BASE_ADDR_DIFF argument
56 #define reg_spi_mode0(i) REG_ADDR8(PSPI_BASE_ADDR+(i)*BASE_ADDR_DIFF) argument
71 #define reg_spi_mode1(i) REG_ADDR8(PSPI_BASE_ADDR+0x01+(i)*BASE_ADDR_DIFF) argument
79 #define reg_spi_mode2(i) REG_ADDR8(PSPI_BASE_ADDR+0x02+(i)*BASE_ADDR_DIFF) argument
93 #define reg_spi_tx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x03+(i)*BASE_ADDR_DIFF) argument
99 #define reg_spi_tx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x12+(i)*(BASE_ADDR_DIFF-0x12+0x20)) argument
105 #define reg_spi_tx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x13+(i)*(BASE_ADDR_DIFF-0x13+0x21)) argument
110 #define reg_spi_rx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x04+(i)*BASE_ADDR_DIFF) argument
116 #define reg_spi_rx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x10+(i)*(BASE_ADDR_DIFF-0x10+0x1e)) argument
121 #define reg_spi_rx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x11+(i)*(BASE_ADDR_DIFF-0x11+0x1f)) argument
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Ddma_reg.h47 #define reg_dma_ctrl(i) REG_ADDR32(( 0x00100444 +(i)*0x14)) argument
64 #define reg_dma_ctr0(i) REG_ADDR8(( 0x00100444 +(i)*0x14)) argument
86 #define reg_dma_ctr3(i) REG_ADDR8((0x00100447 +(i)*0x14)) argument
98 #define reg_dma_src_addr(i) REG_ADDR32 (( 0x00100448 +(i)*0x14)) argument
99 #define reg_dma_dst_addr(i) REG_ADDR32 (( 0x0010044c +(i)*0x14)) argument
100 #define reg_dma_size(i) REG_ADDR32 (( 0x00100450 +(i)*0x14)) argument
110 #define reg_dma_cr3_size(i) (*(volatile unsigned long*) ( 0x00100452 +(i)*0x14)) argument
116 #define reg_dma_llp(i) REG_ADDR32 (( 0x00100454 +(i)*0x14)) argument
Dgpio_reg.h133 #define reg_gpio_in(i) REG_ADDR8(0x140300+((i>>8)<<3)) argument
134 #define reg_gpio_ie(i) REG_ADDR8(0x140301+((i>>8)<<3)) argument
135 #define reg_gpio_oen(i) REG_ADDR8(0x140302+((i>>8)<<3)) argument
136 #define reg_gpio_out(i) REG_ADDR8(0x140303+((i>>8)<<3)) argument
137 #define reg_gpio_pol(i) REG_ADDR8(0x140304+((i>>8)<<3)) argument
138 #define reg_gpio_ds(i) REG_ADDR8(0x140305+((i>>8)<<3)) argument
141 #define reg_gpio_func(i) REG_ADDR8(0x140306+((i>>8)<<3)) argument
142 #define reg_gpio_irq_en(i) REG_ADDR8(0x140307+((i>>8)<<3)) // reg_irq_mask: FLD_IRQ_GPIO_EN argument
143 #define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x140338 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_R… argument
144 #define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x140340 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_R… argument
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Dplic_reg.h35 #define reg_irq_pending(i) (*(volatile unsigned long*)(0 + (0xe4001000+((i>31) ? 4 : 0)))) argument
40 #define reg_irq_src(i) (*(volatile unsigned long*)(0 + (0xe4002000+((i>31) ? 4 : 0) )… argument
45 #define reg_irq_src_priority(i) (*(volatile unsigned long*)(0 + 0xe4000000+((i)<<2))) argument
Dpwm_reg.h149 #define reg_pwm_cmp(i) REG_ADDR16(REG_PWM_BASE+0x14 +(i << 2)) argument
156 #define reg_pwm_cycle(i) REG_ADDR32(REG_PWM_BASE+0x14 + (i << 2)) argument
168 #define reg_pwm_max(i) REG_ADDR16(REG_PWM_BASE+0x16 + (i << 2)) argument
216 #define reg_pwm_irq_mask(i) REG_ADDR8(REG_PWM_BASE+0x30+i*2) argument
232 #define reg_pwm_irq_sta(i) REG_ADDR8(REG_PWM_BASE+0x31+i*2) argument
238 #define reg_pwm_cnt(i) REG_ADDR16(REG_PWM_BASE+0x34 +(i << 1)) argument
268 #define reg_pwm_ir_fifo_dat(i) REG_ADDR16(REG_PWM_BASE+0x48+i*2) argument
Dtimer_reg.h61 #define reg_tmr_capt(i) REG_ADDR32(0x140144 + ((i) << 2)) argument
72 #define reg_tmr_tick(i) REG_ADDR32(0X140150 + ((i) << 2)) argument
Dusb_reg.h119 #define reg_usb_ep_ptr(i) REG_ADDR8(0x100810+((i) & 0x07)) argument
131 #define reg_usb_ep_dat(i) REG_ADDR8(0x100818+((i) & 0x07)) argument
141 #define reg_usb_ep_ctrl(i) REG_ADDR8(0x100820+((i) & 0x07)) argument
162 #define reg_usb_ep_buf_addr(i) REG_ADDR8(0x100828+((i) & 0x07)) argument
Di2c_reg.h165 #define reg_i2c_data_buf(i) REG_ADDR8(( REG_I2C_BASE+0x08 +(i) )) argument
Daudio_reg.h34 #define reg_fifo_buf_adr(i) REG_AUDIO_AHB_BASE+(i)*0x40 argument
Drf_reg.h60 #define reg_rf_dma_tx_rptr(i) REG_ADDR8(0x00100501 + (i << 1)) argument
61 #define reg_rf_dma_tx_wptr(i) REG_ADDR8(0x00100500 + (i << 1)) argument
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/drivers/B91/
Daes.c76 for (unsigned char i = 0; i < 4; i++) { in aes_set_key_data() local
77 temp = key[16-(4*i)-4]<<24 | key[16-(4*i)-3]<<16 | key[16-(4*i)-2]<<8 | key[16-(4*i)-1]; in aes_set_key_data()
78 reg_aes_key(i) = temp; in aes_set_key_data()
79 temp = data[16-(4*i)-4]<<24 | data[16-(4*i)-3]<<16 | data[16-(4*i)-2]<<8 | data[16-(4*i)-1]; in aes_set_key_data()
80 aes_data_buff[i] = temp; in aes_set_key_data()
95 for (unsigned char i=0; i<16; i++) { in aes_get_result() local
96 result[i] = ptr[15 - i]; in aes_get_result()
Dpke.c38 unsigned int i = 0; in valid_bits_get() local
46 for (i = wordLen; i > 0; i--) in valid_bits_get()
48 if (a[i - 1]) in valid_bits_get()
54 if(0 == i) in valid_bits_get()
61 if (a[i - 1] & (0x1 << (j - 1))) in valid_bits_get()
67 return ((i - 1) << 5) + j; in valid_bits_get()
78 unsigned int i = 0; in valid_words_get() local
80 for (i = max_words; i > 0; i--) in valid_words_get()
82 if (a[i - 1]) in valid_words_get()
84 return i; in valid_words_get()
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Dusbhw.c57 for(int i = 0; i < (len); ++i){ in usbhw_write_ep() local
58 reg_usb_ep_dat(ep) = data[i]; in usbhw_write_ep()
Dspi.c501 for (unsigned int i = 0; i < len; i++) in spi_write() local
504 reg_spi_wr_rd_data(spi_sel, i % REG_SPI_WR_RD_SIZE) = data[i]; in spi_write()
518 for (unsigned int i = 0; i < len; i++) in spi_read() local
521 data[i] = reg_spi_wr_rd_data(spi_sel, i % REG_SPI_WR_RD_SIZE); in spi_read()
587 for(int i=0; i<len; i=i+chunk_size) in spi_master_write_read_loopback() local
590 if(chunk_size > (len-i)) in spi_master_write_read_loopback()
592 chunk_size = len-i; in spi_master_write_read_loopback()
596 spi_write(spi_sel, write_data + i, chunk_size); in spi_master_write_read_loopback()
604 else if(i==0) in spi_master_write_read_loopback()
609 else if((len-i) > REG_SPI_WR_RD_SIZE) in spi_master_write_read_loopback()
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Dflash.c114 int i; in flash_wait_done() local
115 for(i = 0; i < 10000000; ++i){ in flash_wait_done()
170 unsigned int i; in flash_write_page_ram() local
171 for(i = 0; i < len; ++i){ in flash_write_page_ram()
172 mspi_write(buf[i]); /* write data */ in flash_write_page_ram()
216 for(unsigned int i = 0; i < len; ++i){ in flash_read_page_ram() local
632 int i,f_cnt=0; in flash_read_mid_uid_with_check() local
645 for(i=0;i<16;i++){ in flash_read_mid_uid_with_check()
646 if(flash_uid[i]==no_uid[i]){ in flash_read_mid_uid_with_check()
Duart.c199 unsigned char i = 0, j= 0; in uart_cal_div_and_bwpc() local
220 for(i=3;i<=15;i++){ in uart_cal_div_and_bwpc()
221 D_intdec[i-3] = (10*primeInt)/(i+1);////get the LSB in uart_cal_div_and_bwpc()
222 D_dec[i-3] = D_intdec[i-3] - 10*(D_intdec[i-3]/10);///get the decimal section in uart_cal_div_and_bwpc()
223 D_int[i-3] = D_intdec[i-3]/10;///get the integer section in uart_cal_div_and_bwpc()
525 for(unsigned char i=0;i<len;i++) in uart_send() local
527 uart_send_byte(uart_num,addr[i]); in uart_send()
684 unsigned int i = 5; in uart_is_prime() local
692 for(i=5;i*i<n;i+=6){ in uart_is_prime()
693 if((n % i == 0)||(n %(i+2))==0){ in uart_is_prime()
Dadc.c315 for(int i=0;i<sample_num;i++) in adc_get_code_dma() local
317 if(sample_buffer[i] & BIT(13)) in adc_get_code_dma()
319 sample_buffer[i] = 0; in adc_get_code_dma()
323 sample_buffer[i] = (sample_buffer[i] & 0x1fff); //BIT(12..0) is valid adc code in adc_get_code_dma()
Dpm.c189 for(volatile unsigned char i = 0; i < 30; i++){ //20us in pm_wait_bbpll_done() local
275 for(volatile unsigned int i = 0; i < 64; i++){ in pm_sleep_start() local
294 for(volatile unsigned int i = 0; i < 300; i++){ //200us in pm_sleep_start() local
Dclock.c101 for(unsigned char i = 0; i< xtal_times; i++) in clock_kick_32k_xtal() local
Daudio.c1079 for (unsigned char i=0;i<9;i++) in audio_set_ext_codec() local
1081 i2c_master_write(0x34,&LineIn_To_I2S_CMD_TAB[i][0],2); in audio_set_ext_codec()
/hal_telink-3.6.0-3.5.0-3.4.0/tlsr9/ble/common/
Dutility.c27 int i, c; in swapN() local
28 for (i=0; i<n/2; i++) in swapN()
30 c = p[i]; in swapN()
31 p[i] = p[n - 1 - i]; in swapN()
32 p[n - 1 - i] = c; in swapN()
38 int i; in swapX() local
39 for (i = 0; i < len; i++) in swapX()
40 dst[len - 1 - i] = src[i]; in swapX()
Dutility.h23 #define cat2(i,j) i##j argument
24 #define cat3(i,j,k) i##j##k argument
100 #define foreach(i, n) for(int i = 0; i < (n); ++i) argument
101 #define foreach_range(i, s, e) for(int i = (s); i < (e); ++i) argument
102 #define foreach_arr(i, arr) for(int i = 0; i < ARRAY_SIZE(arr); ++i) argument
106 #define everyN(i, n) ++(i); (i)=((i) < N ? (i) : 0); if(0 == (i)) argument