1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 /******************************************************************************************************** 20 * @file soc.h 21 * 22 * @brief This is the header file for B91 23 * 24 * @author Driver Group 25 * 26 *******************************************************************************************************/ 27 #pragma once 28 29 #include "../sys.h" 30 31 #define LM_BASE 0x80000000 32 33 #define ILM_BASE (LM_BASE + 0x40000000) 34 #define DLM_BASE (LM_BASE + 0x40200000) 35 #define CPU_ILM_BASE (0x00000000) 36 #define CPU_DLM_BASE (0x00080000) 37 38 #define SC_BASE_ADDR 0x1401c0 39 /******************************* reset registers: 1401e0 ******************************/ 40 #define reg_rst REG_ADDR32(0x1401e0) 41 42 #define reg_rst0 REG_ADDR8(0x1401e0) 43 enum{ 44 FLD_RST0_HSPI = BIT(0), 45 FLD_RST0_I2C = BIT(1), 46 FLD_RST0_UART0 = BIT(2), 47 FLD_RST0_USB = BIT(3), 48 FLD_RST0_PWM = BIT(4), 49 //RSVD 50 FLD_RST0_UART1 = BIT(6), 51 FLD_RST0_SWIRE = BIT(7), 52 }; 53 54 55 #define reg_rst1 REG_ADDR8(0x1401e1) 56 enum{ 57 //RSVD 58 FLD_RST1_SYS_STIMER = BIT(1), 59 FLD_RST1_DMA = BIT(2), 60 FLD_RST1_ALGM = BIT(3), 61 FLD_RST1_PKE = BIT(4), 62 //RSVD 63 FLD_RST1_PSPI = BIT(6), 64 FLD_RST1_SPISLV = BIT(7), 65 }; 66 67 #define reg_rst2 REG_ADDR8(0x1401e2) 68 enum{ 69 FLD_RST2_TIMER = BIT(0), 70 FLD_RST2_AUD = BIT(1), 71 FLD_RST2_TRNG = BIT(2), 72 //RSVD 73 FLD_RST2_MCU = BIT(4), 74 FLD_RST2_LM = BIT(5), 75 FLD_RST2_NPE = BIT(6), 76 //RSVD 77 }; 78 79 #define reg_rst3 REG_ADDR8(0x1401e3) 80 enum{ 81 FLD_RST3_ZB = BIT(0), 82 FLD_RST3_MSTCLK = BIT(1), 83 FLD_RST3_LPCLK = BIT(2), 84 FLD_RST3_ZB_CRYPT = BIT(3), 85 FLD_RST3_MSPI = BIT(4), 86 FLD_RST3_CODEC = BIT(5), 87 FLD_RST3_SARADC = BIT(6), 88 FLD_RST3_ALG = BIT(7), 89 }; 90 91 #define reg_clk_en REG_ADDR32(0x1401e4) 92 93 #define reg_clk_en0 REG_ADDR8(0x1401e4) 94 enum{ 95 FLD_CLK0_HSPI_EN = BIT(0), 96 FLD_CLK0_I2C_EN = BIT(1), 97 FLD_CLK0_UART0_EN = BIT(2), 98 FLD_CLK0_USB_EN = BIT(3), 99 FLD_CLK0_PWM_EN = BIT(4), 100 FLD_CLK0_UART1_EN = BIT(6), 101 FLD_CLK0_SWIRE_EN = BIT(7), 102 }; 103 104 #define reg_clk_en1 REG_ADDR8(0x1401e5) 105 enum{ 106 FLD_CLK1_SYS_TIMER_EN = BIT(1), 107 FLD_CLK1_ALGM_EN = BIT(3), 108 FLD_CLK1_PKE_EN = BIT(4), 109 FLD_CLK1_MACHINETIME_EN = BIT(5), 110 FLD_CLK1_PSPI_EN = BIT(6), 111 FLD_CLK1_SPISLV_EN = BIT(7), 112 113 }; 114 115 #define reg_clk_en2 REG_ADDR8(0x1401e6) 116 enum{ 117 FLD_CLK2_TIMER_EN = BIT(0), 118 FLD_CLK2_AUD_EN = BIT(1), 119 FLD_CLK2_TRNG_EN = BIT(2), 120 FLD_CLK2_MCU_EN = BIT(4), 121 122 FLD_CLK2_NPE_EN = BIT(6), 123 FLD_CLK2_EOC_EN = BIT(7), 124 }; 125 126 #define reg_clk_en3 REG_ADDR8(0x1401e7) 127 enum{ 128 FLD_CLK3_ZB_PCLK_EN = BIT(0), 129 FLD_CLK3_ZB_MSTCLK_EN = BIT(1), 130 FLD_CLK3_ZB_LPCLK_EN = BIT(2), 131 }; 132 133 #define reg_clk_sel0 REG_ADDR8(0x1401e8) 134 enum{ 135 FLD_CLK_SCLK_DIV = BIT_RNG(0,3), 136 FLD_CLK_SCLK_SEL = BIT_RNG(4,6), 137 FLD_CLK_MSPI_CLK_SEL = BIT(7), 138 }; 139 140 #define reg_clk_sel1 REG_ADDR8(0x1401e9) 141 enum{ 142 FLD_CLK_MSPI_DIV = BIT_RNG(4,7), 143 }; 144 145 #define reg_i2s_step REG_ADDR8(SC_BASE_ADDR+0x2a) 146 enum{ 147 FLD_I2S_STEP = BIT_RNG(0,6), 148 FLD_I2S_CLK_EN = BIT(7), 149 }; 150 151 #define reg_i2s_mod REG_ADDR8(SC_BASE_ADDR+0x2b) 152 153 154 #define reg_dmic_step REG_ADDR8(SC_BASE_ADDR+0x2c) 155 enum{ 156 FLD_DMIC_STEP = BIT_RNG(0,6), 157 FLD_DMIC_SEL = BIT(7), 158 }; 159 160 #define reg_dmic_mod REG_ADDR8(SC_BASE_ADDR+0x2d) 161 162 #define reg_wakeup_en REG_ADDR8(SC_BASE_ADDR+0x2e) 163 enum{ 164 FLD_USB_PWDN_I = BIT(0), 165 FLD_GPIO_WAKEUP_I = BIT(1), 166 FLD_USB_RESUME = BIT(2), 167 FLD_STANDBY_EX = BIT(3), 168 }; 169 170 #define reg_dmic_clk_set REG_ADDR8(SC_BASE_ADDR+0x33) 171 172 173 #define reg_wakeup_status 0x64 174 typedef enum{ 175 FLD_WKUP_CMP = BIT(0), 176 FLD_WKUP_TIMER = BIT(1), 177 FLD_WKUP_DIG = BIT(2), 178 FLD_WKUP_PAD = BIT(3), 179 FLD_WKUP_MDEC = BIT(4), 180 FLD_MDEC_RSVD = BIT_RNG(5,7), 181 }wakeup_status_e; 182 183 184
