1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	pke_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #pragma once
28 
29 #include "../sys.h"
30 
31 
32 
33 /*******************************      pke registers: 0x110000      ******************************/
34 
35 #define REG_PKE_BASE			0x110000
36 
37 #define reg_pke_ctrl			REG_ADDR32(REG_PKE_BASE+0x00)
38 enum{
39 	FLD_PKE_CTRL_START			= BIT(0),
40 	FLD_PKE_CTRL_STOP			= BIT(16),
41 };
42 
43 #define reg_pke_conf			REG_ADDR32(REG_PKE_BASE+0x04)
44 typedef enum{
45 	FLD_PKE_CONF_IRQ_EN			= BIT(8),
46 	FLD_PKE_CONF_PARTIAL_RADIX	= BIT_RNG(16,23),
47 	FLD_PKE_CONF_BASE_RADIX		= BIT_RNG(24,26),
48 }pke_conf_e;
49 
50 #define reg_pke_mc_ptr			REG_ADDR32(REG_PKE_BASE+0x10)
51 
52 #define reg_pke_stat			REG_ADDR32(REG_PKE_BASE+0x20)
53 typedef enum{
54 	FLD_PKE_STAT_DONE			= BIT(0),
55 }pke_status_e;
56 
57 #define reg_pke_rt_code			REG_ADDR32(REG_PKE_BASE+0x24)
58 enum{
59 	FLD_PKE_RT_CODE_STOP_LOG	= BIT_RNG(0,3),
60 };
61 
62 #define reg_pke_exe_conf		REG_ADDR32(REG_PKE_BASE+0x50)
63 enum{
64 	FLD_PKE_EXE_CONF_IAFF_R0	= BIT(0),
65 	FLD_PKE_EXE_CONF_IMON_R0	= BIT(1),
66 	FLD_PKE_EXE_CONF_IAFF_R1	= BIT(2),
67 	FLD_PKE_EXE_CONF_IMON_R1	= BIT(3),
68 	FLD_PKE_EXE_CONF_OAFF		= BIT(4),
69 	FLD_PKE_EXE_CONF_OMON		= BIT(5),
70 	FLD_PKE_EXE_CONF_ME_SCA_EN	= BIT_RNG(8,9),
71 };
72 
73 
74 
75 
76