Searched refs:optr_reg_mask (Results 1 – 7 of 7) sorted by relevance
1098 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local1110 optr_reg_mask |= FLASH_OPTR_BOR_LEV; in FLASH_OB_UserConfig()1120 optr_reg_mask |= FLASH_OPTR_nRST_STOP; in FLASH_OB_UserConfig()1130 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; in FLASH_OB_UserConfig()1140 optr_reg_mask |= FLASH_OPTR_nRST_SHDW; in FLASH_OB_UserConfig()1150 optr_reg_mask |= FLASH_OPTR_SRAM_RST; in FLASH_OB_UserConfig()1160 optr_reg_mask |= FLASH_OPTR_IWDG_SW; in FLASH_OB_UserConfig()1170 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; in FLASH_OB_UserConfig()1180 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; in FLASH_OB_UserConfig()1190 optr_reg_mask |= FLASH_OPTR_WWDG_SW; in FLASH_OB_UserConfig()[all …]
955 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local967 optr_reg_mask |= FLASH_OBW1SR_BOR_LEVEL; in FLASH_OB_UserConfig()977 optr_reg_mask |= FLASH_OBW1SR_IWDG_HW; in FLASH_OB_UserConfig()987 optr_reg_mask |= FLASH_OBW1SR_NRST_STOP; in FLASH_OB_UserConfig()997 optr_reg_mask |= FLASH_OBW1SR_NRST_STBY; in FLASH_OB_UserConfig()1007 optr_reg_mask |= FLASH_OBW1SR_XSPI1_HSLV; in FLASH_OB_UserConfig()1017 optr_reg_mask |= FLASH_OBW1SR_XSPI2_HSLV; in FLASH_OB_UserConfig()1027 optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STOP; in FLASH_OB_UserConfig()1037 optr_reg_mask |= FLASH_OBW1SR_IWDG_FZ_STBY; in FLASH_OB_UserConfig()1047 optr_reg_mask |= FLASH_OBW1SR_VDDIO_HSLV; in FLASH_OB_UserConfig()[all …]
959 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local971 optr_reg_mask |= FLASH_OPTR_BOR_LEV; in FLASH_OB_UserConfig()981 optr_reg_mask |= FLASH_OPTR_nRST_STOP; in FLASH_OB_UserConfig()991 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; in FLASH_OB_UserConfig()1001 optr_reg_mask |= FLASH_OPTR_nRST_SHDW; in FLASH_OB_UserConfig()1011 optr_reg_mask |= FLASH_OPTR_IWDG_SW; in FLASH_OB_UserConfig()1021 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; in FLASH_OB_UserConfig()1031 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; in FLASH_OB_UserConfig()1041 optr_reg_mask |= FLASH_OPTR_WWDG_SW; in FLASH_OB_UserConfig()1051 optr_reg_mask |= FLASH_OPTR_SWAP_BANK; in FLASH_OB_UserConfig()[all …]
789 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local808 optr_reg_mask |= FLASH_OPTR_PB4_PUPEN; in FLASH_OB_UserConfig()819 optr_reg_mask |= FLASH_OPTR_BOR_LEV; in FLASH_OB_UserConfig()829 optr_reg_mask |= FLASH_OPTR_nRST_STOP; in FLASH_OB_UserConfig()839 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; in FLASH_OB_UserConfig()849 optr_reg_mask |= FLASH_OPTR_nRST_SHDW; in FLASH_OB_UserConfig()859 optr_reg_mask |= FLASH_OPTR_IWDG_SW; in FLASH_OB_UserConfig()869 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; in FLASH_OB_UserConfig()879 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; in FLASH_OB_UserConfig()889 optr_reg_mask |= FLASH_OPTR_WWDG_SW; in FLASH_OB_UserConfig()[all …]
774 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local792 optr_reg_mask |= FLASH_OPTR_BOR_LEV; in FLASH_OB_UserConfig()802 optr_reg_mask |= FLASH_OPTR_nRST_STOP; in FLASH_OB_UserConfig()812 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; in FLASH_OB_UserConfig()822 optr_reg_mask |= FLASH_OPTR_nRST_SHDW; in FLASH_OB_UserConfig()832 optr_reg_mask |= FLASH_OPTR_IWDG_SW; in FLASH_OB_UserConfig()842 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; in FLASH_OB_UserConfig()852 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; in FLASH_OB_UserConfig()862 optr_reg_mask |= FLASH_OPTR_WWDG_SW; in FLASH_OB_UserConfig()876 optr_reg_mask |= FLASH_OPTR_BFB2; in FLASH_OB_UserConfig()[all …]
1167 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local1179 optr_reg_mask |= FLASH_OPTR_BOR_LEV; in FLASH_OB_UserConfig()1189 optr_reg_mask |= FLASH_OPTR_nRST_STOP; in FLASH_OB_UserConfig()1199 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; in FLASH_OB_UserConfig()1209 optr_reg_mask |= FLASH_OPTR_SRAM1_RST; in FLASH_OB_UserConfig()1219 optr_reg_mask |= FLASH_OPTR_IWDG_SW; in FLASH_OB_UserConfig()1229 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; in FLASH_OB_UserConfig()1239 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; in FLASH_OB_UserConfig()1249 optr_reg_mask |= FLASH_OPTR_WWDG_SW; in FLASH_OB_UserConfig()1260 optr_reg_mask |= FLASH_OPTR_SRAM2_PE; in FLASH_OB_UserConfig()[all …]
1433 uint32_t optr_reg_mask = 0; in FLASH_OB_UserConfig() local1445 optr_reg_mask |= FLASH_OPTSR_IWDG1_SW; in FLASH_OB_UserConfig()1455 optr_reg_mask |= FLASH_OPTSR_IWDG2_SW; in FLASH_OB_UserConfig()1465 optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1; in FLASH_OB_UserConfig()1475 optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1; in FLASH_OB_UserConfig()1485 optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP; in FLASH_OB_UserConfig()1495 optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY; in FLASH_OB_UserConfig()1505 optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE; in FLASH_OB_UserConfig()1515 optr_reg_mask |= FLASH_OPTSR_SECURITY; in FLASH_OB_UserConfig()1526 optr_reg_mask |= FLASH_OPTSR_BCM4; in FLASH_OB_UserConfig()[all …]
