Searched refs:core (Results 1 – 8 of 8) sorted by relevance
| /hal_stm32-latest/lib/stm32wb/ |
| D | README.rst | 13 a host BLE running on CM-4 STM32WB core and a controller BLE firmware running
14 on CM-0 core.
18 firmware running on STM32WB C-M0 core.
21 Middlewares/ST/STM32_WPAN/ble/core/ble_bufsize.h
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| /hal_stm32-latest/lib/ |
| D | README.rst | 7 the host core and the controller core of the STM32WB.
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| /hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/ |
| D | stm32mp1xx_ll_hsem.h | 292 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) in LL_HSEM_ResetAllLock() argument
294 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); in LL_HSEM_ResetAllLock()
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| /hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/ |
| D | stm32h7xx_ll_hsem.h | 304 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) in LL_HSEM_ResetAllLock() argument
306 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); in LL_HSEM_ResetAllLock()
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| /hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/ |
| D | stm32wbaxx_ll_hsem.h | 321 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core, uint32_… in LL_HSEM_ResetAllLock() argument
323 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core | attribute); in LL_HSEM_ResetAllLock()
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| /hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/ |
| D | stm32wlxx_ll_hsem.h | 300 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) in LL_HSEM_ResetAllLock() argument
302 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); in LL_HSEM_ResetAllLock()
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| /hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/ |
| D | stm32wbxx_ll_hsem.h | 298 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) in LL_HSEM_ResetAllLock() argument
300 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); in LL_HSEM_ResetAllLock()
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| /hal_stm32-latest/stm32cube/ |
| D | CMakeLists.txt | 76 # On dual-core MCUs, we must inform Cube which CPU we are building for.
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