1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H5xx_LL_RCC_H
21 #define __STM32H5xx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
44 * @{
45 */
46 /* Defines used for security configuration extension */
47 #define RCC_SECURE_MASK 0x3BFFU
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53 #if !defined(UNUSED)
54 #define UNUSED(x) ((void)(x))
55 #endif /* !UNUSED */
56
57 /* 32 24 16 8 0
58 --------------------------------------------------------
59 | Mask | ClkSource | Bit | Register |
60 | | Config | Position | Offset |
61 --------------------------------------------------------*/
62
63 /* Clock source register offset */
64 #define CCIPR1_OFFSET 0x00UL
65 #define CCIPR2_OFFSET 0x04UL
66 #define CCIPR3_OFFSET 0x08UL
67 #define CCIPR4_OFFSET 0x0CUL
68 #define CCIPR5_OFFSET 0x10UL
69
70 #define LL_RCC_REG_SHIFT 0U
71 #define LL_RCC_POS_SHIFT 8U
72 #define LL_RCC_CONFIG_SHIFT 16U
73 #define LL_RCC_MASK_SHIFT 24U
74
75 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
76
77 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\
78 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
79
80 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\
81 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
82
83 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
84
85 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
86 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
87 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
88 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
89
90 /* Exported types ------------------------------------------------------------*/
91 #if defined(USE_FULL_LL_DRIVER)
92 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
93 * @{
94 */
95
96 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
97 * @{
98 */
99
100 /**
101 * @brief RCC Clocks Frequency Structure
102 */
103 typedef struct
104 {
105 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
106 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
107 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
108 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
109 uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */
110 } LL_RCC_ClocksTypeDef;
111
112 /**
113 * @brief PLL Clocks Frequency Structure
114 */
115 typedef struct
116 {
117 uint32_t PLL_P_Frequency;
118 uint32_t PLL_Q_Frequency;
119 uint32_t PLL_R_Frequency;
120 } LL_PLL_ClocksTypeDef;
121
122 /**
123 * @}
124 */
125
126 /**
127 * @}
128 */
129 #endif /* USE_FULL_LL_DRIVER */
130
131 /* Exported constants --------------------------------------------------------*/
132 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
133 * @{
134 */
135
136 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
137 * @brief Defines used to adapt values of different oscillators
138 * @note These values could be modified in the user environment according to
139 * HW set-up.
140 * @{
141 */
142 #if !defined (HSE_VALUE)
143 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
144 #endif /* HSE_VALUE */
145
146 #if !defined (HSI_VALUE)
147 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
148 #endif /* HSI_VALUE */
149
150 #if !defined (CSI_VALUE)
151 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
152 #endif /* CSI_VALUE */
153
154 #if !defined (LSE_VALUE)
155 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
156 #endif /* LSE_VALUE */
157
158 #if !defined (LSI_VALUE)
159 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
160 #endif /* LSI_VALUE */
161
162 #if !defined (HSI48_VALUE)
163 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
164 #endif /* HSI48_VALUE */
165
166 #if !defined (EXTERNAL_CLOCK_VALUE)
167 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
168 #endif /* EXTERNAL_CLOCK_VALUE */
169
170 /**
171 * @}
172 */
173
174 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
175 * @{
176 */
177 #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI_DIV1 clock activation */
178 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI_DIV2 clock activation */
179 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI_DIV4 clock activation */
180 #define LL_RCC_HSI_DIV_8 RCC_CR_HSIDIV /*!< HSI_DIV8 clock activation */
181 /**
182 * @}
183 */
184
185 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
186 * @{
187 */
188 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
189 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
190 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
191 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
192 /**
193 * @}
194 */
195
196 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
197 * @{
198 */
199 #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI oscillator selection as system clock */
200 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI oscillator selection as system clock */
201 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE oscillator selection as system clock */
202 #define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1 selection as system clock */
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
208 * @{
209 */
210 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
211 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI oscillator used as system clock */
212 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE oscillator used as system clock */
213 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */
214 /**
215 * @}
216 */
217
218 /** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE clock Type
219 * @{
220 */
221 #define LL_RCC_HSE_ANALOG_TYPE 0U /*!< ANALOG clock used as HSE external clock source */
222 #define LL_RCC_HSE_DIGITAL_TYPE RCC_CR_HSEEXT /*!< DIGITAL clock used as HSE external clock source */
223 /**
224 * @}
225 */
226
227 /** @defgroup RCC_LL_EC_LSEEXT EXTERNAL LSE clock Type
228 * @{
229 */
230 #define LL_RCC_LSE_ANALOG_TYPE 0U /*!< ANALOG clock used as LSE external clock source */
231 #define LL_RCC_LSE_DIGITAL_TYPE RCC_BDCR_LSEEXT /*!< DIGITAL clock used as LSE external clock source */
232 /**
233 * @}
234 */
235
236 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
237 * @{
238 */
239 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
240 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
241 /**
242 * @}
243 */
244
245 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
246 * @{
247 */
248 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
249 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */
250 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */
251 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */
252 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */
253 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */
254 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */
255 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */
256 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
262 * @{
263 */
264 #define LL_RCC_APB1_DIV_1 (0x00000000U) /*!< HCLK not divided */
265 #define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
266 #define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */
267 #define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */
268 #define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
274 * @{
275 */
276 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */
277 #define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
278 #define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
279 #define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
280 #define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
281 /**
282 * @}
283 */
284
285 /** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3)
286 * @{
287 */
288 #define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */
289 #define LL_RCC_APB3_DIV_2 RCC_CFGR2_PPRE3_2 /*!< HCLK divided by 2 */
290 #define LL_RCC_APB3_DIV_4 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 4 */
291 #define LL_RCC_APB3_DIV_8 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1) /*!< HCLK divided by 8 */
292 #define LL_RCC_APB3_DIV_16 (RCC_CFGR2_PPRE3_2 | RCC_CFGR2_PPRE3_1 | RCC_CFGR2_PPRE3_0) /*!< HCLK divided by 16 */
293 /**
294 * @}
295 */
296
297 /** @defgroup RCC_LL_EC_AHB1_PERIPH AHB1 peripherals clock branch disable
298 * @{
299 */
300 #define LL_RCC_AHB1_PERIPH_DIS RCC_CFGR2_AHB1DIS /*!< Clock Branch disable for all AHB1 peripherals */
301 /**
302 * @}
303 */
304
305 /** @defgroup RCC_LL_EC_AHB2_PERIPH AHB2 peripherals clock branch disable
306 * @{
307 */
308 #define LL_RCC_AHB2_PERIPH_DIS RCC_CFGR2_AHB2DIS /*!< Clock Branch disable for all AHB2 peripherals */
309 /**
310 * @}
311 */
312
313 /** @defgroup RCC_LL_EC_AHB4_PERIPH AHB4 peripherals clock branch disable
314 * @{
315 */
316 #define LL_RCC_AHB4_PERIPH_DIS RCC_CFGR2_AHB4DIS /*!< Clock Branch disable for all AHB4 peripherals */
317 /**
318 * @}
319 */
320
321 /** @defgroup RCC_LL_EC_APB1_PERIPH APB1 peripherals clock branch disable
322 * @{
323 */
324 #define LL_RCC_APB1_PERIPH_DIS RCC_CFGR2_APB1DIS /*!< Clock Branch disable for all APB1 peripherals */
325 /**
326 * @}
327 */
328
329 /** @defgroup RCC_LL_EC_APB2_PERIPH APB2 peripherals clock branch disable
330 * @{
331 */
332 #define LL_RCC_APB2_PERIPH_DIS RCC_CFGR2_APB2DIS /*!< Clock Branch disable for all APB2 peripherals */
333 /**
334 * @}
335 */
336
337 /** @defgroup RCC_LL_EC_APB3_PERIPH APB3 peripherals clock branch disable
338 * @{
339 */
340 #define LL_RCC_APB3_PERIPH_DIS RCC_CFGR2_APB3DIS /*!< Clock Branch disable for all APB3 peripherals */
341 /**
342 * @}
343 */
344
345 /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
346 * @{
347 */
348 #define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */
349 #define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR4_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
350 #define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR4_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
351 /**
352 * @}
353 */
354
355 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup from stop and CSS backup clock selection
356 * @{
357 */
358 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock after wake-up from STOP */
359 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection as system clock after wake-up from STOP */
360 /**
361 * @}
362 */
363
364 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup from stop clock source
365 * @{
366 */
367 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as kernel clock after wake-up from STOP */
368 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI selection as kernel clock after wake-up from STOP */
369 /**
370 * @}
371 */
372
373 /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
374 * @{
375 */
376 #define LL_RCC_RTC_HSE_NOCLOCK (0x00000000U)
377 #define LL_RCC_RTC_HSE_DIV_2 (0x00000200U)
378 #define LL_RCC_RTC_HSE_DIV_3 (0x00000300U)
379 #define LL_RCC_RTC_HSE_DIV_4 (0x00000400U)
380 #define LL_RCC_RTC_HSE_DIV_5 (0x00000500U)
381 #define LL_RCC_RTC_HSE_DIV_6 (0x00000600U)
382 #define LL_RCC_RTC_HSE_DIV_7 (0x00000700U)
383 #define LL_RCC_RTC_HSE_DIV_8 (0x00000800U)
384 #define LL_RCC_RTC_HSE_DIV_9 (0x00000900U)
385 #define LL_RCC_RTC_HSE_DIV_10 (0x00000A00U)
386 #define LL_RCC_RTC_HSE_DIV_11 (0x00000B00U)
387 #define LL_RCC_RTC_HSE_DIV_12 (0x00000C00U)
388 #define LL_RCC_RTC_HSE_DIV_13 (0x00000D00U)
389 #define LL_RCC_RTC_HSE_DIV_14 (0x00000E00U)
390 #define LL_RCC_RTC_HSE_DIV_15 (0x00000F00U)
391 #define LL_RCC_RTC_HSE_DIV_16 (0x00001000U)
392 #define LL_RCC_RTC_HSE_DIV_17 (0x00001100U)
393 #define LL_RCC_RTC_HSE_DIV_18 (0x00001200U)
394 #define LL_RCC_RTC_HSE_DIV_19 (0x00001300U)
395 #define LL_RCC_RTC_HSE_DIV_20 (0x00001400U)
396 #define LL_RCC_RTC_HSE_DIV_21 (0x00001500U)
397 #define LL_RCC_RTC_HSE_DIV_22 (0x00001600U)
398 #define LL_RCC_RTC_HSE_DIV_23 (0x00001700U)
399 #define LL_RCC_RTC_HSE_DIV_24 (0x00001800U)
400 #define LL_RCC_RTC_HSE_DIV_25 (0x00001900U)
401 #define LL_RCC_RTC_HSE_DIV_26 (0x00001A00U)
402 #define LL_RCC_RTC_HSE_DIV_27 (0x00001B00U)
403 #define LL_RCC_RTC_HSE_DIV_28 (0x00001C00U)
404 #define LL_RCC_RTC_HSE_DIV_29 (0x00001D00U)
405 #define LL_RCC_RTC_HSE_DIV_30 (0x00001E00U)
406 #define LL_RCC_RTC_HSE_DIV_31 (0x00001F00U)
407 #define LL_RCC_RTC_HSE_DIV_32 (0x00002000U)
408 #define LL_RCC_RTC_HSE_DIV_33 (0x00002100U)
409 #define LL_RCC_RTC_HSE_DIV_34 (0x00002200U)
410 #define LL_RCC_RTC_HSE_DIV_35 (0x00002300U)
411 #define LL_RCC_RTC_HSE_DIV_36 (0x00002400U)
412 #define LL_RCC_RTC_HSE_DIV_37 (0x00002500U)
413 #define LL_RCC_RTC_HSE_DIV_38 (0x00002600U)
414 #define LL_RCC_RTC_HSE_DIV_39 (0x00002700U)
415 #define LL_RCC_RTC_HSE_DIV_40 (0x00002800U)
416 #define LL_RCC_RTC_HSE_DIV_41 (0x00002900U)
417 #define LL_RCC_RTC_HSE_DIV_42 (0x00002A00U)
418 #define LL_RCC_RTC_HSE_DIV_43 (0x00002B00U)
419 #define LL_RCC_RTC_HSE_DIV_44 (0x00002C00U)
420 #define LL_RCC_RTC_HSE_DIV_45 (0x00002D00U)
421 #define LL_RCC_RTC_HSE_DIV_46 (0x00002E00U)
422 #define LL_RCC_RTC_HSE_DIV_47 (0x00002F00U)
423 #define LL_RCC_RTC_HSE_DIV_48 (0x00003000U)
424 #define LL_RCC_RTC_HSE_DIV_49 (0x00003100U)
425 #define LL_RCC_RTC_HSE_DIV_50 (0x00003200U)
426 #define LL_RCC_RTC_HSE_DIV_51 (0x00003300U)
427 #define LL_RCC_RTC_HSE_DIV_52 (0x00003400U)
428 #define LL_RCC_RTC_HSE_DIV_53 (0x00003500U)
429 #define LL_RCC_RTC_HSE_DIV_54 (0x00003600U)
430 #define LL_RCC_RTC_HSE_DIV_55 (0x00003700U)
431 #define LL_RCC_RTC_HSE_DIV_56 (0x00003800U)
432 #define LL_RCC_RTC_HSE_DIV_57 (0x00003900U)
433 #define LL_RCC_RTC_HSE_DIV_58 (0x00003A00U)
434 #define LL_RCC_RTC_HSE_DIV_59 (0x00003B00U)
435 #define LL_RCC_RTC_HSE_DIV_60 (0x00003C00U)
436 #define LL_RCC_RTC_HSE_DIV_61 (0x00003D00U)
437 #define LL_RCC_RTC_HSE_DIV_62 (0x00003E00U)
438 #define LL_RCC_RTC_HSE_DIV_63 (0x00003F00U)
439 /**
440 * @}
441 */
442
443 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
444 * @{
445 */
446 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
447 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR1_TIMPRE)
448 /**
449 * @}
450 */
451
452 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO SOURCE selection
453 * @{
454 */
455 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | 0x00000000U)
456 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_0)
457 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_1)
458 #define LL_RCC_MCO1SOURCE_PLL1Q (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) |\
459 RCC_CFGR1_MCO1SEL_1|RCC_CFGR1_MCO1SEL_0)
460 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR1_MCO1SEL>>16U) | RCC_CFGR1_MCO1SEL_2)
461 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | 0x00000000U)
462 #define LL_RCC_MCO2SOURCE_PLL2P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_0)
463 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_1)
464 #define LL_RCC_MCO2SOURCE_PLL1P (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\
465 RCC_CFGR1_MCO2SEL_1|RCC_CFGR1_MCO2SEL_0)
466 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) | RCC_CFGR1_MCO2SEL_2)
467 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR1_MCO2SEL>>16U) |\
468 RCC_CFGR1_MCO2SEL_2|RCC_CFGR1_MCO2SEL_0)
469 /**
470 * @}
471 */
472
473 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
474 * @{
475 */
476 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_0)
477 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_1)
478 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
479 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1)
480 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_2)
481 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
482 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2)
483 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
484 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2)
485 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
486 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2)
487 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE_3)
488 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
489 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3)
490 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
491 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3)
492 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
493 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3)
494 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
495 RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
496 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
497 RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
498 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) |\
499 RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3)
500 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR1_MCO1PRE>>16U) | RCC_CFGR1_MCO1PRE)
501 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_0)
502 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_1)
503 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
504 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1)
505 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_2)
506 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
507 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2)
508 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
509 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2)
510 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
511 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2)
512 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE_3)
513 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
514 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_3)
515 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
516 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3)
517 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
518 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_3)
519 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
520 RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
521 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
522 RCC_CFGR1_MCO2PRE_0 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
523 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) |\
524 RCC_CFGR1_MCO2PRE_1 | RCC_CFGR1_MCO2PRE_2 | RCC_CFGR1_MCO2PRE_3)
525 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR1_MCO2PRE>>16U) | RCC_CFGR1_MCO2PRE)
526 /**
527 * @}
528 */
529
530 #if defined(USE_FULL_LL_DRIVER)
531 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
532 * @{
533 */
534 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
535 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
536 /**
537 * @}
538 */
539 #endif /* USE_FULL_LL_DRIVER */
540
541 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
542 * @{
543 */
544 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
545 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
546 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
547 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by RTCPRE used as RTC clock */
548 /**
549 * @}
550 */
551
552 /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
553 * @{
554 */
555 #define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
556 #define LL_RCC_USART1_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_0) /*!< PLL2 Q clock used as USART1 clock source */
557 #if defined(RCC_CR_PLL3ON)
558 #define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1) /*!< PLL3 Q clock used as USART1 clock source */
559 #endif /* PLL3 */
560 #define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_1 | RCC_CCIPR1_USART1SEL_0) /*!< HSI clock used as USART1 clock source */
561 #define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2) /*!< CSI clock used as USART1 clock source */
562 #define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, RCC_CCIPR1_USART1SEL_2 | RCC_CCIPR1_USART1SEL_0) /*!< LSE clock used as USART1 clock source */
563
564 #define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
565 #define LL_RCC_USART2_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_0) /*!< PLL2 Q clock used as USART2 clock source */
566 #if defined(RCC_CR_PLL3ON)
567 #define LL_RCC_USART2_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1) /*!< PLL3 Q clock used as USART2 clock source */
568 #endif /* PLL3 */
569 #define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_1 | RCC_CCIPR1_USART2SEL_0) /*!< HSI clock used as USART2 clock source */
570 #define LL_RCC_USART2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2) /*!< CSI clock used as USART2 clock source */
571 #define LL_RCC_USART2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIPR1_USART2SEL_2 | RCC_CCIPR1_USART2SEL_0) /*!< LSE clock used as USART2 clock source */
572
573 #define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
574 #define LL_RCC_USART3_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_0) /*!< PLL2 Q clock used as USART3 clock source */
575 #if defined(RCC_CR_PLL3ON)
576 #define LL_RCC_USART3_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1) /*!< PLL3 Q clock used as USART3 clock source */
577 #endif /* PLL3 */
578 #define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_1 | RCC_CCIPR1_USART3SEL_0) /*!< HSI clock used as USART3 clock source */
579 #define LL_RCC_USART3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2) /*!< CSI clock used as USART3 clock source */
580 #define LL_RCC_USART3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, RCC_CCIPR1_USART3SEL_2 | RCC_CCIPR1_USART3SEL_0) /*!< LSE clock used as USART3 clock source */
581
582 #if defined(USART6)
583 #define LL_RCC_USART6_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART6 clock source */
584 #define LL_RCC_USART6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_0) /*!< PLL2 Q clock used as USART6 clock source */
585 #define LL_RCC_USART6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1) /*!< PLL3 Q clock used as USART6 clock source */
586 #define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_1 | RCC_CCIPR1_USART6SEL_0) /*!< HSI clock used as USART6 clock source */
587 #define LL_RCC_USART6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2) /*!< CSI clock used as USART6 clock source */
588 #define LL_RCC_USART6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, RCC_CCIPR1_USART6SEL_2 | RCC_CCIPR1_USART6SEL_0) /*!< LSE clock used as USART6 clock source */
589 #endif /* USART6 */
590
591 #if defined(USART10)
592 #define LL_RCC_USART10_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART10 clock source */
593 #define LL_RCC_USART10_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_0) /*!< PLL2 Q clock used as USART10 clock source */
594 #define LL_RCC_USART10_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1) /*!< PLL3 Q clock used as USART10 clock source */
595 #define LL_RCC_USART10_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_1 | RCC_CCIPR1_USART10SEL_0) /*!< HSI clock used as USART10 clock source */
596 #define LL_RCC_USART10_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2) /*!< CSI clock used as USART10 clock source */
597 #define LL_RCC_USART10_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, RCC_CCIPR1_USART10SEL_2 | RCC_CCIPR1_USART10SEL_0) /*!< LSE clock used as USART10 clock source */
598 #endif /* USART10 */
599
600 #if defined(USART11)
601 #define LL_RCC_USART11_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as USART11 clock source */
602 #define LL_RCC_USART11_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_0) /*!< PLL2 Q clock used as USART11 clock source */
603 #define LL_RCC_USART11_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1) /*!< PLL3 Q clock used as USART11 clock source */
604 #define LL_RCC_USART11_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_1 | RCC_CCIPR2_USART11SEL_0) /*!< HSI clock used as USART11 clock source */
605 #define LL_RCC_USART11_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2) /*!< CSI clock used as USART11 clock source */
606 #define LL_RCC_USART11_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, RCC_CCIPR2_USART11SEL_2 | RCC_CCIPR2_USART11SEL_0) /*!< LSE clock used as USART11 clock source */
607 #endif /* USART11 */
608 /**
609 * @}
610 */
611
612 #if defined(UART4)
613 /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection
614 * @{
615 */
616 #define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
617 #define LL_RCC_UART4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_0) /*!< PLL2 Q clock used as UART4 clock source */
618 #define LL_RCC_UART4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1) /*!< PLL3 Q clock used as UART4 clock source */
619 #define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_1 | RCC_CCIPR1_UART4SEL_0) /*!< HSI clock used as UART4 clock source */
620 #define LL_RCC_UART4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2) /*!< CSI clock used as UART4 clock source */
621 #define LL_RCC_UART4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, RCC_CCIPR1_UART4SEL_2 | RCC_CCIPR1_UART4SEL_0) /*!< LSE clock used as UART4 clock source */
622
623 #define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
624 #define LL_RCC_UART5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_0) /*!< PLL2 Q clock used as UART5 clock source */
625 #define LL_RCC_UART5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1) /*!< PLL3 Q clock used as UART5 clock source */
626 #define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_1 | RCC_CCIPR1_UART5SEL_0) /*!< HSI clock used as UART5 clock source */
627 #define LL_RCC_UART5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2) /*!< CSI clock used as UART5 clock source */
628 #define LL_RCC_UART5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, RCC_CCIPR1_UART5SEL_2 | RCC_CCIPR1_UART5SEL_0) /*!< LSE clock used as UART5 clock source */
629
630 #define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */
631 #define LL_RCC_UART7_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_0) /*!< PLL2 Q clock used as UART7 clock source */
632 #define LL_RCC_UART7_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1) /*!< PLL3 Q clock used as UART7 clock source */
633 #define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_1 | RCC_CCIPR1_UART7SEL_0) /*!< HSI clock used as UART7 clock source */
634 #define LL_RCC_UART7_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2) /*!< CSI clock used as UART7 clock source */
635 #define LL_RCC_UART7_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, RCC_CCIPR1_UART7SEL_2 | RCC_CCIPR1_UART7SEL_0) /*!< LSE clock used as UART7 clock source */
636
637 #define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */
638 #define LL_RCC_UART8_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_0) /*!< PLL2 Q clock used as UART8 clock source */
639 #define LL_RCC_UART8_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1) /*!< PLL3 Q clock used as UART8 clock source */
640 #define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_1 | RCC_CCIPR1_UART8SEL_0) /*!< HSI clock used as UART8 clock source */
641 #define LL_RCC_UART8_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2) /*!< CSI clock used as UART8 clock source */
642 #define LL_RCC_UART8_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, RCC_CCIPR1_UART8SEL_2 | RCC_CCIPR1_UART8SEL_0) /*!< LSE clock used as UART8 clock source */
643
644 #define LL_RCC_UART9_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART9 clock source */
645 #define LL_RCC_UART9_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_0) /*!< PLL2 Q clock used as UART9 clock source */
646 #define LL_RCC_UART9_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1) /*!< PLL3 Q clock used as UART9 clock source */
647 #define LL_RCC_UART9_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_1 | RCC_CCIPR1_UART9SEL_0) /*!< HSI clock used as UART9 clock source */
648 #define LL_RCC_UART9_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2) /*!< CSI clock used as UART9 clock source */
649 #define LL_RCC_UART9_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, RCC_CCIPR1_UART9SEL_2 | RCC_CCIPR1_UART9SEL_0) /*!< LSE clock used as UART9 clock source */
650
651 #define LL_RCC_UART12_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as UART12 clock source */
652 #define LL_RCC_UART12_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_0) /*!< PLL2 Q clock used as UART12 clock source */
653 #define LL_RCC_UART12_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1) /*!< PLL3 Q clock used as UART12 clock source */
654 #define LL_RCC_UART12_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_1 | RCC_CCIPR2_UART12SEL_0) /*!< HSI clock used as UART12 clock source */
655 #define LL_RCC_UART12_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2) /*!< CSI clock used as UART12 clock source */
656 #define LL_RCC_UART12_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, RCC_CCIPR2_UART12SEL_2 | RCC_CCIPR2_UART12SEL_0) /*!< LSE clock used as UART12 clock source */
657 /**
658 * @}
659 */
660 #endif /* UART4 */
661
662 /** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
663 * @{
664 */
665 #define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */
666 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q RCC_CCIPR3_LPUART1SEL_0 /*!< PLL2Q clock used as LPUART1 clock source */
667 #if defined(RCC_CR_PLL3ON)
668 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q RCC_CCIPR3_LPUART1SEL_1 /*!< PLL3Q clock used as LPUART1 clock source */
669 #endif /* PLL3 */
670 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */
671 #define LL_RCC_LPUART1_CLKSOURCE_CSI RCC_CCIPR3_LPUART1SEL_2 /*!< CSI clock used as LPUART1 clock source */
672 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_2) /*!< LSE clock used as LPUART1 clock source */
673 /**
674 * @}
675 */
676
677 /** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
678 * @{
679 */
680 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
681 #if defined(RCC_CR_PLL3ON)
682 #define LL_RCC_I2C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL3 R clock used as I2C1 clock source */
683 #else
684 #define LL_RCC_I2C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_0) /*!< PLL2 R clock used as I2C1 clock source */
685 #endif /* PLL3 */
686 #define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */
687 #define LL_RCC_I2C1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, RCC_CCIPR4_I2C1SEL) /*!< CSI clock used as I2C1 clock source */
688
689 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
690 #if defined(RCC_CR_PLL3ON)
691 #define LL_RCC_I2C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL3 R clock used as I2C2 clock source */
692 #else
693 #define LL_RCC_I2C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_0) /*!< PLL2 R clock used as I2C2 clock source */
694 #endif /* PLL3 */
695 #define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */
696 #define LL_RCC_I2C2_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, RCC_CCIPR4_I2C2SEL) /*!< CSI clock used as I2C2 clock source */
697
698 #if defined(I2C3)
699 #define LL_RCC_I2C3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C3 clock source */
700 #define LL_RCC_I2C3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_0) /*!< PLL3 R clock used as I2C3 clock source */
701 #define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL_1) /*!< HSI clock used as I2C3 clock source */
702 #define LL_RCC_I2C3_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, RCC_CCIPR4_I2C3SEL) /*!< CSI clock used as I2C3 clock source */
703 #endif /* I2C3 */
704
705 #if defined(I2C4)
706 #define LL_RCC_I2C4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I2C4 clock source */
707 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_0) /*!< PLL3 R clock used as I2C4 clock source */
708 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL_1) /*!< HSI clock used as I2C4 clock source */
709 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, RCC_CCIPR4_I2C4SEL) /*!< CSI clock used as I2C4 clock source */
710 #endif /* I2C4 */
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3Cx clock source selection
716 * @{
717 */
718 #define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as I3C1 clock source */
719 #if defined(RCC_CR_PLL3ON)
720 #define LL_RCC_I3C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL3 R clock used as I3C1 clock source */
721 #else
722 #define LL_RCC_I3C1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_0) /*!< PLL2 R clock used as I3C1 clock source */
723 #endif /* PLL3 */
724 #define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL_1) /*!< HSI clock used as I3C1 clock source */
725 #define LL_RCC_I3C1_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR4_I3C1SEL) /*!< NONE clock used as I3C1 clock source */
726
727 #if defined(I3C2)
728 #define LL_RCC_I3C2_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as I3C2 clock source */
729 #if defined(RCC_CR_PLL3ON)
730 #define LL_RCC_I3C2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL3 R clock used as I3C2 clock source */
731 #else
732 #define LL_RCC_I3C2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_0) /*!< PLL2 R clock used as I3C2 clock source */
733 #endif /* PLL3 */
734 #define LL_RCC_I3C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL_1) /*!< HSI clock used as I3C2 clock source */
735 #define LL_RCC_I3C2_CLKSOURCE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, RCC_CCIPR4_I3C2SEL) /*!< NONE clock used as I3C2 clock source */
736 #endif /* I3C2 */
737 /**
738 * @}
739 */
740
741 /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
742 * @{
743 */
744 #define LL_RCC_SPI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI1 clock source */
745 #define LL_RCC_SPI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_0) /*!< PLL2 P clock used as SPI1 clock source */
746 #if defined(RCC_CR_PLL3ON)
747 #define LL_RCC_SPI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1) /*!< PLL3 P clock used as SPI1 clock source */
748 #endif /* PLL3 */
749 #define LL_RCC_SPI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1 | RCC_CCIPR3_SPI1SEL_0) /*!< PIN clock used as SPI1 clock source */
750 #define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_2) /*!< CLKP clock used as SPI1 clock source */
751
752 #define LL_RCC_SPI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI2 clock source */
753 #define LL_RCC_SPI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_0) /*!< PLL2 P clock used as SPI2 clock source */
754 #if defined(RCC_CR_PLL3ON)
755 #define LL_RCC_SPI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1) /*!< PLL3 P clock used as SPI2 clock source */
756 #endif /* PLL3 */
757 #define LL_RCC_SPI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_1 | RCC_CCIPR3_SPI2SEL_0) /*!< PIN clock used as SPI2 clock source */
758 #define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, RCC_CCIPR3_SPI2SEL_2) /*!< CLKP clock used as SPI2 clock source */
759
760 #define LL_RCC_SPI3_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SPI3 clock source */
761 #define LL_RCC_SPI3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_0) /*!< PLL2 P clock used as SPI3 clock source */
762 #if defined(RCC_CR_PLL3ON)
763 #define LL_RCC_SPI3_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1) /*!< PLL3 P clock used as SPI3 clock source */
764 #endif /* PLL3 */
765 #define LL_RCC_SPI3_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_1 | RCC_CCIPR3_SPI3SEL_0) /*!< PIN clock used as SPI3 clock source */
766 #define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, RCC_CCIPR3_SPI3SEL_2) /*!< CLKP clock used as SPI3 clock source */
767
768 #if defined(SPI4)
769 #define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI4 clock source */
770 #define LL_RCC_SPI4_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_0) /*!< PLL2 Q clock used as SPI4 clock source */
771 #define LL_RCC_SPI4_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1) /*!< PLL3 Q clock used as SPI4 clock source */
772 #define LL_RCC_SPI4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_1 | RCC_CCIPR3_SPI4SEL_0) /*!< HSI clock used as SPI4 clock source */
773 #define LL_RCC_SPI4_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2) /*!< CSI clock used as SPI4 clock source */
774 #define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, RCC_CCIPR3_SPI4SEL_2 | RCC_CCIPR3_SPI4SEL_0) /*!< HSE clock used as SPI4 clock source */
775 #endif /* SPI4 */
776
777 #if defined(SPI5)
778 #define LL_RCC_SPI5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI5 clock source */
779 #define LL_RCC_SPI5_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_0) /*!< PLL2 Q clock used as SPI5 clock source */
780 #define LL_RCC_SPI5_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1) /*!< PLL3 Q clock used as SPI5 clock source */
781 #define LL_RCC_SPI5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_1 | RCC_CCIPR3_SPI5SEL_0) /*!< HSI clock used as SPI5 clock source */
782 #define LL_RCC_SPI5_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2) /*!< CSI clock used as SPI5 clock source */
783 #define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, RCC_CCIPR3_SPI5SEL_2 | RCC_CCIPR3_SPI5SEL_0) /*!< HSE clock used as SPI5 clock source */
784 #endif /* SPI5 */
785
786 #if defined(SPI6)
787 #define LL_RCC_SPI6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000U) /*!< PCLK2 clock used as SPI6 clock source */
788 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_0) /*!< PLL2 Q clock used as SPI6 clock source */
789 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1) /*!< PLL3 Q clock used as SPI6 clock source */
790 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_1 | RCC_CCIPR3_SPI6SEL_0) /*!< HSI clock used as SPI6 clock source */
791 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2) /*!< CSI clock used as SPI6 clock source */
792 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, RCC_CCIPR3_SPI6SEL_2 | RCC_CCIPR3_SPI6SEL_0) /*!< HSE clock used as SPI6 clock source */
793 #endif /* SPI6 */
794 /**
795 * @}
796 */
797
798 /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
799 * @{
800 */
801 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM1 clock source */
802 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0) /*!< PLL2 P clock used as LPTIM1 clock source */
803 #if defined(RCC_CR_PLL3ON)
804 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1) /*!< PLL3 R clock used as LPTIM1 clock source */
805 #endif /* PLL3 */
806 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_1) /*!< LSE clock used as LPTIM1 clock source */
807 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2) /*!< LSI clock used as LPTIM1 clock source */
808 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0 | RCC_CCIPR2_LPTIM1SEL_2) /*!< CLKP clock used as LPTIM1 clock source */
809
810 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000U) /*!< PCLK1 clock used as LPTIM2 clock source */
811 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0) /*!< PLL2 P clock used as LPTIM2 clock source */
812 #if defined(RCC_CR_PLL3ON)
813 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_1) /*!< PLL3 R clock used as LPTIM2 clock source */
814 #endif /* PLL3 */
815 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_1) /*!< LSE clock used as LPTIM2 clock source */
816 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_2) /*!< LSI clock used as LPTIM2 clock source */
817 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, RCC_CCIPR2_LPTIM2SEL_0 | RCC_CCIPR2_LPTIM2SEL_2) /*!< CLKP clock used as LPTIM2 clock source */
818
819 #if defined(LPTIM3)
820 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM3 clock source */
821 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0) /*!< PLL2 P clock used as LPTIM3 clock source */
822 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_1) /*!< PLL3 R clock used as LPTIM3 clock source */
823 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_1) /*!< LSE clock used as LPTIM3 clock source */
824 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_2) /*!< LSI clock used as LPTIM3 clock source */
825 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, RCC_CCIPR2_LPTIM3SEL_0 | RCC_CCIPR2_LPTIM3SEL_2) /*!< CLKP clock used as LPTIM3 clock source */
826 #endif /* LPTIM3 */
827
828 #if defined(LPTIM4)
829 #define LL_RCC_LPTIM4_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM4 clock source */
830 #define LL_RCC_LPTIM4_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0) /*!< PLL2 P clock used as LPTIM4 clock source */
831 #define LL_RCC_LPTIM4_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_1) /*!< PLL3 R clock used as LPTIM4 clock source */
832 #define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_1) /*!< LSE clock used as LPTIM4 clock source */
833 #define LL_RCC_LPTIM4_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_2) /*!< LSI clock used as LPTIM4 clock source */
834 #define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, RCC_CCIPR2_LPTIM4SEL_0 | RCC_CCIPR2_LPTIM4SEL_2) /*!< CLKP clock used as LPTIM4 clock source */
835 #endif /* LPTIM4 */
836
837 #if defined(LPTIM5)
838 #define LL_RCC_LPTIM5_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM5 clock source */
839 #define LL_RCC_LPTIM5_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0) /*!< PLL2 P clock used as LPTIM5 clock source */
840 #define LL_RCC_LPTIM5_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_1) /*!< PLL3 R clock used as LPTIM5 clock source */
841 #define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_1) /*!< LSE clock used as LPTIM5 clock source */
842 #define LL_RCC_LPTIM5_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_2) /*!< LSI clock used as LPTIM5 clock source */
843 #define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, RCC_CCIPR2_LPTIM5SEL_0 | RCC_CCIPR2_LPTIM5SEL_2) /*!< CLKP clock used as LPTIM5 clock source */
844 #endif /* LPTIM5 */
845
846 #if defined(LPTIM6)
847 #define LL_RCC_LPTIM6_CLKSOURCE_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000U) /*!< PCLK3 clock used as LPTIM6 clock source */
848 #define LL_RCC_LPTIM6_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0) /*!< PLL2 P clock used as LPTIM6 clock source */
849 #define LL_RCC_LPTIM6_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_1) /*!< PLL3 R clock used as LPTIM6 clock source */
850 #define LL_RCC_LPTIM6_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_1) /*!< LSE clock used as LPTIM6 clock source */
851 #define LL_RCC_LPTIM6_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_2) /*!< LSI clock used as LPTIM6 clock source */
852 #define LL_RCC_LPTIM6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, RCC_CCIPR2_LPTIM6SEL_0 | RCC_CCIPR2_LPTIM6SEL_2) /*!< CLKP clock used as LPTIM6 clock source */
853 #endif /* LPTIM6 */
854 /**
855 * @}
856 */
857
858 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
859 * @{
860 */
861 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */
862 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q RCC_CCIPR5_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */
863 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q RCC_CCIPR5_FDCANSEL_1 /*!< PLL2 Q clock used as FDCAN kernel clock source */
864 #define LL_RCC_FDCAN_CLKSOURCE_NONE RCC_CCIPR5_FDCANSEL /*!< NO clock used as FDCAN kernel clock source */
865 /**
866 * @}
867 */
868
869 #if defined(SAI1)
870 /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
871 * @{
872 */
873 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI1 clock source */
874 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_0) /*!< PLL2 P clock used as SAI1 clock source */
875 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1) /*!< PLL3 P clock used as SAI1 clock source */
876 #define LL_RCC_SAI1_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_1 | RCC_CCIPR5_SAI1SEL_0) /*!< External input clock used as SAI1 clock source */
877 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, RCC_CCIPR5_SAI1SEL_2) /*!< CLKP clock used as SAI1 clock source */
878
879 #define LL_RCC_SAI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000U) /*!< PLL1 Q clock used as SAI2 clock source */
880 #define LL_RCC_SAI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_0) /*!< PLL2 P clock used as SAI2 clock source */
881 #define LL_RCC_SAI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1) /*!< PLL3 P clock used as SAI2 clock source */
882 #define LL_RCC_SAI2_CLKSOURCE_PIN LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_1 | RCC_CCIPR5_SAI2SEL_0) /*!< External input clock used as SAI2 clock source */
883 #define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, RCC_CCIPR5_SAI2SEL_2) /*!< CLKP clock used as SAI2 clock source */
884 /**
885 * @}
886 */
887 #endif /* SAI1 */
888
889 #if defined(SDMMC1)
890 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMCx kernel clock source selection
891 * @{
892 */
893 #define LL_RCC_SDMMC1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC1 clock source */
894 #define LL_RCC_SDMMC1_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, RCC_CCIPR4_SDMMC1SEL) /*!< PLL2 R used as SDMMC1 clock source */
895 #if defined(SDMMC2)
896 #define LL_RCC_SDMMC2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000U) /*!< PLL1 Q used as SDMMC2 clock source */
897 #define LL_RCC_SDMMC2_CLKSOURCE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, RCC_CCIPR4_SDMMC2SEL) /*!< PLL2 R used as SDMMC2 clock source */
898 #endif /*SDMMC2*/
899 /**
900 * @}
901 */
902 #endif /* SDMMC1 */
903
904 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
905 * @{
906 */
907 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
908 #define LL_RCC_RNG_CLKSOURCE_PLL1Q RCC_CCIPR5_RNGSEL_0 /*!< PLL1 Q clock used as RNG clock source */
909 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR5_RNGSEL_1 /*!< LSE clock used as RNG clock source */
910 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR5_RNGSEL /*!< LSI clock used as RNG clock source */
911 /**
912 * @}
913 */
914
915 #if defined(USB_DRD_FS)
916 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
917 * @{
918 */
919 #define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /*!< No clock used as USB clock source */
920 #define LL_RCC_USB_CLKSOURCE_PLL1Q RCC_CCIPR4_USBSEL_0 /*!< PLL1 Q clock used as USB clock source */
921 #if defined(RCC_CR_PLL3ON)
922 #define LL_RCC_USB_CLKSOURCE_PLL3Q RCC_CCIPR4_USBSEL_1 /*!< PLL3 Q clock used as USB clock source */
923 #else
924 #define LL_RCC_USB_CLKSOURCE_PLL2Q RCC_CCIPR4_USBSEL_1 /*!< PLL2 Q clock used as USB clock source */
925 #endif /* PLL3 */
926 #define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR4_USBSEL /*!< HSI48 clock used as USB clock source */
927 /**
928 * @}
929 */
930 #endif /* USB_DRD_FS */
931
932 /** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCDAC clock source selection
933 * @{
934 */
935 #define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as ADCDAC clock source */
936 #define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR5_ADCDACSEL_0 /*!< SYSCLK clock used as ADCDAC clock source */
937 #define LL_RCC_ADCDAC_CLKSOURCE_PLL2R RCC_CCIPR5_ADCDACSEL_1 /*!< PLL2 R clock used as ADCDAC clock source */
938 #define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_1) /*!< HSE clock used as ADCDAC clock source */
939 #define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR5_ADCDACSEL_2 /*!< HSI clock used as ADCDAC clock source */
940 #define LL_RCC_ADCDAC_CLKSOURCE_CSI (RCC_CCIPR5_ADCDACSEL_0 | RCC_CCIPR5_ADCDACSEL_2) /*!< CSI clock used as ADCDAC clock source */
941 /**
942 * @}
943 */
944
945 /** @defgroup RCC_LL_EC_DAC_CLKSOURCE Peripheral DAC low-power clock source selection
946 * @{
947 */
948 #define LL_RCC_DAC_LP_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC low-power clock */
949 #define LL_RCC_DAC_LP_CLKSOURCE_LSI RCC_CCIPR5_DACSEL /*!< LSI clock used as DAC low-power clock */
950 /**
951 * @}
952 */
953
954 #if defined(CEC)
955 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
956 * @{
957 */
958 #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as CEC clock */
959 #define LL_RCC_CEC_CLKSOURCE_LSI RCC_CCIPR5_CECSEL_0 /*!< LSI clock used as CEC clock */
960 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 RCC_CCIPR5_CECSEL_1 /*!< CSI clock divied by 122 used as CEC clock */
961 #define LL_RCC_CEC_CLKSOURCE_NONE RCC_CCIPR5_CECSEL /*!< NO clock used as CEC clock source */
962 /**
963 * @}
964 */
965 #endif /* CEC */
966
967 #if defined(OCTOSPI1)
968 /** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
969 * @{
970 */
971 #define LL_RCC_OSPI_CLKSOURCE_HCLK 0x00000000U /*!< AHB clock used as OctoSPI kernel clock source */
972 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q RCC_CCIPR4_OCTOSPISEL_0 /*!< PLL1 Q clock used as OctoSPI kernel clock source */
973 #define LL_RCC_OSPI_CLKSOURCE_PLL2R RCC_CCIPR4_OCTOSPISEL_1 /*!< PLL2 R clock used as OctoSPI kernel clock source */
974 #define LL_RCC_OSPI_CLKSOURCE_CLKP RCC_CCIPR4_OCTOSPISEL /*!< CLKP clock used as OctoSPI clock source */
975 /**
976 * @}
977 */
978 #endif /* OCTOSPI1 */
979
980 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
981 * @{
982 */
983 #define LL_RCC_CLKP_CLKSOURCE_HSI 0x00000000U /*!< HSI clock used as CLKP clock source */
984 #define LL_RCC_CLKP_CLKSOURCE_CSI RCC_CCIPR5_CKERPSEL_0 /*!< CSI clock used as CLKP clock source */
985 #define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR5_CKERPSEL_1 /*!< HSE clock used as CLKP clock source */
986 #define LL_RCC_CLKP_CLKSOURCE_NONE RCC_CCIPR5_CKERPSEL /*!< No clock selected as CLKP clock source */
987 /**
988 * @}
989 */
990
991 /** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
992 * @{
993 */
994 #define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART1SEL, RCC_CCIPR1_USART1SEL_Pos, 0x00000000U) /*!< USART1 Clock source selection */
995 #define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x00000000U) /*!< USART2 Clock source selection */
996 #define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART3SEL, RCC_CCIPR1_USART3SEL_Pos, 0x00000000U) /*!< USART3 Clock source selection */
997 #if defined(USART6)
998 #define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART6SEL, RCC_CCIPR1_USART6SEL_Pos, 0x00000000U) /*!< USART6 Clock source selection */
999 #endif /* USART6 */
1000 #if defined(USART10)
1001 #define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART10SEL, RCC_CCIPR1_USART10SEL_Pos, 0x00000000U) /*!< USART10 Clock source selection */
1002 #endif /* USART10 */
1003 #if defined(USART11)
1004 #define LL_RCC_USART11_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_USART11SEL, RCC_CCIPR2_USART11SEL_Pos, 0x00000000U) /*!< USART11 Clock source selection */
1005 #endif /* USART11 */
1006 /**
1007 * @}
1008 */
1009
1010 #if defined(UART4)
1011 /** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source
1012 * @{
1013 */
1014 #define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART4SEL, RCC_CCIPR1_UART4SEL_Pos, 0x00000000U) /*!< UART4 Clock source selection */
1015 #define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART5SEL, RCC_CCIPR1_UART5SEL_Pos, 0x00000000U) /*!< UART5 Clock source selection */
1016 #define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART7SEL, RCC_CCIPR1_UART7SEL_Pos, 0x00000000U) /*!< UART7 Clock source selection */
1017 #define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART8SEL, RCC_CCIPR1_UART8SEL_Pos, 0x00000000U) /*!< UART8 Clock source selection */
1018 #define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_UART9SEL, RCC_CCIPR1_UART9SEL_Pos, 0x00000000U) /*!< UART9 Clock source selection */
1019 #define LL_RCC_UART12_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART12SEL, RCC_CCIPR2_UART12SEL_Pos, 0x00000000U) /*!< UART12 Clock source selection */
1020 /**
1021 * @}
1022 */
1023 #endif /*UART4*/
1024
1025 /** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
1026 * @{
1027 */
1028 #define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x00000000U) /*!< SPI1 Clock source selection */
1029 #define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI2SEL, RCC_CCIPR3_SPI2SEL_Pos, 0x00000000U) /*!< SPI2 Clock source selection */
1030 #define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI3SEL, RCC_CCIPR3_SPI3SEL_Pos, 0x00000000U) /*!< SPI3 Clock source selection */
1031 #if defined(SPI4)
1032 #define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI4SEL, RCC_CCIPR3_SPI4SEL_Pos, 0x00000000U) /*!< SPI4 Clock source selection */
1033 #endif /* SPI4 */
1034 #if defined(SPI5)
1035 #define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI5SEL, RCC_CCIPR3_SPI5SEL_Pos, 0x00000000U) /*!< SPI5 Clock source selection */
1036 #endif /* SPI5 */
1037 #if defined(SPI6)
1038 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI6SEL, RCC_CCIPR3_SPI6SEL_Pos, 0x00000000U) /*!< SPI6 Clock source selection */
1039 #endif /* SPI6 */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
1045 * @{
1046 */
1047 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
1048 /**
1049 * @}
1050 */
1051
1052 /** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
1053 * @{
1054 */
1055 #define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0x00000000U) /*!< I2C1 Clock source selection */
1056 #define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0x00000000U) /*!< I2C2 Clock source selection */
1057 #if defined(I2C3)
1058 #define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0x00000000U) /*!< I2C3 Clock source selection */
1059 #endif /* I2C3 */
1060 #if defined(I2C4)
1061 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0x00000000U) /*!< I2C4 Clock source selection */
1062 #endif /* I2C4 */
1063 /**
1064 * @}
1065 */
1066
1067 /** @defgroup RCC_LL_EC_I3C Peripheral I3Cx get clock source
1068 * @{
1069 */
1070 #define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x00000000U) /*!< I3C1 Clock source selection */
1071 #if defined(I3C2)
1072 #define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0x00000000U) /*!< I3C2 Clock source selection */
1073 #endif /* I3C2 */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
1079 * @{
1080 */
1081 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x00000000U) /*!< LPTIM1 Clock source selection */
1082 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM2SEL, RCC_CCIPR2_LPTIM2SEL_Pos, 0x00000000U) /*!< LPTIM2 Clock source selection */
1083 #if defined(LPTIM3)
1084 #define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM3SEL, RCC_CCIPR2_LPTIM3SEL_Pos, 0x00000000U) /*!< LPTIM3 Clock source selection */
1085 #endif /* LPTIM3 */
1086 #if defined(LPTIM4)
1087 #define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM4SEL, RCC_CCIPR2_LPTIM4SEL_Pos, 0x00000000U) /*!< LPTIM4 Clock source selection */
1088 #endif /* LPTIM4 */
1089 #if defined(LPTIM5)
1090 #define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM5SEL, RCC_CCIPR2_LPTIM5SEL_Pos, 0x00000000U) /*!< LPTIM5 Clock source selection */
1091 #endif /* LPTIM5 */
1092 #if defined(LPTIM6)
1093 #define LL_RCC_LPTIM6_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM6SEL, RCC_CCIPR2_LPTIM6SEL_Pos, 0x00000000U) /*!< LPTIM6 Clock source selection */
1094 #endif /* LPTIM6 */
1095 /**
1096 * @}
1097 */
1098
1099 #if defined(SAI1)
1100 /** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
1101 * @{
1102 */
1103 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI1SEL, RCC_CCIPR5_SAI1SEL_Pos, 0x00000000U) /*!< SAI1 Clock source selection */
1104 #define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR5_OFFSET, RCC_CCIPR5_SAI2SEL, RCC_CCIPR5_SAI2SEL_Pos, 0x00000000U) /*!< SAI2 Clock source selection */
1105 /**
1106 * @}
1107 */
1108 #endif /* SAI1 */
1109
1110 #if defined(SDMMC1)
1111 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
1112 * @{
1113 */
1114 #define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC1SEL, RCC_CCIPR4_SDMMC1SEL_Pos, 0x00000000U) /*!< SDMMC1 Kernel Clock source selection */
1115 #if defined(SDMMC2)
1116 #define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SDMMC2SEL, RCC_CCIPR4_SDMMC2SEL_Pos, 0x00000000U) /*!< SDMMC2 Kernel Clock source selection */
1117 #endif /*SDMMC2*/
1118 /**
1119 * @}
1120 */
1121 #endif /* SDMMC1 */
1122
1123 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
1124 * @{
1125 */
1126 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR5_RNGSEL /*!< RNG Clock source selection */
1127 /**
1128 * @}
1129 */
1130
1131 #if defined(USB_DRD_FS)
1132 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
1133 * @{
1134 */
1135 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR4_USBSEL /*!< USB Clock source selection */
1136 /**
1137 * @}
1138 */
1139 #endif /* USB_DRD_FS */
1140
1141 /** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source
1142 * @{
1143 */
1144 #define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR5_ADCDACSEL /*!< ADCDACs Clock source selection */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup RCC_LL_EC_DAC Peripheral DAC get low-power clock source
1150 * @{
1151 */
1152 #define LL_RCC_DAC_LP_CLKSOURCE RCC_CCIPR5_DACSEL /*!< DAC low-power Clock source selection */
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
1158 * @{
1159 */
1160 #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR5_CECSEL
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source
1166 * @{
1167 */
1168 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR5_FDCANSEL /*!< FDCAN kernel Clock source selection */
1169 /**
1170 * @}
1171 */
1172
1173 /** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
1174 * @{
1175 */
1176 #define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR4_OCTOSPISEL /*!< OctoSPI Clock source selection */
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1182 * @{
1183 */
1184 #define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR5_CKERPSEL /*!< CLKP Clock source selection */
1185 /**
1186 * @}
1187 */
1188
1189 /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
1190 * @{
1191 */
1192 #define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */
1193 #define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 /*!< HSI clock selected as main PLL1 entry clock source */
1194 #define LL_RCC_PLL1SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 /*!< CSI clock selected as main PLL1 entry clock source */
1195 #define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
1201 * @{
1202 */
1203 #define LL_RCC_PLLINPUTRANGE_1_2 0x00000000U /*!< VCO input range: 1 to 2 MHz */
1204 #define LL_RCC_PLLINPUTRANGE_2_4 0x00000001U /*!< VCO input range: 2 to 4 MHz */
1205 #define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */
1206 #define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup RCC_LL_EC_PLLOUTPUTRANGE All PLLs output ranges
1212 * @{
1213 */
1214 #define LL_RCC_PLLVCORANGE_WIDE 0x00000000U /*!< VCO output range: 192 to 836 MHz */
1215 #define LL_RCC_PLLVCORANGE_MEDIUM 0x00000001U /*!< VCO output range: 150 to 420 MHz */
1216
1217 /**
1218 * @}
1219 */
1220
1221 /** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source
1222 * @{
1223 */
1224 #define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */
1225 #define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_0 /*!< HSI clock selected as main PLL2 entry clock source */
1226 #define LL_RCC_PLL2SOURCE_CSI RCC_PLL2CFGR_PLL2SRC_1 /*!< CSI clock selected as main PLL2 entry clock source */
1227 #define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source
1233 * @{
1234 */
1235 #define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */
1236 #define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_0 /*!< HSI clock selected as main PLL3 entry clock source */
1237 #define LL_RCC_PLL3SOURCE_CSI RCC_PLL3CFGR_PLL3SRC_1 /*!< CSI clock selected as main PLL3 entry clock source */
1238 #define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */
1239 /**
1240 * @}
1241 */
1242
1243 #if defined(RCC_SECCFGR_HSISEC)
1244 /** @defgroup RCC_LL_EC_SECURE_ATTRIBUTES Secure attributes
1245 * @note Only available when system implements security (TZEN=1)
1246 * @{
1247 */
1248 #define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
1249 #define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
1250
1251 #define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */
1252 #define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
1253 #define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */
1254 #define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
1255 #define LL_RCC_CSI_SEC RCC_SECCFGR_CSISEC /*!< CSI clock configuration secure-only access */
1256 #define LL_RCC_CSI_NSEC 0U /*!< CSI clock configuration secure/non-secure access */
1257 #define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */
1258 #define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
1259 #define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */
1260 #define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
1261 #define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */
1262 #define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
1263 #define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */
1264 #define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
1265 #define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< main PLL clock configuration secure-only access */
1266 #define LL_RCC_PLL1_NSEC 0U /*!< main PLL clock configuration secure/non-secure access */
1267 #define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration secure-only access */
1268 #define LL_RCC_PLL2_NSEC 0U /*!< PLL2 clock configuration secure/non-secure access */
1269 #define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration secure-only access */
1270 #define LL_RCC_PLL3_NSEC 0U /*!< PLL3 clock configuration secure/non-secure access */
1271 #define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration secure-only access */
1272 #define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */
1273 #define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-ony access */
1274 #define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */
1275 #define LL_RCC_CKPERSEL_SEC RCC_SECCFGR_CKPERSELSEC /*!< Periph clock configuration secure-ony access */
1276 #define LL_RCC_CKPERSEL_NSEC 0U /*!< Periph clock configuration secure/non-secure access */
1277 /**
1278 * @}
1279 */
1280 #endif /* RCC_SECCFGR_HSISEC */
1281
1282 /**
1283 * @}
1284 */
1285
1286 /* Exported macro ------------------------------------------------------------*/
1287 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1288 * @{
1289 */
1290
1291 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1292 * @{
1293 */
1294
1295 /**
1296 * @brief Write a value in RCC register
1297 * @param __REG__ Register to be written
1298 * @param __VALUE__ Value to be written in the register
1299 * @retval None
1300 */
1301 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1302
1303 /**
1304 * @brief Read a value in RCC register
1305 * @param __REG__ Register to be read
1306 * @retval Register value
1307 */
1308 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1314 * @{
1315 */
1316
1317 /**
1318 * @brief Helper macro to calculate the PLL1P clock frequency
1319 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1320 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
1321 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1322 * @param __PLL1M__ parameter can be a value between 1 and 63
1323 * @param __PLL1N__ parameter can be a value between 4 and 512
1324 * @param __PLL1P__ parameter can be a value between 1 and 128 (odd values not allowed)
1325 * @retval PLL1P clock frequency (in Hz)
1326 */
1327
1328 #define __LL_RCC_CALC_PLL1CLK_P_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) \
1329 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
1330
1331 /**
1332 * @brief Helper macro to calculate the PLL1Q clock frequency
1333 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1334 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
1335 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1336 * @param __PLL1M__ parameter can be a value between 1 and 63
1337 * @param __PLL1N__ parameter can be a value between 4 and 512
1338 * @param __PLL1Q__ parameter can be a value between 2 and 128
1339 * @retval PLL1Q clock frequency (in Hz)
1340 */
1341 #define __LL_RCC_CALC_PLL1CLK_Q_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) \
1342 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
1343
1344 /**
1345 * @brief Helper macro to calculate the PLL1R clock frequency
1346 * @note ex: @ref __LL_RCC_CALC_PLL1CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetM (),
1347 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetN ());
1348 * @param __INPUTFREQ__ PLL1 Input frequency (based on HSI/HSE/CSI)
1349 * @param __PLL1M__ parameter can be a value between 1 and 63
1350 * @param __PLL1N__ parameter can be a value between 4 and 512
1351 * @param __PLL1R__ parameter can be a value between 1 and 128
1352 * @retval PLL1R clock frequency (in Hz)
1353 */
1354
1355 #define __LL_RCC_CALC_PLL1CLK_R_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) \
1356 ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__))
1357
1358 /**
1359 * @brief Helper macro to calculate the PLL2P clock frequency
1360 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_P_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetM (),
1361 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ());
1362 * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI)
1363 * @param __PLL2M__ parameter can be a value between 1 and 63
1364 * @param __PLL2N__ parameter can be a value between 4 and 512
1365 * @param __PLL2P__ parameter can be a value between 2 and 128
1366 * @retval PLL2P clock frequency (in Hz)
1367 */
1368 #define __LL_RCC_CALC_PLL2CLK_P_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) \
1369 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__))
1370
1371 /**
1372 * @brief Helper macro to calculate the PLL2Q clock frequency
1373 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (),
1374 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ());
1375 * @param __INPUTFREQ__ PLL Input frequency (based on HSI/HSE/CSI)
1376 * @param __PLL2M__ parameter can be a value between 1 and 63
1377 * @param __PLL2N__ parameter can be a value between 4 and 512
1378 * @param __PLL2Q__ parameter can be a value between 1 and 128
1379 * @retval PLL2Q clock frequency (in Hz)
1380 */
1381 #define __LL_RCC_CALC_PLL2CLK_Q_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) \
1382 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__))
1383
1384 /**
1385 * @brief Helper macro to calculate the PLL2R clock frequency
1386 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetM (),
1387 * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ());
1388 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSI/HSE/CSI)
1389 * @param __PLL2M__ parameter can be a value between 1 and 63
1390 * @param __PLL2N__ parameter can be a value between 4 and 512
1391 * @param __PLL2R__ parameter can be a value between 1 and 128
1392 * @retval PLL2R clock frequency (in Hz)
1393 */
1394 #define __LL_RCC_CALC_PLL2CLK_R_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) \
1395 ((((__INPUTFREQ__) /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__))
1396
1397 /**
1398 * @brief Helper macro to calculate the PLL3P clock frequency
1399 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_P_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1400 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ());
1401 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1402 * @param __PLL3M__ parameter can be a value between 1 and 63
1403 * @param __PLL3N__ parameter can be a value between 4 and 512
1404 * @param __PLL3P__ parameter can be a value between 2 and 128
1405 * @retval PLL3P clock frequency (in Hz)
1406 */
1407 #define __LL_RCC_CALC_PLL3CLK_P_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__) \
1408 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__))
1409
1410 /**
1411 * @brief Helper macro to calculate the PLL3 frequency
1412 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_Q_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1413 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ());
1414 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1415 * @param __PLL3M__ parameter can be a value between 1 and 63
1416 * @param __PLL3N__ parameter can be a value between 4 and 512
1417 * @param __PLL3Q__ parameter can be a value between 1 and 128
1418 * @retval PLL3Q clock frequency (in Hz)
1419 */
1420 #define __LL_RCC_CALC_PLL3CLK_Q_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) \
1421 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__))
1422
1423 /**
1424 * @brief Helper macro to calculate the PLL3 frequency
1425 * @note ex: @ref __LL_RCC_CALC_PLL3CLK_R_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetM (),
1426 * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetR ());
1427 * @param __INPUTFREQ__ PLL3 Input frequency (based on HSI/HSE/CSI)
1428 * @param __PLL3M__ parameter can be a value between 1 and 63
1429 * @param __PLL3N__ parameter can be a value between 4 and 512
1430 * @param __PLL3R__ parameter can be a value between 1 and 128
1431 * @retval PLL3R clock frequency (in Hz)
1432 */
1433 #define __LL_RCC_CALC_PLL3CLK_R_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) \
1434 ((((__INPUTFREQ__) /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__))
1435
1436 /**
1437 * @brief Helper macro to calculate the HCLK frequency
1438 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSI/HSE/CSI/PLLCLK)
1439 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1440 * @arg @ref LL_RCC_SYSCLK_DIV_1
1441 * @arg @ref LL_RCC_SYSCLK_DIV_2
1442 * @arg @ref LL_RCC_SYSCLK_DIV_4
1443 * @arg @ref LL_RCC_SYSCLK_DIV_8
1444 * @arg @ref LL_RCC_SYSCLK_DIV_16
1445 * @arg @ref LL_RCC_SYSCLK_DIV_64
1446 * @arg @ref LL_RCC_SYSCLK_DIV_128
1447 * @arg @ref LL_RCC_SYSCLK_DIV_256
1448 * @arg @ref LL_RCC_SYSCLK_DIV_512
1449 * @retval HCLK clock frequency (in Hz)
1450 */
1451 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \
1452 ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos])
1453
1454 /**
1455 * @brief Helper macro to calculate the PCLK1 frequency (APB1)
1456 * @param __HCLKFREQ__ HCLK frequency
1457 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1458 * @arg @ref LL_RCC_APB1_DIV_1
1459 * @arg @ref LL_RCC_APB1_DIV_2
1460 * @arg @ref LL_RCC_APB1_DIV_4
1461 * @arg @ref LL_RCC_APB1_DIV_8
1462 * @arg @ref LL_RCC_APB1_DIV_16
1463 * @retval PCLK1 clock frequency (in Hz)
1464 */
1465 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
1466 ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
1467
1468 /**
1469 * @brief Helper macro to calculate the PCLK2 frequency (APB2)
1470 * @param __HCLKFREQ__ HCLK frequency
1471 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1472 * @arg @ref LL_RCC_APB2_DIV_1
1473 * @arg @ref LL_RCC_APB2_DIV_2
1474 * @arg @ref LL_RCC_APB2_DIV_4
1475 * @arg @ref LL_RCC_APB2_DIV_8
1476 * @arg @ref LL_RCC_APB2_DIV_16
1477 * @retval PCLK2 clock frequency (in Hz)
1478 */
1479 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \
1480 ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos])
1481
1482
1483 /**
1484 * @brief Helper macro to calculate the PCLK3 frequency (APB3)
1485 * @param __HCLKFREQ__ HCLK frequency
1486 * @param __APB3PRESCALER__ This parameter can be one of the following values:
1487 * @arg @ref LL_RCC_APB3_DIV_1
1488 * @arg @ref LL_RCC_APB3_DIV_2
1489 * @arg @ref LL_RCC_APB3_DIV_4
1490 * @arg @ref LL_RCC_APB3_DIV_8
1491 * @arg @ref LL_RCC_APB3_DIV_16
1492 * @retval PCLK3 clock frequency (in Hz)
1493 */
1494 #define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) \
1495 ((__HCLKFREQ__) >> APBPrescTable[(__APB3PRESCALER__) >> RCC_CFGR2_PPRE3_Pos])
1496
1497 /**
1498 * @brief Helper macro to calculate the HSI frequency
1499 * @param __HSIDIV__ This parameter can be one of the following values:
1500 * @arg @ref LL_RCC_HSI_DIV_1
1501 * @arg @ref LL_RCC_HSI_DIV_2
1502 * @arg @ref LL_RCC_HSI_DIV_4
1503 * @arg @ref LL_RCC_HSI_DIV_8
1504 * @retval HSI clock frequency (in Hz)
1505 */
1506 #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE >> ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))
1507
1508 /**
1509 * @}
1510 */
1511
1512 /**
1513 * @}
1514 */
1515
1516 /* Exported functions --------------------------------------------------------*/
1517 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1518 * @{
1519 */
1520
1521 /** @defgroup RCC_LL_EF_HSE HSE
1522 * @{
1523 */
1524
1525 /**
1526 * @brief Enable the HSE Clock Security System.
1527 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
1528 * @retval None
1529 */
LL_RCC_HSE_EnableCSS(void)1530 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1531 {
1532 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
1533 }
1534
1535 /**
1536 * @brief Enable HSE external oscillator (HSE Bypass)
1537 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1538 * @retval None
1539 */
LL_RCC_HSE_EnableBypass(void)1540 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1541 {
1542 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1543 }
1544
1545 /**
1546 * @brief Disable HSE external oscillator (HSE Bypass)
1547 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1548 * @retval None
1549 */
LL_RCC_HSE_DisableBypass(void)1550 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1551 {
1552 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1553 }
1554
1555 /**
1556 * @brief Enable HSE crystal oscillator (HSE ON)
1557 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1558 * @retval None
1559 */
LL_RCC_HSE_Enable(void)1560 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1561 {
1562 SET_BIT(RCC->CR, RCC_CR_HSEON);
1563 }
1564
1565 /**
1566 * @brief Disable HSE crystal oscillator (HSE ON)
1567 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1568 * @retval None
1569 */
LL_RCC_HSE_Disable(void)1570 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1571 {
1572 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1573 }
1574
1575 /**
1576 * @brief Check if HSE oscillator Ready
1577 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1578 * @retval State of bit (1 or 0).
1579 */
LL_RCC_HSE_IsReady(void)1580 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1581 {
1582 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @brief Set external HSE clock type in Bypass mode
1587 * @note This bit can be written only if the HSE oscillator is disabled
1588 * @rmtoll CR HSEEXT LL_RCC_HSE_SetExternalClockType
1589 * @param HSEClockMode This parameter can be one of the following values:
1590 * @arg @ref LL_RCC_HSE_ANALOG_TYPE
1591 * @arg @ref LL_RCC_HSE_DIGITAL_TYPE
1592 * @retval None
1593 */
LL_RCC_HSE_SetExternalClockType(uint32_t HSEClockMode)1594 __STATIC_INLINE void LL_RCC_HSE_SetExternalClockType(uint32_t HSEClockMode)
1595 {
1596 MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEClockMode);
1597 }
1598
1599 /**
1600 * @brief Get external HSE clock type in Bypass mode
1601 * @rmtoll CR HSEEXT LL_RCC_HSE_GetExternalClockType
1602 * @retval Returned value can be one of the following values:
1603 * @arg @ref LL_RCC_HSE_ANALOG_TYPE
1604 * @arg @ref LL_RCC_HSE_DIGITAL_TYPE
1605 */
LL_RCC_HSE_GetExternalClockType(void)1606 __STATIC_INLINE uint32_t LL_RCC_HSE_GetExternalClockType(void)
1607 {
1608 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT));
1609 }
1610
1611 /**
1612 * @}
1613 */
1614
1615 /** @defgroup RCC_LL_EF_HSI HSI
1616 * @{
1617 */
1618
1619 /**
1620 * @brief Enable HSI oscillator
1621 * @rmtoll CR HSION LL_RCC_HSI_Enable
1622 * @retval None
1623 */
LL_RCC_HSI_Enable(void)1624 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1625 {
1626 SET_BIT(RCC->CR, RCC_CR_HSION);
1627 }
1628
1629 /**
1630 * @brief Disable HSI oscillator
1631 * @rmtoll CR HSION LL_RCC_HSI_Disable
1632 * @retval None
1633 */
LL_RCC_HSI_Disable(void)1634 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1635 {
1636 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1637 }
1638
1639 /**
1640 * @brief Check if HSI clock is ready
1641 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1642 * @retval State of bit (1 or 0).
1643 */
LL_RCC_HSI_IsReady(void)1644 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1645 {
1646 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Enable HSI even in stop mode for some peripherals kernel
1651 * @note HSI oscillator is forced ON even in Stop mode
1652 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1653 * @retval None
1654 */
LL_RCC_HSI_EnableInStopMode(void)1655 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1656 {
1657 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1658 }
1659
1660 /**
1661 * @brief Disable HSI in stop mode for some peripherals kernel
1662 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1663 * @retval None
1664 */
LL_RCC_HSI_DisableInStopMode(void)1665 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1666 {
1667 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1668 }
1669
1670 /**
1671 * @brief Check if HSI is enabled in stop mode
1672 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1673 * @retval State of bit (1 or 0).
1674 */
LL_RCC_HSI_IsEnabledInStopMode(void)1675 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1676 {
1677 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
1678 }
1679
1680 /**
1681 * @brief Check if HSI new divider applied and ready
1682 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1683 * @retval State of bit (1 or 0).
1684 */
LL_RCC_HSI_IsDividerReady(void)1685 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1686 {
1687 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Set HSI divider
1692 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1693 * @param Divider This parameter can be one of the following values:
1694 * @arg @ref LL_RCC_HSI_DIV_1
1695 * @arg @ref LL_RCC_HSI_DIV_2
1696 * @arg @ref LL_RCC_HSI_DIV_4
1697 * @arg @ref LL_RCC_HSI_DIV_8
1698 * @retval None.
1699 */
LL_RCC_HSI_SetDivider(uint32_t Divider)1700 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1701 {
1702 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1703 }
1704
1705 /**
1706 * @brief Get HSI divider
1707 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1708 * @retval can be one of the following values:
1709 * @arg @ref LL_RCC_HSI_DIV_1
1710 * @arg @ref LL_RCC_HSI_DIV_2
1711 * @arg @ref LL_RCC_HSI_DIV_4
1712 * @arg @ref LL_RCC_HSI_DIV_8
1713 */
LL_RCC_HSI_GetDivider(void)1714 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1715 {
1716 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1717 }
1718
1719 /**
1720 * @brief Get HSI Calibration value
1721 * @note When HSITRIM is written, HSICAL is updated with the sum of
1722 * HSITRIM and the factory trim value
1723 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1724 * @retval A value between 0 and 4095 (0xFFF)
1725 */
LL_RCC_HSI_GetCalibration(void)1726 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1727 {
1728 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1729 }
1730
1731 /**
1732 * @brief Set HSI Calibration trimming
1733 * @note user-programmable trimming value that is added to the HSICAL
1734 * @note Default value is 64, which, when added to the HSICAL value,
1735 * should trim the HSI to 64 MHz +/- 1 %
1736 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1737 * @param Value can be a value between Min_Data = 0 and Max_Data = 127 (0x7F)
1738 * @retval None
1739 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1740 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1741 {
1742 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1743 }
1744
1745 /**
1746 * @brief Get HSI Calibration trimming
1747 * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming
1748 * @retval A value between Min_Data = 0 and Max_Data = 127 (0x7F)
1749 */
LL_RCC_HSI_GetCalibTrimming(void)1750 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1751 {
1752 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1753 }
1754
1755 /**
1756 * @}
1757 */
1758
1759 /** @defgroup RCC_LL_EF_CSI CSI
1760 * @{
1761 */
1762
1763 /**
1764 * @brief Enable CSI oscillator
1765 * @rmtoll CR CSION LL_RCC_CSI_Enable
1766 * @retval None
1767 */
LL_RCC_CSI_Enable(void)1768 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1769 {
1770 SET_BIT(RCC->CR, RCC_CR_CSION);
1771 }
1772
1773 /**
1774 * @brief Disable CSI oscillator
1775 * @rmtoll CR CSION LL_RCC_CSI_Disable
1776 * @retval None
1777 */
LL_RCC_CSI_Disable(void)1778 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1779 {
1780 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1781 }
1782
1783 /**
1784 * @brief Check if CSI clock is ready
1785 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1786 * @retval State of bit (1 or 0).
1787 */
LL_RCC_CSI_IsReady(void)1788 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1789 {
1790 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Enable CSI oscillator in Stop mode for some peripherals kernel clock
1795 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableInStopMode
1796 * @retval None
1797 */
LL_RCC_CSI_EnableInStopMode(void)1798 __STATIC_INLINE void LL_RCC_CSI_EnableInStopMode(void)
1799 {
1800 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1801 }
1802
1803 /**
1804 * @brief Disable CSI oscillator in Stop mode for some peripherals kernel clock
1805 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableInStopMode
1806 * @retval None
1807 */
LL_RCC_CSI_DisableInStopMode(void)1808 __STATIC_INLINE void LL_RCC_CSI_DisableInStopMode(void)
1809 {
1810 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1811 }
1812
1813 /**
1814 * @brief Check if CSI is enabled in stop mode
1815 * @rmtoll CR CSIKERON LL_RCC_CSI_IsEnabledInStopMode
1816 * @retval State of bit (1 or 0).
1817 */
LL_RCC_CSI_IsEnabledInStopMode(void)1818 __STATIC_INLINE uint32_t LL_RCC_CSI_IsEnabledInStopMode(void)
1819 {
1820 return ((READ_BIT(RCC->CR, RCC_CR_CSIKERON) == RCC_CR_CSIKERON) ? 1UL : 0UL);
1821 }
1822
1823 /**
1824 * @brief Get CSI Calibration value
1825 * @note When CSITRIM is written, CSICAL is updated with the sum of
1826 * CSITRIM and the factory trim value
1827 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1828 * @retval A value between 0 and 255 (0xFF)
1829 */
LL_RCC_CSI_GetCalibration(void)1830 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1831 {
1832 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1833 }
1834
1835 /**
1836 * @brief Set CSI Calibration trimming
1837 * @note user-programmable trimming value that is added to the CSICAL
1838 * @note Default value is 16, which, when added to the CSICAL value,
1839 * should trim the CSI to 4 MHz +/- 1 %
1840 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1841 * @param Value can be a value between Min_Data = 0 and Max_Data = 63 (0x3F)
1842 * @retval None
1843 */
LL_RCC_CSI_SetCalibTrimming(uint32_t Value)1844 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1845 {
1846 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1847 }
1848
1849 /**
1850 * @brief Get CSI Calibration trimming
1851 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1852 * @retval A value between 0 and 63 (0x3F)
1853 */
LL_RCC_CSI_GetCalibTrimming(void)1854 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1855 {
1856 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1857 }
1858
1859 /**
1860 * @}
1861 */
1862
1863 /** @defgroup RCC_LL_EF_HSI48 HSI48
1864 * @{
1865 */
1866
1867 /**
1868 * @brief Enable HSI48
1869 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1870 * @retval None
1871 */
LL_RCC_HSI48_Enable(void)1872 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1873 {
1874 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1875 }
1876
1877 /**
1878 * @brief Disable HSI48
1879 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1880 * @retval None
1881 */
LL_RCC_HSI48_Disable(void)1882 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1883 {
1884 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1885 }
1886
1887 /**
1888 * @brief Check if HSI48 oscillator Ready
1889 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1890 * @retval State of bit (1 or 0).
1891 */
LL_RCC_HSI48_IsReady(void)1892 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1893 {
1894 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
1895 }
1896
1897 /**
1898 * @brief Get HSI48 Calibration value
1899 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1900 * @retval A value between 0 and 1023 (0x3FF)
1901 */
LL_RCC_HSI48_GetCalibration(void)1902 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1903 {
1904 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1905 }
1906
1907 /**
1908 * @}
1909 */
1910
1911 /** @defgroup RCC_LL_EF_LSE LSE
1912 * @{
1913 */
1914
1915 /**
1916 * @brief Enable Low Speed External (LSE) crystal.
1917 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1918 * @retval None
1919 */
LL_RCC_LSE_Enable(void)1920 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1921 {
1922 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1923 }
1924
1925 /**
1926 * @brief Disable Low Speed External (LSE) crystal.
1927 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1928 * @retval None
1929 */
LL_RCC_LSE_Disable(void)1930 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1931 {
1932 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1933 }
1934
1935 /**
1936 * @brief Check if LSE oscillator Ready
1937 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1938 * @retval State of bit (1 or 0).
1939 */
LL_RCC_LSE_IsReady(void)1940 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1941 {
1942 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
1943 }
1944
1945 /**
1946 * @brief Enable external clock source (LSE bypass).
1947 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1948 * @retval None
1949 */
LL_RCC_LSE_EnableBypass(void)1950 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1951 {
1952 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1953 }
1954
1955 /**
1956 * @brief Disable external clock source (LSE bypass).
1957 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1958 * @retval None
1959 */
LL_RCC_LSE_DisableBypass(void)1960 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1961 {
1962 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1963 }
1964
1965 /**
1966 * @brief Set external LSE clock type in Bypass mode
1967 * @note This bit can be written only if the LSE oscillator is disabled
1968 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SetExternalClockType
1969 * @param LSEClockMode This parameter can be one of the following values:
1970 * @arg @ref LL_RCC_LSE_ANALOG_TYPE
1971 * @arg @ref LL_RCC_LSE_DIGITAL_TYPE (*)
1972 * @retval None
1973 *
1974 * (*) not to be used if RTC is active
1975 */
LL_RCC_LSE_SetExternalClockType(uint32_t LSEClockMode)1976 __STATIC_INLINE void LL_RCC_LSE_SetExternalClockType(uint32_t LSEClockMode)
1977 {
1978 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEEXT, LSEClockMode);
1979 }
1980
1981 /**
1982 * @brief Get external LSE clock type in Bypass mode
1983 * @rmtoll BDCR LSEEXT LL_RCC_LSE_GetExternalClockType
1984 * @retval Returned value can be one of the following values:
1985 * @arg @ref LL_RCC_LSE_ANALOG_TYPE
1986 * @arg @ref LL_RCC_LSE_DIGITAL_TYPE
1987 */
LL_RCC_LSE_GetExternalClockType(void)1988 __STATIC_INLINE uint32_t LL_RCC_LSE_GetExternalClockType(void)
1989 {
1990 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEEXT));
1991 }
1992
1993 /**
1994 * @brief Set LSE oscillator drive capability
1995 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1996 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1997 * @param LSEDrive This parameter can be one of the following values:
1998 * @arg @ref LL_RCC_LSEDRIVE_LOW
1999 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2000 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2001 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2002 * @retval None
2003 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)2004 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2005 {
2006 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2007 }
2008
2009 /**
2010 * @brief Get LSE oscillator drive capability
2011 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2012 * @retval Returned value can be one of the following values:
2013 * @arg @ref LL_RCC_LSEDRIVE_LOW
2014 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2015 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2016 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2017 */
LL_RCC_LSE_GetDriveCapability(void)2018 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2019 {
2020 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2021 }
2022
2023 /**
2024 * @brief Enable Clock security system on LSE.
2025 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2026 * @retval None
2027 */
LL_RCC_LSE_EnableCSS(void)2028 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2029 {
2030 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2031 }
2032
2033 /**
2034 * @brief Disable Clock security system on LSE.
2035 * @note Clock security system can be disabled only after a LSE
2036 * failure detection. In that case it MUST be disabled by software.
2037 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
2038 * @retval None
2039 */
LL_RCC_LSE_DisableCSS(void)2040 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
2041 {
2042 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2043 }
2044
2045 /**
2046 * @brief Check if CSS on LSE failure Detection
2047 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
2048 * @retval State of bit (1 or 0).
2049 */
LL_RCC_LSE_IsCSSDetected(void)2050 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
2051 {
2052 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
2053 }
2054
2055 /**
2056 * @}
2057 */
2058
2059 /** @defgroup RCC_LL_EF_LSI LSI
2060 * @{
2061 */
2062
2063 /**
2064 * @brief Enable LSI Oscillator
2065 * @rmtoll BDCR LSION LL_RCC_LSI_Enable
2066 * @retval None
2067 */
LL_RCC_LSI_Enable(void)2068 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2069 {
2070 SET_BIT(RCC->BDCR, RCC_BDCR_LSION);
2071 }
2072
2073 /**
2074 * @brief Disable LSI Oscillator
2075 * @rmtoll BDCR LSION LL_RCC_LSI_Disable
2076 * @retval None
2077 */
LL_RCC_LSI_Disable(void)2078 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2079 {
2080 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION);
2081 }
2082
2083 /**
2084 * @brief Check if LSI is Ready
2085 * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady
2086 * @retval State of bit (1 or 0).
2087 */
LL_RCC_LSI_IsReady(void)2088 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2089 {
2090 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL);
2091 }
2092
2093
2094 /**
2095 * @}
2096 */
2097
2098
2099 /** @defgroup RCC_LL_EF_LSCO LSCO
2100 * @{
2101 */
2102
2103 /**
2104 * @brief Enable Low Speed Microcontroller Clock Output
2105 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
2106 * @retval None
2107 */
LL_RCC_LSCO_Enable(void)2108 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
2109 {
2110 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2111 }
2112
2113 /**
2114 * @brief Disable Low Speed Microcontroller Clock Output
2115 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
2116 * @retval None
2117 */
LL_RCC_LSCO_Disable(void)2118 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
2119 {
2120 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
2121 }
2122
2123 /**
2124 * @brief Configure Low Speed Microcontroller Clock Output selection
2125 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
2126 * @param Source This parameter can be one of the following values:
2127 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2128 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2129 * @retval None
2130 */
LL_RCC_LSCO_SetSource(uint32_t Source)2131 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
2132 {
2133 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
2134 }
2135
2136 /**
2137 * @brief Get Low Speed Microcontroller Clock Output selection
2138 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
2139 * @retval Returned value can be one of the following values:
2140 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
2141 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
2142 */
LL_RCC_LSCO_GetSource(void)2143 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
2144 {
2145 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
2146 }
2147
2148 /**
2149 * @}
2150 */
2151
2152 /** @defgroup RCC_LL_EF_System System
2153 * @{
2154 */
2155
2156 /**
2157 * @brief Configure the system clock source
2158 * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
2159 * @param Source This parameter can be one of the following values:
2160 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2161 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2162 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2163 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2164 * @retval None
2165 */
LL_RCC_SetSysClkSource(uint32_t Source)2166 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2167 {
2168 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
2169 }
2170
2171 /**
2172 * @brief Get the system clock source
2173 * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
2174 * @retval Returned value can be one of the following values:
2175 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2176 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2177 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2178 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2179 */
LL_RCC_GetSysClkSource(void)2180 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2181 {
2182 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
2183 }
2184
2185 /**
2186 * @brief Set AHB prescaler
2187 * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
2188 * @param Prescaler This parameter can be one of the following values:
2189 * @arg @ref LL_RCC_SYSCLK_DIV_1
2190 * @arg @ref LL_RCC_SYSCLK_DIV_2
2191 * @arg @ref LL_RCC_SYSCLK_DIV_4
2192 * @arg @ref LL_RCC_SYSCLK_DIV_8
2193 * @arg @ref LL_RCC_SYSCLK_DIV_16
2194 * @arg @ref LL_RCC_SYSCLK_DIV_64
2195 * @arg @ref LL_RCC_SYSCLK_DIV_128
2196 * @arg @ref LL_RCC_SYSCLK_DIV_256
2197 * @arg @ref LL_RCC_SYSCLK_DIV_512
2198 * @retval None
2199 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2200 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2201 {
2202 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
2203 }
2204
2205 /**
2206 * @brief Set Systick clock source
2207 * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource
2208 * @param SystickSource This parameter can be one of the following values:
2209 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
2210 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
2211 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
2212 * @retval None
2213 */
LL_RCC_SetSystickClockSource(uint32_t SystickSource)2214 __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
2215 {
2216 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, SystickSource);
2217 }
2218
2219 /**
2220 * @brief Set APB1 prescaler
2221 * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
2222 * @param Prescaler This parameter can be one of the following values:
2223 * @arg @ref LL_RCC_APB1_DIV_1
2224 * @arg @ref LL_RCC_APB1_DIV_2
2225 * @arg @ref LL_RCC_APB1_DIV_4
2226 * @arg @ref LL_RCC_APB1_DIV_8
2227 * @arg @ref LL_RCC_APB1_DIV_16
2228 * @retval None
2229 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2230 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2231 {
2232 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
2233 }
2234
2235 /**
2236 * @brief Set APB2 prescaler
2237 * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
2238 * @param Prescaler This parameter can be one of the following values:
2239 * @arg @ref LL_RCC_APB2_DIV_1
2240 * @arg @ref LL_RCC_APB2_DIV_2
2241 * @arg @ref LL_RCC_APB2_DIV_4
2242 * @arg @ref LL_RCC_APB2_DIV_8
2243 * @arg @ref LL_RCC_APB2_DIV_16
2244 * @retval None
2245 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2246 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2247 {
2248 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
2249 }
2250
2251 /**
2252 * @brief Set APB3 prescaler
2253 * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler
2254 * @param Prescaler This parameter can be one of the following values:
2255 * @arg @ref LL_RCC_APB3_DIV_1
2256 * @arg @ref LL_RCC_APB3_DIV_2
2257 * @arg @ref LL_RCC_APB3_DIV_4
2258 * @arg @ref LL_RCC_APB3_DIV_8
2259 * @arg @ref LL_RCC_APB3_DIV_16
2260 * @retval None
2261 */
LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)2262 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2263 {
2264 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE3, Prescaler);
2265 }
2266
2267 /**
2268 * @brief Get AHB prescaler
2269 * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
2270 * @retval Returned value can be one of the following values:
2271 * @arg @ref LL_RCC_SYSCLK_DIV_1
2272 * @arg @ref LL_RCC_SYSCLK_DIV_2
2273 * @arg @ref LL_RCC_SYSCLK_DIV_4
2274 * @arg @ref LL_RCC_SYSCLK_DIV_8
2275 * @arg @ref LL_RCC_SYSCLK_DIV_16
2276 * @arg @ref LL_RCC_SYSCLK_DIV_64
2277 * @arg @ref LL_RCC_SYSCLK_DIV_128
2278 * @arg @ref LL_RCC_SYSCLK_DIV_256
2279 * @arg @ref LL_RCC_SYSCLK_DIV_512
2280 */
LL_RCC_GetAHBPrescaler(void)2281 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2282 {
2283 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
2284 }
2285
2286 /**
2287 * @brief Get Sysctick clock source
2288 * @rmtoll CCIPR4 SYSTICKSEL LL_RCC_SetSystickClockSource
2289 * @retval Returned value can be one of the following values:
2290 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
2291 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
2292 * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
2293 */
LL_RCC_GetSystickClockSource(void)2294 __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
2295 {
2296 return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL));
2297 }
2298
2299 /**
2300 * @brief Get APB1 prescaler
2301 * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
2302 * @retval Returned value can be one of the following values:
2303 * @arg @ref LL_RCC_APB1_DIV_1
2304 * @arg @ref LL_RCC_APB1_DIV_2
2305 * @arg @ref LL_RCC_APB1_DIV_4
2306 * @arg @ref LL_RCC_APB1_DIV_8
2307 * @arg @ref LL_RCC_APB1_DIV_16
2308 */
LL_RCC_GetAPB1Prescaler(void)2309 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2310 {
2311 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
2312 }
2313
2314 /**
2315 * @brief Get APB2 prescaler
2316 * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
2317 * @retval Returned value can be one of the following values:
2318 * @arg @ref LL_RCC_APB2_DIV_1
2319 * @arg @ref LL_RCC_APB2_DIV_2
2320 * @arg @ref LL_RCC_APB2_DIV_4
2321 * @arg @ref LL_RCC_APB2_DIV_8
2322 * @arg @ref LL_RCC_APB2_DIV_16
2323 */
LL_RCC_GetAPB2Prescaler(void)2324 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2325 {
2326 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
2327 }
2328
2329 /**
2330 * @brief Get APB3 prescaler
2331 * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler
2332 * @retval Returned value can be one of the following values:
2333 * @arg @ref LL_RCC_APB3_DIV_1
2334 * @arg @ref LL_RCC_APB3_DIV_2
2335 * @arg @ref LL_RCC_APB3_DIV_4
2336 * @arg @ref LL_RCC_APB3_DIV_8
2337 * @arg @ref LL_RCC_APB3_DIV_16
2338 */
LL_RCC_GetAPB3Prescaler(void)2339 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2340 {
2341 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE3));
2342 }
2343
2344 /**
2345 * @brief Set System Clock After Wake-Up From Stop mode
2346 * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop
2347 * @param Clock This parameter can be one of the following values:
2348 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2349 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2350 * @retval None
2351 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)2352 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
2353 {
2354 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock);
2355 }
2356
2357 /**
2358 * @brief Get System Clock After Wake-Up From Stop mode
2359 * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop
2360 * @retval Returned value can be one of the following values:
2361 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2362 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2363 */
LL_RCC_GetClkAfterWakeFromStop(void)2364 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
2365 {
2366 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
2367 }
2368 /**
2369 * @}
2370 */
2371
2372 /** @defgroup RCC_LL_EF_MCO MCO
2373 * @{
2374 */
2375
2376 /**
2377 * @brief Configure MCO1 (pin PA8) or MCO2 (pin PC9)
2378 * @rmtoll CFGR1 MCO1 LL_RCC_ConfigMCO\n
2379 * CFGR1 MCO1PRE LL_RCC_ConfigMCO\n
2380 * CFGR1 MCO2 LL_RCC_ConfigMCO\n
2381 * CFGR1 MCO2PRE LL_RCC_ConfigMCO
2382 * @param MCOxSource This parameter can be one of the following values:
2383 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2384 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2385 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2386 * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q
2387 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2388 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2389 * @arg @ref LL_RCC_MCO2SOURCE_PLL2P
2390 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2391 * @arg @ref LL_RCC_MCO2SOURCE_PLL1P
2392 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2393 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2394 * @param MCOxPrescaler This parameter can be one of the following values:
2395 * @arg @ref LL_RCC_MCO1_DIV_1
2396 * @arg @ref LL_RCC_MCO1_DIV_2
2397 * @arg @ref LL_RCC_MCO1_DIV_3
2398 * @arg @ref LL_RCC_MCO1_DIV_4
2399 * @arg @ref LL_RCC_MCO1_DIV_5
2400 * @arg @ref LL_RCC_MCO1_DIV_6
2401 * @arg @ref LL_RCC_MCO1_DIV_7
2402 * @arg @ref LL_RCC_MCO1_DIV_8
2403 * @arg @ref LL_RCC_MCO1_DIV_9
2404 * @arg @ref LL_RCC_MCO1_DIV_10
2405 * @arg @ref LL_RCC_MCO1_DIV_11
2406 * @arg @ref LL_RCC_MCO1_DIV_12
2407 * @arg @ref LL_RCC_MCO1_DIV_13
2408 * @arg @ref LL_RCC_MCO1_DIV_14
2409 * @arg @ref LL_RCC_MCO1_DIV_15
2410 * @arg @ref LL_RCC_MCO2_DIV_1
2411 * @arg @ref LL_RCC_MCO2_DIV_2
2412 * @arg @ref LL_RCC_MCO2_DIV_3
2413 * @arg @ref LL_RCC_MCO2_DIV_4
2414 * @arg @ref LL_RCC_MCO2_DIV_5
2415 * @arg @ref LL_RCC_MCO2_DIV_6
2416 * @arg @ref LL_RCC_MCO2_DIV_7
2417 * @arg @ref LL_RCC_MCO2_DIV_8
2418 * @arg @ref LL_RCC_MCO2_DIV_9
2419 * @arg @ref LL_RCC_MCO2_DIV_10
2420 * @arg @ref LL_RCC_MCO2_DIV_11
2421 * @arg @ref LL_RCC_MCO2_DIV_12
2422 * @arg @ref LL_RCC_MCO2_DIV_13
2423 * @arg @ref LL_RCC_MCO2_DIV_14
2424 * @arg @ref LL_RCC_MCO2_DIV_15
2425 * @retval None
2426 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2427 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2428 {
2429 MODIFY_REG(RCC->CFGR1, (MCOxSource << 16U) | (MCOxPrescaler << 16U), \
2430 (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2431 }
2432
2433 /**
2434 * @}
2435 */
2436
2437
2438 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2439 * @{
2440 */
2441
2442 /**
2443 * @brief Configure periph clock source
2444 * @rmtoll CCIPR1 * LL_RCC_SetClockSource\n
2445 * CCIPR2 * LL_RCC_SetClockSource\n
2446 * CCIPR3 * LL_RCC_SetClockSource\n
2447 * CCIPR4 * LL_RCC_SetClockSource\n
2448 * CCIPR5 * LL_RCC_SetClockSource
2449 * @param ClkSource This parameter can be one of the following values:
2450 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2451 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2452 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
2453 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2454 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2455 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2456 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2457 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
2458 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
2459 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2460 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
2461 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2462 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2463 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
2464 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
2465 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2466 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
2467 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2468 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
2469 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
2470 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
2471 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
2472 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
2473 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
2474 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
2475 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
2476 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
2477 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
2478 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
2479 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
2480 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
2481 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
2482 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
2483 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
2484 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
2485 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
2486 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
2487 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*)
2488 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*)
2489 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
2490 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*)
2491 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
2492 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
2493 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*)
2494 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*)
2495 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
2496 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*)
2497 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
2498 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*)
2499 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*)
2500 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*)
2501 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*)
2502 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*)
2503 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*)
2504 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*)
2505 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*)
2506 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*)
2507 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*)
2508 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*)
2509 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*)
2510 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*)
2511 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*)
2512 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*)
2513 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*)
2514 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*)
2515 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*)
2516 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*)
2517 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*)
2518 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*)
2519 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*)
2520 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*)
2521 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*)
2522 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
2523 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2524 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
2525 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2526 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2527 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2528 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2529 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
2530 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (*)
2531 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2532 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2533 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2534 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*)
2535 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (*)
2536 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2537 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
2538 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
2539 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
2540 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2541 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
2542 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
2543 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
2544 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2545 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
2546 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
2547 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
2548 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*)
2549 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2550 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
2551 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*)
2552 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*)
2553 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*)
2554 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*)
2555 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2556 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2557 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
2558 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
2559 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2560 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
2561 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*)
2562 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
2563 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
2564 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
2565 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
2566 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*)
2567 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
2568 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
2569 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
2570 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
2571 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
2572 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
2573 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
2574 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
2575 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
2576 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
2577 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
2578 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
2579 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
2580 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
2581 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
2582 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
2583 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
2584 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
2585 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
2586 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
2587 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
2588 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
2589 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2590 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2591 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2592 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2593 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2594 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2595 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*)
2596 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
2597 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2598 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2599 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2600 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
2601 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
2602 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
2603 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
2604 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
2605 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
2606 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
2607 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
2608 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
2609 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
2610 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
2611 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
2612 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
2613 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
2614 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
2615 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
2616 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
2617 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
2618 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
2619 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
2620 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
2621 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
2622 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
2623 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
2624 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*)
2625 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*)
2626 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*)
2627 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
2628 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*)
2629 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*)
2630 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*)
2631 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*)
2632 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
2633 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*)
2634 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*)
2635 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*)
2636 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
2637 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
2638 *
2639 * (*) value not defined in all devices.
2640 * @retval None
2641 */
LL_RCC_SetClockSource(uint32_t ClkSource)2642 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2643 {
2644 uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource));
2645 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2646 }
2647
2648
2649 /**
2650 * @brief Configure USARTx kernel clock source
2651 * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
2652 * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
2653 * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n
2654 * CCIPR1 USART6SEL LL_RCC_SetUSARTClockSource\n
2655 * CCIPR1 USART10SEL LL_RCC_SetUSARTClockSource\n
2656 * CCIPR2 USART11SEL LL_RCC_SetUSARTClockSource
2657 * @param USARTxSource This parameter can be one of the following values:
2658 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2659 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2660 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
2661 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2662 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2663 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2664 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2665 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
2666 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
2667 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2668 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
2669 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2670 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2671 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
2672 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
2673 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2674 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
2675 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2676 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
2677 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
2678 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
2679 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
2680 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
2681 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
2682 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
2683 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
2684 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
2685 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
2686 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
2687 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
2688 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
2689 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
2690 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
2691 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
2692 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
2693 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
2694 *
2695 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2696 * @retval None
2697 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2698 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2699 {
2700 LL_RCC_SetClockSource(USARTxSource);
2701 }
2702
2703 #if defined(UART4)
2704 /**
2705 * @brief Configure UARTx kernel clock source
2706 * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n
2707 * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource\n
2708 * CCIPR1 UART7SEL LL_RCC_SetUARTClockSource\n
2709 * CCIPR1 UART8SEL LL_RCC_SetUARTClockSource\n
2710 * CCIPR1 UART9SEL LL_RCC_SetUARTClockSource\n
2711 * CCIPR2 UART12SEL LL_RCC_SetUARTClockSource
2712 * @param UARTxSource This parameter can be one of the following values:
2713 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2714 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q
2715 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q
2716 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2717 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI
2718 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2719 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2720 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q
2721 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q
2722 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2723 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI
2724 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2725 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2726 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q
2727 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q
2728 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2729 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI
2730 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2731 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2732 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q
2733 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q
2734 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2735 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI
2736 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2737 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1
2738 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q
2739 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q
2740 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
2741 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI
2742 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
2743 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1
2744 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q
2745 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q
2746 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI
2747 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI
2748 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE
2749 * @retval None
2750 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)2751 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2752 {
2753 LL_RCC_SetClockSource(UARTxSource);
2754 }
2755 #endif /* UART4 */
2756
2757 /**
2758 * @brief Configure LPUARTx kernel clock source
2759 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
2760 * @param LPUARTxSource This parameter can be one of the following values:
2761 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
2762 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2763 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
2764 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2765 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2766 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2767 *
2768 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2769 * @retval None
2770 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2771 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2772 {
2773 MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
2774 }
2775
2776 /**
2777 * @brief Configure I2Cx kernel clock source
2778 * @rmtoll CCIPR4 I2C1SEL LL_RCC_SetI2CClockSource\n
2779 * CCIPR4 I2C2SEL LL_RCC_SetI2CClockSource\n
2780 * CCIPR4 I2C3SEL LL_RCC_SetI2CClockSource\n
2781 * CCIPR4 I2C4SEL LL_RCC_SetI2CClockSource
2782 * @param I2CxSource This parameter can be one of the following values:
2783 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2784 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
2785 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**)
2786 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2787 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2788 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2789 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*)
2790 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**)
2791 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2792 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
2793 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
2794 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
2795 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
2796 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
2797 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
2798 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
2799 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2800 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
2801 *
2802 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2803 * (**) : For stm32h503xx family line only.
2804 * @retval None
2805 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2806 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2807 {
2808 LL_RCC_SetClockSource(I2CxSource);
2809 }
2810
2811 /**
2812 * @brief Configure I3Cx kernel clock source
2813 * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n
2814 * CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource
2815 * @param I3CxSource This parameter can be one of the following values:
2816 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
2817 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**)
2818 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2819 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
2820 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**)
2821 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**)
2822 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**)
2823 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**)
2824 * @retval None
2825 *
2826 * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines.
2827 * (**) : For stm32h503xx family line.
2828 * (***) : For stm32h5exxx and stm32h5fxxx family lines.
2829 */
LL_RCC_SetI3CClockSource(uint32_t I3CxSource)2830 __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t I3CxSource)
2831 {
2832 LL_RCC_SetClockSource(I3CxSource);
2833 }
2834
2835 /**
2836 * @brief Configure SPIx kernel clock source
2837 * @rmtoll CCIPR3 SPI1SEL LL_RCC_SetSPIClockSource\n
2838 * CCIPR3 SPI2SEL LL_RCC_SetSPIClockSource\n
2839 * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n
2840 * CCIPR3 SPI4SEL LL_RCC_SetSPIClockSource\n
2841 * CCIPR3 SPI5SEL LL_RCC_SetSPIClockSource\n
2842 * CCIPR3 SPI6SEL LL_RCC_SetSPIClockSource
2843 * @param SPIxSource This parameter can be one of the following values:
2844 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2845 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2846 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*)
2847 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
2848 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2849 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
2850 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P
2851 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
2852 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
2853 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
2854 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
2855 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P
2856 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
2857 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
2858 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
2859 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
2860 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
2861 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
2862 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
2863 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
2864 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
2865 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
2866 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
2867 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
2868 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
2869 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
2870 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
2871 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
2872 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
2873 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
2874 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
2875 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
2876 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
2877 *
2878 * (*) : For stm32h56xxx and stm32h57xxx family lines.
2879 * @retval None
2880 */
LL_RCC_SetSPIClockSource(uint32_t SPIxSource)2881 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
2882 {
2883 LL_RCC_SetClockSource(SPIxSource);
2884 }
2885
2886 /**
2887 * @brief Configure LPTIMx kernel clock source
2888 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
2889 * CCIPR2 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2890 * CCIPR2 LPTIM3SEL LL_RCC_SetLPTIMClockSource\n
2891 * CCIPR2 LPTIM4SEL LL_RCC_SetLPTIMClockSource\n
2892 * CCIPR2 LPTIM5SEL LL_RCC_SetLPTIMClockSource\n
2893 * CCIPR2 LPTIM6SEL LL_RCC_SetLPTIMClockSource
2894 * @param LPTIMxSource This parameter can be one of the following values:
2895 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
2896 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2897 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*)
2898 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2899 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2900 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2901 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2902 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2903 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
2904 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2905 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2906 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2907 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
2908 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
2909 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
2910 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
2911 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
2912 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
2913 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
2914 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
2915 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
2916 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
2917 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
2918 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
2919 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
2920 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
2921 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
2922 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
2923 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
2924 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
2925 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
2926 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
2927 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
2928 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
2929 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
2930 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
2931 *
2932 * (*) : For stm32h56xxx and stm32h57xxx family lines.
2933 * @retval None
2934 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2935 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2936 {
2937 LL_RCC_SetClockSource(LPTIMxSource);
2938 }
2939
2940 /**
2941 * @brief Configure FDCAN kernel clock source
2942 * @rmtoll CCIPR5 FDCANSEL LL_RCC_SetFDCANClockSource
2943 * @param FDCANxSource This parameter can be one of the following values:
2944 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2945 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
2946 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
2947 * @retval None
2948 *
2949 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)2950 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
2951 {
2952 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_FDCANSEL, FDCANxSource);
2953 }
2954
2955 #if defined(SAI1)
2956 /**
2957 * @brief Configure SAIx kernel clock source
2958 * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
2959 * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource
2960 * @param SAIxSource This parameter can be one of the following values:
2961 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2962 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2963 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2964 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2965 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2966 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
2967 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
2968 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
2969 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2970 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2971 * @retval None
2972 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)2973 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2974 {
2975 LL_RCC_SetClockSource(SAIxSource);
2976 }
2977 #endif /* SAI1 */
2978
2979 #if defined(SDMMC1)
2980 /**
2981 * @brief Configure SDMMCx kernel clock source
2982 * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_SetSDMMCClockSource
2983 * @rmtoll CCIPR4 SDMMC2SEL LL_RCC_SetSDMMCClockSource
2984 * @param SDMMCxSource This parameter can be one of the following values:
2985 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q
2986 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R
2987 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q
2988 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R
2989 * @retval None
2990 */
LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)2991 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2992 {
2993 LL_RCC_SetClockSource(SDMMCxSource);
2994 }
2995 #endif /* SDMMC1 */
2996
2997 /**
2998 * @brief Configure RNG kernel clock source
2999 * @rmtoll CCIPR5 RNGSEL LL_RCC_SetRNGClockSource
3000 * @param RNGxSource This parameter can be one of the following values:
3001 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3002 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3003 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3004 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3005 * @retval None
3006 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)3007 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3008 {
3009 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_RNGSEL, RNGxSource);
3010 }
3011
3012 #if defined(USB_DRD_FS)
3013 /**
3014 * @brief Configure USB clock source
3015 * @rmtoll CCIPR4 USBSEL LL_RCC_SetUSBClockSource
3016 * @param USBxSource This parameter can be one of the following values:
3017 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
3018 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3019 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*)
3020 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*)
3021 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3022 *
3023 * (*) : Available in some STM32H5 lines only.
3024 * @retval None
3025 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)3026 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3027 {
3028 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_USBSEL, USBxSource);
3029 }
3030 #endif /* USB_DRD_FS */
3031
3032 /**
3033 * @brief Configure ADCx kernel clock source
3034 * @rmtoll CCIPR5 ADCDACSEL LL_RCC_SetADCDACClockSource
3035 * @param ADCDACxSource This parameter can be one of the following values:
3036 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
3037 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
3038 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R
3039 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
3040 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
3041 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI
3042 * @retval None
3043 */
LL_RCC_SetADCDACClockSource(uint32_t ADCDACxSource)3044 __STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCDACxSource)
3045 {
3046 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADCDACSEL, ADCDACxSource);
3047 }
3048
3049 /**
3050 * @brief Configure DAC low-power kernel clock source
3051 * @rmtoll CCIPR5 DACSEL LL_RCC_SetDACLPClockSource
3052 * @param DACLPxSource This parameter can be one of the following values:
3053 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE
3054 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI
3055 * @retval None
3056 */
LL_RCC_SetDACLPClockSource(uint32_t DACLPxSource)3057 __STATIC_INLINE void LL_RCC_SetDACLPClockSource(uint32_t DACLPxSource)
3058 {
3059 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_DACSEL, DACLPxSource);
3060 }
3061
3062 #if defined(CEC)
3063 /**
3064 * @brief Configure CECx kernel clock source
3065 * @rmtoll CCIPR5 CECSEL LL_RCC_SetCECClockSource
3066 * @param CECxSource This parameter can be one of the following values:
3067 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3068 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3069 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3070 * @retval None
3071 */
LL_RCC_SetCECClockSource(uint32_t CECxSource)3072 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
3073 {
3074 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CECSEL, CECxSource);
3075 }
3076 #endif /* CEC */
3077
3078 #if defined(OCTOSPI1)
3079 /**
3080 * @brief Configure OCTOSPIx kernel clock source
3081 * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_SetOCTOSPIClockSource
3082 * @param OCTOSPIxSource This parameter can be one of the following values:
3083 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3084 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3085 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3086 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3087 * @retval None
3088 */
LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource)3089 __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource)
3090 {
3091 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OCTOSPISEL, OCTOSPIxSource);
3092 }
3093 #endif /* OCTOSPI1 */
3094
3095 /**
3096 * @brief Configure CLKP Kernel clock source
3097 * @rmtoll CCIPR5 CKPERSEL LL_RCC_SetCLKPClockSource
3098 * @param ClkSource This parameter can be one of the following values:
3099 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3100 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3101 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3102 * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE
3103 * @retval None
3104 */
LL_RCC_SetCLKPClockSource(uint32_t ClkSource)3105 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3106 {
3107 MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_CKERPSEL, ClkSource);
3108 }
3109
3110
3111 /**
3112 * @brief Get periph clock source
3113 * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n
3114 * CCIPR2 * LL_RCC_GetClockSource\n
3115 * CCIPR3 * LL_RCC_GetClockSource\n
3116 * CCIPR4 * LL_RCC_GetClockSource\n
3117 * CCIPR5 * LL_RCC_GetClockSource
3118 * @param Periph This parameter can be one of the following values:
3119 * @arg @ref LL_RCC_USART1_CLKSOURCE
3120 * @arg @ref LL_RCC_USART2_CLKSOURCE
3121 * @arg @ref LL_RCC_USART3_CLKSOURCE
3122 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
3123 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
3124 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
3125 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
3126 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
3127 * @arg @ref LL_RCC_UART7_CLKSOURCE (*)
3128 * @arg @ref LL_RCC_UART8_CLKSOURCE (*)
3129 * @arg @ref LL_RCC_UART9_CLKSOURCE (*)
3130 * @arg @ref LL_RCC_UART12_CLKSOURCE (*)
3131 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3132 * @arg @ref LL_RCC_SPI2_CLKSOURCE
3133 * @arg @ref LL_RCC_SPI3_CLKSOURCE
3134 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
3135 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
3136 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3137 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3138 * @arg @ref LL_RCC_I2C2_CLKSOURCE
3139 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
3140 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3141 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3142 * @arg @ref LL_RCC_I3C2_CLKSOURCE (*)
3143 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3144 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3145 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
3146 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
3147 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
3148 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
3149 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3150 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3151 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
3152 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
3153 * @retval Returned value can be one of the following values:
3154 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3155 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
3156 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
3157 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3158 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3159 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3160 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3161 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
3162 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
3163 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3164 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
3165 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3166 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3167 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
3168 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
3169 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3170 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
3171 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3172 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
3173 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
3174 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
3175 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
3176 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
3177 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
3178 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
3179 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
3180 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
3181 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
3182 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
3183 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
3184 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
3185 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
3186 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
3187 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
3188 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
3189 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
3190 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
3191 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q (*)
3192 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q (*)
3193 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
3194 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI (*)
3195 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
3196 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
3197 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q (*)
3198 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q (*)
3199 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
3200 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI (*)
3201 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
3202 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 (*)
3203 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q (*)
3204 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q (*)
3205 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI (*)
3206 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI (*)
3207 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE (*)
3208 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 (*)
3209 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q (*)
3210 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q (*)
3211 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI (*)
3212 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI (*)
3213 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE (*)
3214 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1 (*)
3215 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q (*)
3216 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q (*)
3217 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI (*)
3218 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI (*)
3219 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE (*)
3220 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1 (*)
3221 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q (*)
3222 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q (*)
3223 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI (*)
3224 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI (*)
3225 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE (*)
3226 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
3227 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3228 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
3229 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3230 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3231 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3232 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3233 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
3234 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (*)
3235 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3236 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
3237 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3238 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R
3239 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R
3240 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3241 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
3242 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
3243 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
3244 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
3245 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
3246 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
3247 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
3248 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3249 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
3250 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3251 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
3252 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*)
3253 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3254 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
3255 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*)
3256 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*)
3257 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*)
3258 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*)
3259 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
3260 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
3261 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
3262 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
3263 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3264 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
3265 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P (*)
3266 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
3267 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
3268 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3269 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
3270 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P (*)
3271 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
3272 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
3273 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3274 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
3275 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
3276 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
3277 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
3278 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
3279 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
3280 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
3281 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
3282 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
3283 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
3284 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
3285 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
3286 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
3287 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
3288 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
3289 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
3290 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
3291 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
3292 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
3293 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3294 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3295 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3296 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3297 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3298 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3299 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P (*)
3300 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
3301 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3302 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3303 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3304 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
3305 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
3306 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
3307 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
3308 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
3309 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
3310 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
3311 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
3312 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
3313 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
3314 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
3315 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
3316 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
3317 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
3318 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
3319 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
3320 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
3321 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
3322 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
3323 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
3324 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
3325 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
3326 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
3327 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
3328 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q (*)
3329 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P (*)
3330 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P (*)
3331 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3332 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP (*)
3333 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q (*)
3334 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P (*)
3335 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P (*)
3336 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
3337 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP (*)
3338 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q (*)
3339 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R (*)
3340 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
3341 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
3342 *
3343 * (*) value not defined in all devices.
3344 * @retval None
3345 */
LL_RCC_GetClockSource(uint32_t Periph)3346 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3347 {
3348 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph)));
3349 return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> \
3350 LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
3351 }
3352
3353 /**
3354 * @brief Get USARTx kernel clock source
3355 * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
3356 * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
3357 * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n
3358 * CCIPR1 USART6SEL LL_RCC_GetUSARTClockSource\n
3359 * CCIPR1 USART10SEL LL_RCC_GetUSARTClockSource\n
3360 * CCIPR2 USART11SEL LL_RCC_GetUSARTClockSource
3361 * @param USARTx This parameter can be one of the following values:
3362 * @arg @ref LL_RCC_USART1_CLKSOURCE
3363 * @arg @ref LL_RCC_USART2_CLKSOURCE
3364 * @arg @ref LL_RCC_USART3_CLKSOURCE
3365 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
3366 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
3367 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
3368 * @retval Returned value can be one of the following values:
3369 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3370 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
3371 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q (*)
3372 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3373 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3374 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3375 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
3376 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL2Q
3377 * @arg @ref LL_RCC_USART2_CLKSOURCE_PLL3Q (*)
3378 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
3379 * @arg @ref LL_RCC_USART2_CLKSOURCE_CSI
3380 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
3381 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
3382 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL2Q
3383 * @arg @ref LL_RCC_USART3_CLKSOURCE_PLL3Q (*)
3384 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
3385 * @arg @ref LL_RCC_USART3_CLKSOURCE_CSI
3386 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
3387 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*)
3388 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL2Q (*)
3389 * @arg @ref LL_RCC_USART6_CLKSOURCE_PLL3Q (*)
3390 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*)
3391 * @arg @ref LL_RCC_USART6_CLKSOURCE_CSI (*)
3392 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*)
3393 * @arg @ref LL_RCC_USART10_CLKSOURCE_PCLK1 (*)
3394 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL2Q (*)
3395 * @arg @ref LL_RCC_USART10_CLKSOURCE_PLL3Q (*)
3396 * @arg @ref LL_RCC_USART10_CLKSOURCE_HSI (*)
3397 * @arg @ref LL_RCC_USART10_CLKSOURCE_CSI (*)
3398 * @arg @ref LL_RCC_USART10_CLKSOURCE_LSE (*)
3399 * @arg @ref LL_RCC_USART11_CLKSOURCE_PCLK1 (*)
3400 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL2Q (*)
3401 * @arg @ref LL_RCC_USART11_CLKSOURCE_PLL3Q (*)
3402 * @arg @ref LL_RCC_USART11_CLKSOURCE_HSI (*)
3403 * @arg @ref LL_RCC_USART11_CLKSOURCE_CSI (*)
3404 * @arg @ref LL_RCC_USART11_CLKSOURCE_LSE (*)
3405 *
3406 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3407 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)3408 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
3409 {
3410 return LL_RCC_GetClockSource(USARTx);
3411 }
3412
3413 #if defined(UART4)
3414 /**
3415 * @brief Get UARTx kernel clock source
3416 * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n
3417 * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource\n
3418 * CCIPR1 UART7SEL LL_RCC_GetUARTClockSource\n
3419 * CCIPR1 UART8SEL LL_RCC_GetUARTClockSource\n
3420 * CCIPR1 UART9SEL LL_RCC_GetUARTClockSource\n
3421 * CCIPR2 UART12SEL LL_RCC_GetUARTClockSource
3422 * @param UARTx This parameter can be one of the following values:
3423 * @arg @ref LL_RCC_UART4_CLKSOURCE
3424 * @arg @ref LL_RCC_UART5_CLKSOURCE
3425 * @arg @ref LL_RCC_UART7_CLKSOURCE
3426 * @arg @ref LL_RCC_UART8_CLKSOURCE
3427 * @arg @ref LL_RCC_UART9_CLKSOURCE
3428 * @arg @ref LL_RCC_UART12_CLKSOURCE
3429 * @retval Returned value can be one of the following values:
3430 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
3431 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL2Q
3432 * @arg @ref LL_RCC_UART4_CLKSOURCE_PLL3Q
3433 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
3434 * @arg @ref LL_RCC_UART4_CLKSOURCE_CSI
3435 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
3436 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
3437 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL2Q
3438 * @arg @ref LL_RCC_UART5_CLKSOURCE_PLL3Q
3439 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
3440 * @arg @ref LL_RCC_UART5_CLKSOURCE_CSI
3441 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
3442 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
3443 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL2Q
3444 * @arg @ref LL_RCC_UART7_CLKSOURCE_PLL3Q
3445 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
3446 * @arg @ref LL_RCC_UART7_CLKSOURCE_CSI
3447 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
3448 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
3449 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL2Q
3450 * @arg @ref LL_RCC_UART8_CLKSOURCE_PLL3Q
3451 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
3452 * @arg @ref LL_RCC_UART8_CLKSOURCE_CSI
3453 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
3454 * @arg @ref LL_RCC_UART9_CLKSOURCE_PCLK1
3455 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL2Q
3456 * @arg @ref LL_RCC_UART9_CLKSOURCE_PLL3Q
3457 * @arg @ref LL_RCC_UART9_CLKSOURCE_HSI
3458 * @arg @ref LL_RCC_UART9_CLKSOURCE_CSI
3459 * @arg @ref LL_RCC_UART9_CLKSOURCE_LSE
3460 * @arg @ref LL_RCC_UART12_CLKSOURCE_PCLK1
3461 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL2Q
3462 * @arg @ref LL_RCC_UART12_CLKSOURCE_PLL3Q
3463 * @arg @ref LL_RCC_UART12_CLKSOURCE_HSI
3464 * @arg @ref LL_RCC_UART12_CLKSOURCE_CSI
3465 * @arg @ref LL_RCC_UART12_CLKSOURCE_LSE
3466 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)3467 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
3468 {
3469 return LL_RCC_GetClockSource(UARTx);
3470 }
3471 #endif /* UART4 */
3472
3473 /**
3474 * @brief Get LPUARTx kernel clock source
3475 * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource
3476 * @param LPUARTx This parameter can be one of the following values:
3477 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3478 * @retval Returned value can be one of the following values:
3479 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
3480 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3481 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q (*)
3482 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3483 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3484 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3485 *
3486 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3487 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)3488 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
3489 {
3490 return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
3491 }
3492
3493 /**
3494 * @brief Get I2Cx kernel clock source
3495 * @rmtoll CCIPR4 I2C1SEL LL_RCC_GetI2CClockSource\n
3496 * CCIPR4 I2C2SEL LL_RCC_GetI2CClockSource\n
3497 * CCIPR4 I2C3SEL LL_RCC_GetI2CClockSource\n
3498 * CCIPR4 I2C4SEL LL_RCC_GetI2CClockSource
3499 * @param I2Cx This parameter can be one of the following values:
3500 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3501 * @arg @ref LL_RCC_I2C2_CLKSOURCE
3502 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
3503 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
3504 * @retval Returned value can be one of the following values:
3505 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3506 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R (*)
3507 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL2R (**)
3508 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3509 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
3510 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
3511 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL3R (*)
3512 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PLL2R (**)
3513 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
3514 * @arg @ref LL_RCC_I2C2_CLKSOURCE_CSI
3515 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 (*)
3516 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PLL3R (*)
3517 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
3518 * @arg @ref LL_RCC_I2C3_CLKSOURCE_CSI (*)
3519 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK3 (*)
3520 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R (*)
3521 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
3522 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI (*)
3523 *
3524 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3525 * (**) : For stm32h503xx family line only.
3526 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)3527 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
3528 {
3529 return LL_RCC_GetClockSource(I2Cx);
3530 }
3531
3532 /**
3533 * @brief Get I3Cx kernel clock source
3534 * @rmtoll CCIPR4 I3C1SEL LL_RCC_GetI3CClockSource\n
3535 * CCIPR4 I3C2SEL LL_RCC_GetI3CClockSource
3536 * @param I3Cx This parameter can be one of the following values:
3537 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3538 * @arg @ref LL_RCC_I3C2_CLKSOURCE (**)
3539 * @retval Returned value can be one of the following values:
3540 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3541 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*)
3542 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**)
3543 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3544 * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE
3545 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**)
3546 * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**)
3547 * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**)
3548 * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**)
3549 *
3550 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3551 * (**) : For stm32h503xx family line.
3552 */
LL_RCC_GetI3CClockSource(uint32_t I3Cx)3553 __STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t I3Cx)
3554 {
3555 return LL_RCC_GetClockSource(I3Cx);
3556 }
3557
3558 /**
3559 * @brief Get SPIx kernel clock source
3560 * @rmtoll CCIPR3 SPI1SEL LL_RCC_GetSPIClockSource\n
3561 * CCIPR3 SPI2SEL LL_RCC_GetSPIClockSource\n
3562 * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource\n
3563 * CCIPR3 SPI4SEL LL_RCC_GetSPIClockSource\n
3564 * CCIPR3 SPI5SEL LL_RCC_GetSPIClockSource\n
3565 * CCIPR3 SPI6SEL LL_RCC_GetSPIClockSource
3566 * @param SPIx This parameter can be one of the following values:
3567 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3568 * @arg @ref LL_RCC_SPI2_CLKSOURCE
3569 * @arg @ref LL_RCC_SPI3_CLKSOURCE
3570 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
3571 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
3572 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3573 * @retval Returned value can be one of the following values:
3574 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
3575 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
3576 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P (*)
3577 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PIN
3578 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3579 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL1Q
3580 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL2P
3581 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PLL3P (*)
3582 * @arg @ref LL_RCC_SPI2_CLKSOURCE_PIN
3583 * @arg @ref LL_RCC_SPI2_CLKSOURCE_CLKP
3584 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL1Q
3585 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL2P
3586 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PLL3P (*)
3587 * @arg @ref LL_RCC_SPI3_CLKSOURCE_PIN
3588 * @arg @ref LL_RCC_SPI3_CLKSOURCE_CLKP
3589 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PCLK2 (*)
3590 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL2Q (*)
3591 * @arg @ref LL_RCC_SPI4_CLKSOURCE_PLL3Q (*)
3592 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSI (*)
3593 * @arg @ref LL_RCC_SPI4_CLKSOURCE_CSI (*)
3594 * @arg @ref LL_RCC_SPI4_CLKSOURCE_HSE (*)
3595 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PCLK3 (*)
3596 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL2Q (*)
3597 * @arg @ref LL_RCC_SPI5_CLKSOURCE_PLL3Q (*)
3598 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSI (*)
3599 * @arg @ref LL_RCC_SPI5_CLKSOURCE_CSI (*)
3600 * @arg @ref LL_RCC_SPI5_CLKSOURCE_HSE (*)
3601 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK2 (*)
3602 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q (*)
3603 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q (*)
3604 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI (*)
3605 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI (*)
3606 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE (*)
3607 *
3608 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3609 */
LL_RCC_GetSPIClockSource(uint32_t SPIx)3610 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
3611 {
3612 return LL_RCC_GetClockSource(SPIx);
3613 }
3614
3615 /**
3616 * @brief Get LPTIMx kernel clock source
3617 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3618 * CCIPR2 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
3619 * CCIPR2 LPTIM3SEL LL_RCC_GetLPTIMClockSource\n
3620 * CCIPR2 LPTIM4SEL LL_RCC_GetLPTIMClockSource\n
3621 * CCIPR2 LPTIM5SEL LL_RCC_GetLPTIMClockSource\n
3622 * CCIPR2 LPTIM6SEL LL_RCC_GetLPTIMClockSource
3623 * @param LPTIMx This parameter can be one of the following values:
3624 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3625 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3626 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
3627 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
3628 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
3629 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
3630 * @retval Returned value can be one of the following values:
3631 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK3
3632 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3633 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R (*)
3634 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3635 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3636 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3637 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
3638 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3639 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R (*)
3640 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3641 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3642 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3643 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK3 (*)
3644 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL2P (*)
3645 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PLL3R (*)
3646 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE (*)
3647 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI (*)
3648 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_CLKP (*)
3649 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PCLK3 (*)
3650 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL2P (*)
3651 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_PLL3R (*)
3652 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSE (*)
3653 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_LSI (*)
3654 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE_CLKP (*)
3655 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PCLK3 (*)
3656 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL2P (*)
3657 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_PLL3R (*)
3658 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSE (*)
3659 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_LSI (*)
3660 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE_CLKP (*)
3661 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PCLK3 (*)
3662 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL2P (*)
3663 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_PLL3R (*)
3664 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSE (*)
3665 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_LSI (*)
3666 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE_CLKP (*)
3667 *
3668 * (*) : For stm32h56xxx and stm32h57xxx family lines.
3669 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)3670 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3671 {
3672 return LL_RCC_GetClockSource(LPTIMx);
3673 }
3674
3675 /**
3676 * @brief Enable TIM2,15 and LPTIM2 Input capture clock source
3677 * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Enable
3678 * @retval None
3679 */
LL_RCC_TIMIC_Enable(void)3680 __STATIC_INLINE void LL_RCC_TIMIC_Enable(void)
3681 {
3682 SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL);
3683 }
3684
3685 /**
3686 * @brief Disable TIM2,15 and LPTIM2 Input capture clock source
3687 * @rmtoll CCIPR1 TIMICSEL LL_RCC_TIMIC_Disable
3688 * @retval None
3689 */
LL_RCC_TIMIC_Disable(void)3690 __STATIC_INLINE void LL_RCC_TIMIC_Disable(void)
3691 {
3692 CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL);
3693 }
3694
3695 /**
3696 * @brief Get FDCAN kernel clock source
3697 * @rmtoll CCIPR5 FDCANSEL LL_RCC_GetFDCANClockSource
3698 * @param FDCANx This parameter can be one of the following values:
3699 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3700 * @retval Returned value can be one of the following values:
3701 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3702 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3703 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3704 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)3705 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
3706 {
3707 return (uint32_t)(READ_BIT(RCC->CCIPR5, FDCANx));
3708 }
3709
3710 #if defined(SAI1)
3711 /**
3712 * @brief Get SAIx kernel clock source
3713 * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
3714 * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource
3715 * @param SAIx This parameter can be one of the following values:
3716 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3717 * @arg @ref LL_RCC_SAI2_CLKSOURCE
3718 * @retval Returned value can be one of the following values:
3719 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3720 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3721 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3722 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
3723 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3724 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
3725 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
3726 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
3727 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
3728 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
3729 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)3730 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3731 {
3732 return LL_RCC_GetClockSource(SAIx);
3733 }
3734 #endif /* SAI1 */
3735
3736 #if defined(SDMMC1)
3737 /**
3738 * @brief Get SDMMCx kernel clock source
3739 * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_GetSDMMCClockSource
3740 * rmtoll CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource
3741 * @param SDMMCx This parameter can be one of the following values:
3742 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
3743 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
3744 * @retval Returned value can be one of the following values:
3745 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL1Q
3746 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL2R
3747 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL1Q (*)
3748 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL2R (*)
3749 *
3750 * (*) value not defined in all devices.
3751 */
LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)3752 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
3753 {
3754 return LL_RCC_GetClockSource(SDMMCx);
3755 }
3756 #endif /* SDMMC1 */
3757
3758 /**
3759 * @brief Get RNGx kernel clock source
3760 * @rmtoll CCIPR5 RNGSEL LL_RCC_GetRNGClockSource
3761 * @param RNGx This parameter can be one of the following values:
3762 * @arg @ref LL_RCC_RNG_CLKSOURCE
3763 * @retval Returned value can be one of the following values:
3764 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3765 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3766 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3767 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3768 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)3769 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3770 {
3771 return (uint32_t)(READ_BIT(RCC->CCIPR5, RNGx));
3772 }
3773
3774 #if defined(USB_DRD_FS)
3775 /**
3776 * @brief Get USB clock source
3777 * @rmtoll CCIPR4 USBSEL LL_RCC_GetUSBClockSource
3778 * @param USBx This parameter can be one of the following values:
3779 * @arg @ref LL_RCC_USB_CLKSOURCE
3780 * @retval Returned value can be one of the following values:
3781 * @arg @ref LL_RCC_USB_CLKSOURCE_NONE
3782 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3783 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2Q (*)
3784 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q (*)
3785 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3786 *
3787 * (*) : Available in some STM32H5 lines only.
3788 */
LL_RCC_GetUSBClockSource(uint32_t USBx)3789 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3790 {
3791 return (uint32_t)(READ_BIT(RCC->CCIPR4, USBx));
3792 }
3793 #endif /* USB_DRD_FS */
3794
3795 /**
3796 * @brief Get ADCDACx kernel clock source
3797 * @rmtoll CCIPR5 ADCDACSEL LL_RCC_GetADCDACClockSource
3798 * @param ADCDACx This parameter can be one of the following values:
3799 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
3800 * @retval Returned value can be one of the following values:
3801 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
3802 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
3803 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2R
3804 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
3805 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
3806 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_CSI
3807 */
LL_RCC_GetADCDACClockSource(uint32_t ADCDACx)3808 __STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCDACx)
3809 {
3810 return (uint32_t)(READ_BIT(RCC->CCIPR5, ADCDACx));
3811 }
3812
3813 /**
3814 * @brief Get DAC low-power kernel Clock Source
3815 * @rmtoll CCIPR5 DACSEL LL_RCC_GetDACLPClockSource
3816 * @param DACLPx This parameter can be one of the following values:
3817 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE
3818 * @retval Returned value can be one of the following values:
3819 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSE
3820 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE_LSI
3821 */
LL_RCC_GetDACLPClockSource(uint32_t DACLPx)3822 __STATIC_INLINE uint32_t LL_RCC_GetDACLPClockSource(uint32_t DACLPx)
3823 {
3824 return (uint32_t)(READ_BIT(RCC->CCIPR5, DACLPx));
3825 }
3826
3827 /**
3828 * @brief Get CECx kernel clock source
3829 * @rmtoll CCIPR5 CECSEL LL_RCC_GetCECClockSource
3830 * @param CECx This parameter can be one of the following values:
3831 * @arg @ref LL_RCC_CEC_CLKSOURCE
3832 * @retval Returned value can be one of the following values:
3833 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3834 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3835 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3836 */
LL_RCC_GetCECClockSource(uint32_t CECx)3837 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3838 {
3839 return (uint32_t)(READ_BIT(RCC->CCIPR5, CECx));
3840 }
3841
3842 #if defined(OCTOSPI1)
3843 /**
3844 * @brief Get OCTOSPI kernel clock source
3845 * @rmtoll CCIPR4 OCTOSPISEL LL_RCC_GetOCTOSPIClockSource
3846 * @param OCTOSPIx This parameter can be one of the following values:
3847 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
3848 * @retval Returned value can be one of the following values:
3849 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3850 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3851 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3852 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3853 */
LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)3854 __STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
3855 {
3856 return (uint32_t)(READ_BIT(RCC->CCIPR4, OCTOSPIx));
3857 }
3858 #endif /* OCTOSPI1 */
3859
3860 /**
3861 * @brief Get CLKP kernel clock source
3862 * @rmtoll CCIPR5 CKPERSEL LL_RCC_GetCLKPClockSource
3863 * @param CLKPx This parameter can be one of the following values:
3864 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3865 * @retval Returned value can be one of the following values:
3866 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3867 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3868 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3869 * @arg @ref LL_RCC_CLKP_CLKSOURCE_NONE
3870 */
LL_RCC_GetCLKPClockSource(uint32_t CLKPx)3871 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t CLKPx)
3872 {
3873 return (uint32_t)(READ_BIT(RCC->CCIPR5, CLKPx));
3874 }
3875
3876 /**
3877 * @brief Configure the Kernel wakeup clock source
3878 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
3879 * @param Source This parameter can be one of the following values:
3880 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
3881 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
3882 * @retval None
3883 */
LL_RCC_SetKerWakeUpClkSource(uint32_t Source)3884 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
3885 {
3886 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Source);
3887 }
3888
3889 /**
3890 * @brief Get the Kernel wakeup clock source
3891 * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
3892 * @retval Returned value can be one of the following values:
3893 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
3894 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
3895 */
LL_RCC_GetKerWakeUpClkSource(void)3896 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
3897 {
3898 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK));
3899 }
3900
3901 /**
3902 * @}
3903 */
3904
3905 /** @defgroup RCC_LL_EF_RTC RTC
3906 * @{
3907 */
3908
3909 /**
3910 * @brief Set RTC Clock Source
3911 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3912 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3913 * set). The BDRST bit can be used to reset them.
3914 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3915 * @param Source This parameter can be one of the following values:
3916 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3917 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3918 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3919 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3920 * @retval None
3921 */
LL_RCC_SetRTCClockSource(uint32_t Source)3922 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3923 {
3924 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3925 }
3926
3927 /**
3928 * @brief Get RTC Clock Source
3929 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3930 * @retval Returned value can be one of the following values:
3931 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3932 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3933 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3934 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV
3935 */
LL_RCC_GetRTCClockSource(void)3936 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3937 {
3938 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3939 }
3940
3941 /**
3942 * @brief Enable RTC
3943 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3944 * @retval None
3945 */
LL_RCC_EnableRTC(void)3946 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3947 {
3948 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3949 }
3950
3951 /**
3952 * @brief Disable RTC
3953 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3954 * @retval None
3955 */
LL_RCC_DisableRTC(void)3956 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3957 {
3958 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3959 }
3960
3961 /**
3962 * @brief Check if RTC has been enabled or not
3963 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3964 * @retval State of bit (1 or 0).
3965 */
LL_RCC_IsEnabledRTC(void)3966 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3967 {
3968 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
3969 }
3970
3971 /**
3972 * @brief Force the Backup domain reset
3973 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
3974 * @retval None
3975 */
LL_RCC_ForceBackupDomainReset(void)3976 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3977 {
3978 SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3979 }
3980
3981 /**
3982 * @brief Release the Backup domain reset
3983 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
3984 * @retval None
3985 */
LL_RCC_ReleaseBackupDomainReset(void)3986 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3987 {
3988 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3989 }
3990
3991 /**
3992 * @brief Set HSE Prescalers for RTC Clock
3993 * @rmtoll CFGR1 RTCPRE LL_RCC_SetRTC_HSEPrescaler
3994 * @param Prescaler This parameter can be one of the following values:
3995 * @arg @ref LL_RCC_RTC_HSE_NOCLOCK
3996 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3997 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3998 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3999 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4000 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4001 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4002 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4003 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4004 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4005 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4006 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4007 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4008 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4009 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4010 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4011 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4012 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4013 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4014 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4015 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4016 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4017 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4018 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4019 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4020 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4021 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4022 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4023 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4024 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4025 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4026 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4027 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4028 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4029 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4030 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4031 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4032 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4033 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4034 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4035 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4036 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4037 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4038 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4039 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4040 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4041 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4042 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4043 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4044 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4045 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4046 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4047 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4048 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4049 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4050 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4051 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4052 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4053 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4054 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4055 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4056 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4057 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4058 * @retval None
4059 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)4060 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4061 {
4062 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, Prescaler);
4063 }
4064
4065 /**
4066 * @brief Get HSE Prescalers for RTC Clock
4067 * @rmtoll CFGR1 RTCPRE LL_RCC_GetRTC_HSEPrescaler
4068 * @retval Returned value can be one of the following values:
4069 * @arg @ref LL_RCC_RTC_HSE_NOCLOCK
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4131 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4132 */
LL_RCC_GetRTC_HSEPrescaler(void)4133 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4134 {
4135 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE));
4136 }
4137
4138
4139 /**
4140 * @}
4141 */
4142
4143 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4144 * @{
4145 */
4146
4147 /**
4148 * @brief Set Timers Clock Prescalers
4149 * @rmtoll CFGR1 TIMPRE LL_RCC_SetTIMPrescaler
4150 * @param Prescaler This parameter can be one of the following values:
4151 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4152 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4153 * @retval None
4154 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)4155 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4156 {
4157 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_TIMPRE, Prescaler);
4158 }
4159
4160 /**
4161 * @brief Get Timers Clock Prescalers
4162 * @rmtoll CFGR1 TIMPRE LL_RCC_GetTIMPrescaler
4163 * @retval Returned value can be one of the following values:
4164 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4165 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4166 */
LL_RCC_GetTIMPrescaler(void)4167 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4168 {
4169 return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_TIMPRE));
4170 }
4171
4172 /**
4173 * @}
4174 */
4175
4176 /** @defgroup RCC_LL_EF_PLL1 PLL1
4177 * @{
4178 */
4179
4180 /**
4181 * @brief Enable PLL1
4182 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
4183 * @retval None
4184 */
LL_RCC_PLL1_Enable(void)4185 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4186 {
4187 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4188 }
4189
4190 /**
4191 * @brief Disable PLL1
4192 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4193 * @rmtoll CR PLLON LL_RCC_PLL1_Disable
4194 * @retval None
4195 */
LL_RCC_PLL1_Disable(void)4196 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4197 {
4198 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4199 }
4200
4201 /**
4202 * @brief Check if PLL1 Ready
4203 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
4204 * @retval State of bit (1 or 0).
4205 */
LL_RCC_PLL1_IsReady(void)4206 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4207 {
4208 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
4209 }
4210
4211 /**
4212 * @brief Enable PLL1 P output mapped to SYSCLK
4213 * @note This API shall be called only when PLL1 is disabled.
4214 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Enable
4215 * @retval None
4216 */
LL_RCC_PLL1P_Enable(void)4217 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4218 {
4219 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
4220 }
4221
4222 /**
4223 * @brief Disable PLL1 P output mapped to SYSCLK
4224 * @note Cannot be disabled if the PLL1 clock is used as the system
4225 * clock
4226 * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1P_Disable
4227 * @retval None
4228 */
LL_RCC_PLL1P_Disable(void)4229 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4230 {
4231 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
4232 }
4233
4234 /**
4235 * @brief Enable PLL1 Q output
4236 * @note This API shall be called only when PLL1 is disabled.
4237 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Enable
4238 * @retval None
4239 */
LL_RCC_PLL1Q_Enable(void)4240 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4241 {
4242 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
4243 }
4244
4245 /**
4246 * @brief Disable PLL1 Q output
4247 * @note In order to save power, when the PLL1 Q output of the PLL1 is
4248 * not used, PLL1Q should be 0
4249 * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1Q_Disable
4250 * @retval None
4251 */
LL_RCC_PLL1Q_Disable(void)4252 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4253 {
4254 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
4255 }
4256
4257 /**
4258 * @brief Enable PLL1 R output
4259 * @note This API shall be called only when PLL1 is disabled.
4260 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Enable
4261 * @retval None
4262 */
LL_RCC_PLL1R_Enable(void)4263 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4264 {
4265 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
4266 }
4267
4268 /**
4269 * @brief Disable PLL1 R output
4270 * @note In order to save power, when the PLL1 R output of the PLL1 is
4271 * not used, PLL1R should be 0
4272 * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1R_Disable
4273 * @retval None
4274 */
LL_RCC_PLL1R_Disable(void)4275 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4276 {
4277 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
4278 }
4279
4280 /**
4281 * @brief Check if PLL1 P is enabled
4282 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
4283 * @retval State of bit (1 or 0).
4284 */
LL_RCC_PLL1P_IsEnabled(void)4285 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4286 {
4287 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL);
4288 }
4289
4290 /**
4291 * @brief Check if PLL1 Q is enabled
4292 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
4293 * @retval State of bit (1 or 0).
4294 */
LL_RCC_PLL1Q_IsEnabled(void)4295 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4296 {
4297 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL);
4298 }
4299
4300 /**
4301 * @brief Check if PLL1 R is enabled
4302 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
4303 * @retval State of bit (1 or 0).
4304 */
LL_RCC_PLL1R_IsEnabled(void)4305 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4306 {
4307 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL);
4308 }
4309
4310 /**
4311 * @brief Configure PLL1 used for SYSCLK
4312 * @note PLL1 Source, PLL1M, PLL1N and PLL1P can be written only when PLL1 is disabled.
4313 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n
4314 * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n
4315 * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n
4316 * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS
4317 * @param Source This parameter can be one of the following values:
4318 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4319 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4320 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4321 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4322 * @param PLL1M parameter can be a value between 1 and 63
4323 * @param PLL1P parameter can be a value between 1 and 128 (odd values not allowed)
4324 * @param PLL1N parameter can be a value between 4 and 512
4325 * @retval None
4326 */
LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source,uint32_t PLL1M,uint32_t PLL1N,uint32_t PLL1P)4327 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLL1M, uint32_t PLL1N, uint32_t PLL1P)
4328 {
4329 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | (PLL1M << RCC_PLL1CFGR_PLL1M_Pos));
4330 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, \
4331 ((PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos));
4332 }
4333
4334 /**
4335 * @brief Configure PLL clock source
4336 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetSource
4337 * @param PLL1Source This parameter can be one of the following values:
4338 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4339 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4340 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4341 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4342 * @retval None
4343 */
LL_RCC_PLL1_SetSource(uint32_t PLL1Source)4344 __STATIC_INLINE void LL_RCC_PLL1_SetSource(uint32_t PLL1Source)
4345 {
4346 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
4347 }
4348
4349 /**
4350 * @brief Get the oscillator used as PLL1 clock source.
4351 * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetSource
4352 * @retval Returned value can be one of the following values:
4353 * @arg @ref LL_RCC_PLL1SOURCE_NONE
4354 * @arg @ref LL_RCC_PLL1SOURCE_CSI
4355 * @arg @ref LL_RCC_PLL1SOURCE_HSI
4356 * @arg @ref LL_RCC_PLL1SOURCE_HSE
4357 */
LL_RCC_PLL1_GetSource(void)4358 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetSource(void)
4359 {
4360 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
4361 }
4362
4363 /**
4364 * @brief Set Main PLL1 multiplication factor for VCO
4365 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN
4366 * @param PLL1N parameter can be a value between 4 and 512
4367 */
LL_RCC_PLL1_SetN(uint32_t PLL1N)4368 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
4369 {
4370 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
4371 }
4372
4373 /**
4374 * @brief Get Main PLL1 multiplication factor for VCO
4375 * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN
4376 * @retval Between 4 and 512
4377 */
LL_RCC_PLL1_GetN(void)4378 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4379 {
4380 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
4381 }
4382
4383 /**
4384 * @brief Set Main PLL1 division factor for PLL1P
4385 * @note Used for System clock
4386 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP
4387 * @param PLL1P parameter can be a value between 2 and 128 (odd value not allowed)
4388 */
LL_RCC_PLL1_SetP(uint32_t PLL1P)4389 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
4390 {
4391 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
4392 }
4393
4394 /**
4395 * @brief Get PLL1 division factor for PLL1P
4396 * @note Used for System clock
4397 * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP
4398 * @retval Between 2 and 128
4399 */
LL_RCC_PLL1_GetP(void)4400 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4401 {
4402 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
4403 }
4404
4405
4406 /**
4407 * @brief Set PLL1 division factor for PLL1Q
4408 * @note Used for peripherals clocks
4409 * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ
4410 * @param PLL1Q parameter can be a value between 1 and 128
4411 */
LL_RCC_PLL1_SetQ(uint32_t PLL1Q)4412 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
4413 {
4414 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
4415 }
4416
4417 /**
4418 * @brief Get PLL1 division factor for PLL1Q
4419 * @note Used for peripherals clocks
4420 * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ
4421 * @retval Between 1 and 128
4422 */
LL_RCC_PLL1_GetQ(void)4423 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4424 {
4425 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
4426 }
4427
4428 /**
4429 * @brief Set PLL1 division factor for PLL1R
4430 * @note Used for trace
4431 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
4432 * @param PLL1R parameter can be a value between 1 and 128
4433 */
LL_RCC_PLL1_SetR(uint32_t PLL1R)4434 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
4435 {
4436 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
4437 }
4438
4439 /**
4440 * @brief Get Main PLL1 division factor for PLL1R
4441 * @note Used for trace
4442 * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
4443 * @retval Between 1 and 128
4444 */
LL_RCC_PLL1_GetR(void)4445 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4446 {
4447 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
4448 }
4449
4450 /**
4451 * @brief Set Division factor for the main PLL and other PLL
4452 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetM
4453 * @param PLL1M parameter can be a value between 1 and 63
4454 */
LL_RCC_PLL1_SetM(uint32_t PLL1M)4455 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t PLL1M)
4456 {
4457 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, PLL1M << RCC_PLL1CFGR_PLL1M_Pos);
4458 }
4459
4460 /**
4461 * @brief Get Division factor for the main PLL and other PLL
4462 * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetM
4463 * @retval Between 0 and 63
4464 */
LL_RCC_PLL1_GetM(void)4465 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4466 {
4467 return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos);
4468 }
4469
4470 /**
4471 * @brief Enable PLL1 FRACN
4472 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4473 * @retval None
4474 */
LL_RCC_PLL1FRACN_Enable(void)4475 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4476 {
4477 SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
4478 }
4479
4480 /**
4481 * @brief Check if PLL1 FRACN is enabled
4482 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
4483 * @retval State of bit (1 or 0).
4484 */
LL_RCC_PLL1FRACN_IsEnabled(void)4485 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4486 {
4487 return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
4488 }
4489
4490 /**
4491 * @brief Disable PLL1 FRACN
4492 * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
4493 * @retval None
4494 */
LL_RCC_PLL1FRACN_Disable(void)4495 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4496 {
4497 CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
4498 }
4499
4500 /**
4501 * @brief Set PLL1 FRACN Coefficient
4502 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
4503 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4504 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)4505 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4506 {
4507 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
4508 }
4509
4510 /**
4511 * @brief Get PLL1 FRACN Coefficient
4512 * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
4513 * @retval A value between 0 and 8191 (0x1FFF)
4514 */
LL_RCC_PLL1_GetFRACN(void)4515 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4516 {
4517 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
4518 }
4519
4520 /**
4521 * @brief Set PLL1 VCO Input Range
4522 * @note This API shall be called only when PLL1 is disabled.
4523 * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
4524 * @param InputRange This parameter can be one of the following values:
4525 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4526 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4527 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4528 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4529 * @retval None
4530 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)4531 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4532 {
4533 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
4534 }
4535
4536 /**
4537 * @brief Set PLL1 VCO OutputRange
4538 * @note This API shall be called only when PLL1 is disabled.
4539 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOutputRange
4540 * @param VCORange This parameter can be one of the following values:
4541 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4542 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4543 * @retval None
4544 */
LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)4545 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4546 {
4547 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, VCORange << RCC_PLL1CFGR_PLL1VCOSEL_Pos);
4548 }
4549
4550 /**
4551 * @}
4552 */
4553
4554 /** @defgroup RCC_LL_EF_PLL2 PLL2
4555 * @{
4556 */
4557
4558 /**
4559 * @brief Enable PLL2
4560 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4561 * @retval None
4562 */
LL_RCC_PLL2_Enable(void)4563 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4564 {
4565 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4566 }
4567
4568 /**
4569 * @brief Disable PLL2
4570 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4571 * @retval None
4572 */
LL_RCC_PLL2_Disable(void)4573 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4574 {
4575 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4576 }
4577
4578 /**
4579 * @brief Check if PLL2 Ready
4580 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4581 * @retval State of bit (1 or 0).
4582 */
LL_RCC_PLL2_IsReady(void)4583 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4584 {
4585 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL);
4586 }
4587
4588 /**
4589 * @brief Configure PLL2 clock source
4590 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource
4591 * @param PLL2Source This parameter can be one of the following values:
4592 * @arg @ref LL_RCC_PLL2SOURCE_NONE
4593 * @arg @ref LL_RCC_PLL2SOURCE_CSI
4594 * @arg @ref LL_RCC_PLL2SOURCE_HSI
4595 * @arg @ref LL_RCC_PLL2SOURCE_HSE
4596 * @retval None
4597 */
LL_RCC_PLL2_SetSource(uint32_t PLL2Source)4598 __STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source)
4599 {
4600 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source);
4601 }
4602
4603 /**
4604 * @brief Get the oscillator used as PLL2 clock source.
4605 * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource
4606 * @retval Returned value can be one of the following values:
4607 * @arg @ref LL_RCC_PLL2SOURCE_NONE
4608 * @arg @ref LL_RCC_PLL2SOURCE_CSI
4609 * @arg @ref LL_RCC_PLL2SOURCE_HSI
4610 * @arg @ref LL_RCC_PLL2SOURCE_HSE
4611 */
LL_RCC_PLL2_GetSource(void)4612 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
4613 {
4614 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC));
4615 }
4616
4617 /**
4618 * @brief Set PLL2 Division factor M
4619 * @note This API shall be called only when PLL2 is disabled.
4620 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetM
4621 * @param PLL2M parameter can be a value between 1 and 63
4622 */
LL_RCC_PLL2_SetM(uint32_t PLL2M)4623 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t PLL2M)
4624 {
4625 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, PLL2M << RCC_PLL2CFGR_PLL2M_Pos);
4626 }
4627
4628 /**
4629 * @brief Get PLL2 division factor M
4630 * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetM
4631 * @retval Between 1 and 63
4632 */
LL_RCC_PLL2_GetM(void)4633 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4634 {
4635 return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
4636 }
4637
4638 /**
4639 * @brief Set PLL2 multiplication factor N
4640 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN
4641 * @param PLL2N parameter can be a value between 4 and 512
4642 */
LL_RCC_PLL2_SetN(uint32_t PLL2N)4643 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N)
4644 {
4645 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos);
4646 }
4647
4648 /**
4649 * @brief Get PLL2 multiplication factor N
4650 * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN
4651 * @retval Between 4 and 512
4652 */
LL_RCC_PLL2_GetN(void)4653 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4654 {
4655 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL);
4656 }
4657
4658 /**
4659 * @brief Set PLL2 division factor P
4660 * @note Used for peripherals clocks
4661 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP
4662 * @param PLL2P parameter can be a value between 1 and 128
4663 */
LL_RCC_PLL2_SetP(uint32_t PLL2P)4664 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P)
4665 {
4666 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos);
4667 }
4668
4669 /**
4670 * @brief Get PLL2 division factor P
4671 * @note Used for peripherals clocks
4672 * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP
4673 * @retval Between 1 and 128
4674 */
LL_RCC_PLL2_GetP(void)4675 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4676 {
4677 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL);
4678 }
4679
4680
4681 /**
4682 * @brief Set PLL2 division factor Q
4683 * @note Used for peripherals clocks
4684 * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ
4685 * @param PLL2Q parameter can be a value between 1 and 128
4686 */
LL_RCC_PLL2_SetQ(uint32_t PLL2Q)4687 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q)
4688 {
4689 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos);
4690 }
4691
4692 /**
4693 * @brief Get PLL2 division factor Q
4694 * @note Used for peripherals clocks
4695 * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ
4696 * @retval Between 1 and 128
4697 */
LL_RCC_PLL2_GetQ(void)4698 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4699 {
4700 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
4701 }
4702
4703 /**
4704 * @brief Set PLL2 division factor R
4705 * @note Used for PLL2CLK selected for peripherals clocks
4706 * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_SetR
4707 * @param PLL2R parameter can be a value between 1 and 128
4708 */
LL_RCC_PLL2_SetR(uint32_t PLL2R)4709 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R)
4710 {
4711 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos);
4712 }
4713
4714 /**
4715 * @brief Get PLL2 division factor R
4716 * @note Used for PLL2CLK (system clock)
4717 * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR
4718 * @retval Between 1 and 128
4719 */
LL_RCC_PLL2_GetR(void)4720 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4721 {
4722 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1UL);
4723 }
4724
4725 /**
4726 * @brief Enable PLL2 P output
4727 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Enable
4728 * @retval None
4729 */
LL_RCC_PLL2P_Enable(void)4730 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4731 {
4732 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
4733 }
4734
4735 /**
4736 * @brief Disable PLL2 P output
4737 * @note In order to save power, when PLL2P output is
4738 * not used, it should be disabled (at any time)
4739 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_Disable
4740 * @retval None
4741 */
LL_RCC_PLL2P_Disable(void)4742 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4743 {
4744 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
4745 }
4746
4747 /**
4748 * @brief Enable PLL2 Q output
4749 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_Enable
4750 * @retval None
4751 */
LL_RCC_PLL2Q_Enable(void)4752 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4753 {
4754 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
4755 }
4756
4757 /**
4758 * @brief Disable PLL2 Q output
4759 * @note In order to save power, when PLL2Q output is
4760 * not used, it should be disabled (at any time)
4761 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_Disable
4762 * @retval None
4763 */
LL_RCC_PLL2Q_Disable(void)4764 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4765 {
4766 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
4767 }
4768
4769 /**
4770 * @brief Enable PLL2 R output
4771 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Enable
4772 * @retval None
4773 */
LL_RCC_PLL2R_Enable(void)4774 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4775 {
4776 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
4777 }
4778
4779 /**
4780 * @brief Disable PLL2 R output
4781 * @note In order to save power, when PLL2R output is
4782 * not used, it should be disabled (at any time)
4783 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_Disable
4784 * @retval None
4785 */
LL_RCC_PLL2R_Disable(void)4786 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4787 {
4788 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
4789 }
4790
4791 /**
4792 * @brief Check if PLL2 P is enabled
4793 * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2P_IsEnabled
4794 * @retval State of bit (1 or 0).
4795 */
LL_RCC_PLL2P_IsEnabled(void)4796 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4797 {
4798 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == RCC_PLL2CFGR_PLL2PEN) ? 1UL : 0UL);
4799 }
4800
4801 /**
4802 * @brief Check if PLL2 Q is enabled
4803 * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2Q_IsEnabled
4804 * @retval State of bit (1 or 0).
4805 */
LL_RCC_PLL2Q_IsEnabled(void)4806 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4807 {
4808 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == RCC_PLL2CFGR_PLL2QEN) ? 1UL : 0UL);
4809 }
4810
4811 /**
4812 * @brief Check if PLL2 R is enabled
4813 * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2R_IsEnabled
4814 * @retval State of bit (1 or 0).
4815 */
LL_RCC_PLL2R_IsEnabled(void)4816 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4817 {
4818 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == RCC_PLL2CFGR_PLL2REN) ? 1UL : 0UL);
4819 }
4820
4821 /**
4822 * @brief Enable PLL2 FRACN
4823 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4824 * @retval None
4825 */
LL_RCC_PLL2FRACN_Enable(void)4826 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4827 {
4828 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
4829 }
4830
4831 /**
4832 * @brief Check if PLL2 FRACN is enabled
4833 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4834 * @retval State of bit (1 or 0).
4835 */
LL_RCC_PLL2FRACN_IsEnabled(void)4836 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4837 {
4838 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL);
4839 }
4840
4841 /**
4842 * @brief Disable PLL2 FRACN
4843 * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable
4844 * @retval None
4845 */
LL_RCC_PLL2FRACN_Disable(void)4846 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4847 {
4848 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
4849 }
4850
4851 /**
4852 * @brief Set PLL2 FRACN Coefficient
4853 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN
4854 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4855 */
LL_RCC_PLL2_SetFRACN(uint32_t FRACN)4856 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4857 {
4858 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos);
4859 }
4860
4861 /**
4862 * @brief Get PLL2 FRACN Coefficient
4863 * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN
4864 * @retval A value between 0 and 8191 (0x1FFF)
4865 */
LL_RCC_PLL2_GetFRACN(void)4866 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4867 {
4868 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos);
4869 }
4870
4871 /**
4872 * @brief Set PLL2 VCO Input Range
4873 * @note This API shall be called only when PLL2 is disabled.
4874 * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4875 * @param InputRange This parameter can be one of the following values:
4876 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4877 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4878 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4879 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4880 * @retval None
4881 */
LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)4882 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4883 {
4884 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos);
4885 }
4886
4887 /**
4888 * @brief Set PLL2 VCO OutputRange
4889 * @note This API shall be called only when PLL2 is disabled.
4890 * @rmtoll PLL2CFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOutputRange
4891 * @param VCORange This parameter can be one of the following values:
4892 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4893 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4894 * @retval None
4895 */
LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)4896 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4897 {
4898 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2VCOSEL, VCORange << RCC_PLL2CFGR_PLL2VCOSEL_Pos);
4899 }
4900
4901 /**
4902 * @}
4903 */
4904
4905 #if defined(RCC_CR_PLL3ON)
4906 /** @defgroup RCC_LL_EF_PLL3 PLL3
4907 * @{
4908 */
4909
4910 /**
4911 * @brief Enable PLL3
4912 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4913 * @retval None
4914 */
LL_RCC_PLL3_Enable(void)4915 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4916 {
4917 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4918 }
4919
4920 /**
4921 * @brief Disable PLL3
4922 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4923 * @retval None
4924 */
LL_RCC_PLL3_Disable(void)4925 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4926 {
4927 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4928 }
4929
4930 /**
4931 * @brief Check if PLL3 is Ready
4932 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4933 * @retval State of bit (1 or 0).
4934 */
LL_RCC_PLL3_IsReady(void)4935 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4936 {
4937 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL);
4938 }
4939
4940
4941 /**
4942 * @brief Configure PLL3 clock source
4943 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource
4944 * @param PLLSource This parameter can be one of the following values:
4945 * @arg @ref LL_RCC_PLL3SOURCE_NONE
4946 * @arg @ref LL_RCC_PLL3SOURCE_CSI
4947 * @arg @ref LL_RCC_PLL3SOURCE_HSI
4948 * @arg @ref LL_RCC_PLL3SOURCE_HSE
4949 * @retval None
4950 */
LL_RCC_PLL3_SetSource(uint32_t PLLSource)4951 __STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
4952 {
4953 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource);
4954 }
4955
4956 /**
4957 * @brief Get the oscillator used as PLL3 clock source.
4958 * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource
4959 * @retval Returned value can be one of the following values:
4960 * @arg @ref LL_RCC_PLL3SOURCE_NONE
4961 * @arg @ref LL_RCC_PLL3SOURCE_CSI
4962 * @arg @ref LL_RCC_PLL3SOURCE_HSI
4963 * @arg @ref LL_RCC_PLL3SOURCE_HSE
4964 */
LL_RCC_PLL3_GetSource(void)4965 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
4966 {
4967 return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC));
4968 }
4969
4970 /**
4971 * @brief Set PLL3 multiplication factor N
4972 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN
4973 * @param PLL3N parameter can be a value between 4 and 512
4974 */
LL_RCC_PLL3_SetN(uint32_t PLL3N)4975 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N)
4976 {
4977 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos);
4978 }
4979
4980 /**
4981 * @brief Get PLL3 multiplication factor N
4982 * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN
4983 * @retval Between 4 and 512
4984 */
LL_RCC_PLL3_GetN(void)4985 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
4986 {
4987 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL);
4988 }
4989
4990 /**
4991 * @brief Set PLL3 division factor P
4992 * @note Used for peripherals clocks
4993 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP
4994 * @param PLL3P parameter can be a value between 1 and 128
4995 */
LL_RCC_PLL3_SetP(uint32_t PLL3P)4996 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P)
4997 {
4998 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos);
4999 }
5000
5001 /**
5002 * @brief Get PLL3 division factor P
5003 * @note Used for peripherals clocks
5004 * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP
5005 * @retval Between 1 and 128
5006 */
LL_RCC_PLL3_GetP(void)5007 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5008 {
5009 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL);
5010 }
5011
5012 /**
5013 * @brief Set PLL3 division factor Q
5014 * @note Used for peripherals clocks
5015 * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ
5016 * @param PLL3Q parameter can be a value between 1 and 128
5017 */
LL_RCC_PLL3_SetQ(uint32_t PLL3Q)5018 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q)
5019 {
5020 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos);
5021 }
5022
5023 /**
5024 * @brief Get PLL3 division factor Q
5025 * @note Used for peripherals clocks
5026 * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ
5027 * @retval Between 1 and 128
5028 */
LL_RCC_PLL3_GetQ(void)5029 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5030 {
5031 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL);
5032 }
5033
5034 /**
5035 * @brief Set PLL3 division factor R
5036 * @note Used for peripherals clocks
5037 * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_SetR
5038 * @param PLL3R parameter can be a value between 1 and 128
5039 */
LL_RCC_PLL3_SetR(uint32_t PLL3R)5040 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R)
5041 {
5042 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos);
5043 }
5044
5045 /**
5046 * @brief Get PLL3 division factor R
5047 * @note Used for PLL3CLK (system clock)
5048 * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR
5049 * @retval Between 1 and 128
5050 */
LL_RCC_PLL3_GetR(void)5051 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5052 {
5053 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL);
5054 }
5055
5056 /**
5057 * @brief Set PLL3 Division factor M
5058 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetM
5059 * @param PLL3M parameter can be a value between 1 and 63
5060 */
LL_RCC_PLL3_SetM(uint32_t PLL3M)5061 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t PLL3M)
5062 {
5063 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, PLL3M << RCC_PLL3CFGR_PLL3M_Pos);
5064 }
5065
5066 /**
5067 * @brief Get PLL3 Division factor M
5068 * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetM
5069 * @retval Between 1 and 63
5070 */
LL_RCC_PLL3_GetM(void)5071 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5072 {
5073 return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
5074 }
5075
5076 /**
5077 * @brief Enable PLL3 P output
5078 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Enable
5079 * @retval None
5080 */
LL_RCC_PLL3P_Enable(void)5081 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
5082 {
5083 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
5084 }
5085
5086 /**
5087 * @brief Disable PLL3 P output
5088 * @note In order to save power, when PLL3P output is
5089 * not used, it should be disabled (at any time)
5090 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_Disable
5091 * @retval None
5092 */
LL_RCC_PLL3P_Disable(void)5093 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5094 {
5095 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
5096 }
5097
5098 /**
5099 * @brief Enable PLL3 Q output
5100 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Enable
5101 * @retval None
5102 */
LL_RCC_PLL3Q_Enable(void)5103 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
5104 {
5105 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
5106 }
5107
5108 /**
5109 * @brief Disable PLL3 Q output
5110 * @note In order to save power, when PLL3Q output is
5111 * not used, it should be disabled (at any time)
5112 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_Disable
5113 * @retval None
5114 */
LL_RCC_PLL3Q_Disable(void)5115 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
5116 {
5117 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
5118 }
5119
5120 /**
5121 * @brief Enable PLL3 R output
5122 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Enable
5123 * @retval None
5124 */
LL_RCC_PLL3R_Enable(void)5125 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
5126 {
5127 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
5128 }
5129
5130 /**
5131 * @brief Disable PLL3 R output
5132 * @note In order to save power, when PLL3R output is
5133 * not used, it should be disabled (at any time)
5134 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_Disable
5135 * @retval None
5136 */
LL_RCC_PLL3R_Disable(void)5137 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5138 {
5139 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
5140 }
5141
5142 /**
5143 * @brief Check if PLL3 P is enabled
5144 * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3P_IsEnabled
5145 * @retval State of bit (1 or 0).
5146 */
LL_RCC_PLL3P_IsEnabled(void)5147 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5148 {
5149 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == RCC_PLL3CFGR_PLL3PEN) ? 1UL : 0UL);
5150 }
5151
5152 /**
5153 * @brief Check if PLL3 Q is enabled
5154 * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3Q_IsEnabled
5155 * @retval State of bit (1 or 0).
5156 */
LL_RCC_PLL3Q_IsEnabled(void)5157 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
5158 {
5159 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == RCC_PLL3CFGR_PLL3QEN) ? 1UL : 0UL);
5160 }
5161
5162 /**
5163 * @brief Check if PLL3 R is enabled
5164 * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3R_IsEnabled
5165 * @retval State of bit (1 or 0).
5166 */
LL_RCC_PLL3R_IsEnabled(void)5167 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
5168 {
5169 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == RCC_PLL3CFGR_PLL3REN) ? 1UL : 0UL);
5170 }
5171
5172 /**
5173 * @brief Enable PLL3 FRACN
5174 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5175 * @retval None
5176 */
LL_RCC_PLL3FRACN_Enable(void)5177 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
5178 {
5179 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
5180 }
5181
5182 /**
5183 * @brief Check if PLL3 FRACN is enabled
5184 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
5185 * @retval State of bit (1 or 0).
5186 */
LL_RCC_PLL3FRACN_IsEnabled(void)5187 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
5188 {
5189 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL);
5190 }
5191
5192 /**
5193 * @brief Disable PLL3 FRACN
5194 * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable
5195 * @retval None
5196 */
LL_RCC_PLL3FRACN_Disable(void)5197 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5198 {
5199 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
5200 }
5201
5202 /**
5203 * @brief Set PLL3 FRACN Coefficient
5204 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN
5205 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5206 */
LL_RCC_PLL3_SetFRACN(uint32_t FRACN)5207 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5208 {
5209 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos);
5210 }
5211
5212 /**
5213 * @brief Get PLL3 FRACN Coefficient
5214 * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN
5215 * @retval A value between 0 and 8191 (0x1FFF)
5216 */
LL_RCC_PLL3_GetFRACN(void)5217 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5218 {
5219 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos);
5220 }
5221
5222 /**
5223 * @brief Set PLL3 VCO Input Range
5224 * @note This API shall be called only when PLL3 is disabled.
5225 * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
5226 * @param InputRange This parameter can be one of the following values:
5227 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5228 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5229 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5230 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5231 * @retval None
5232 */
LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)5233 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5234 {
5235 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos);
5236 }
5237
5238 /**
5239 * @brief Set PLL3 VCO OutputRange
5240 * @note This API shall be called only when PLL3 is disabled.
5241 * @rmtoll PLL3CFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOutputRange
5242 * @param VCORange This parameter can be one of the following values:
5243 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
5244 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5245 * @retval None
5246 */
LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)5247 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5248 {
5249 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3VCOSEL, VCORange << RCC_PLL3CFGR_PLL3VCOSEL_Pos);
5250 }
5251
5252 /**
5253 * @}
5254 */
5255 #endif /* PLL3 */
5256
5257 /** @defgroup RCC_LL_EF_PRIV Privileged mode
5258 * @{
5259 */
5260
5261 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5262 /**
5263 * @brief Enable Secure Privileged mode
5264 * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode
5265 * @retval None
5266 */
LL_RCC_EnableSecPrivilegedMode(void)5267 __STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void)
5268 {
5269 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
5270 }
5271
5272 /**
5273 * @brief Disable Secure Privileged mode
5274 * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode
5275 * @retval None
5276 */
LL_RCC_DisableSecPrivilegedMode(void)5277 __STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void)
5278 {
5279 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
5280 }
5281
5282 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
5283
5284 #if defined(RCC_PRIVCFGR_NSPRIV)
5285 /**
5286 * @brief Enable Non Secure Privileged mode
5287 * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode
5288 * @retval None
5289 */
LL_RCC_EnableNSecPrivilegedMode(void)5290 __STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void)
5291 {
5292 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
5293 }
5294
5295 /**
5296 * @brief Disable Non Secure Privileged mode
5297 * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode
5298 * @retval None
5299 */
LL_RCC_DisableNSecPrivilegedMode(void)5300 __STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void)
5301 {
5302 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
5303 }
5304
5305 /**
5306 * @brief Check if Secure Privileged mode has been enabled or not
5307 * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode
5308 * @retval State of bit (1 or 0).
5309 */
LL_RCC_IsEnabledSecPrivilegedMode(void)5310 __STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void)
5311 {
5312 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
5313 }
5314
5315 /**
5316 * @brief Check if Non Secure Privileged mode has been enabled or not
5317 * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode
5318 * @retval State of bit (1 or 0).
5319 */
LL_RCC_IsEnabledNSecPrivilegedMode(void)5320 __STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void)
5321 {
5322 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
5323 }
5324
5325 #else
5326 /**
5327 * @brief Enable Privileged mode
5328 * @rmtoll PRIVCFGR PRIV LL_RCC_EnablePrivilegedMode
5329 * @retval None
5330 */
LL_RCC_EnablePrivilegedMode(void)5331 __STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void)
5332 {
5333 SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV);
5334 }
5335
5336 /**
5337 * @brief Disable Privileged mode
5338 * @rmtoll PRIVCFGR PRIV LL_RCC_DisablePrivilegedMode
5339 * @retval None
5340 */
LL_RCC_DisablePrivilegedMode(void)5341 __STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void)
5342 {
5343 CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV);
5344 }
5345
5346 /**
5347 * @brief Check if Privileged mode has been enabled or not
5348 * @rmtoll PRIVCFGR PRIV LL_RCC_IsEnabledPrivilegedMode
5349 * @retval State of bit (1 or 0).
5350 */
LL_RCC_IsEnabledPrivilegedMode(void)5351 __STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void)
5352 {
5353 return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_PRIV) == RCC_PRIVCFGR_PRIV) ? 1UL : 0UL);
5354 }
5355
5356 #endif /* RCC_PRIVCFGR_NSPRIV */
5357
5358 /**
5359 * @}
5360 */
5361
5362 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5363 * @{
5364 */
5365
5366 /**
5367 * @brief Clear LSI ready interrupt flag
5368 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5369 * @retval None
5370 */
LL_RCC_ClearFlag_LSIRDY(void)5371 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5372 {
5373 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5374 }
5375
5376 /**
5377 * @brief Clear LSE ready interrupt flag
5378 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5379 * @retval None
5380 */
LL_RCC_ClearFlag_LSERDY(void)5381 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5382 {
5383 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5384 }
5385
5386 /**
5387 * @brief Clear CSI ready interrupt flag
5388 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5389 * @retval None
5390 */
LL_RCC_ClearFlag_CSIRDY(void)5391 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5392 {
5393 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5394 }
5395
5396 /**
5397 * @brief Clear HSI ready interrupt flag
5398 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5399 * @retval None
5400 */
LL_RCC_ClearFlag_HSIRDY(void)5401 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5402 {
5403 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5404 }
5405
5406 /**
5407 * @brief Clear HSE ready interrupt flag
5408 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5409 * @retval None
5410 */
LL_RCC_ClearFlag_HSERDY(void)5411 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5412 {
5413 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5414 }
5415
5416
5417 /**
5418 * @brief Clear HSI48 ready interrupt flag
5419 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5420 * @retval None
5421 */
LL_RCC_ClearFlag_HSI48RDY(void)5422 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5423 {
5424 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5425 }
5426
5427 /**
5428 * @brief Clear PLL1 ready interrupt flag
5429 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5430 * @retval None
5431 */
LL_RCC_ClearFlag_PLL1RDY(void)5432 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5433 {
5434 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
5435 }
5436
5437 /**
5438 * @brief Clear PLL2 ready interrupt flag
5439 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5440 * @retval None
5441 */
LL_RCC_ClearFlag_PLL2RDY(void)5442 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5443 {
5444 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5445 }
5446
5447 #if defined(RCC_CR_PLL3ON)
5448 /**
5449 * @brief Clear PLL3 ready interrupt flag
5450 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5451 * @retval None
5452 */
LL_RCC_ClearFlag_PLL3RDY(void)5453 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5454 {
5455 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5456 }
5457 #endif /* PLL3 */
5458
5459 /**
5460 * @brief Clear Clock security system interrupt flag
5461 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5462 * @retval None
5463 */
LL_RCC_ClearFlag_HSECSS(void)5464 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5465 {
5466 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5467 }
5468
5469 /**
5470 * @brief Check if LSI ready interrupt occurred or not
5471 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5472 * @retval State of bit (1 or 0).
5473 */
LL_RCC_IsActiveFlag_LSIRDY(void)5474 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5475 {
5476 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5477 }
5478
5479 /**
5480 * @brief Check if LSE ready interrupt occurred or not
5481 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5482 * @retval State of bit (1 or 0).
5483 */
LL_RCC_IsActiveFlag_LSERDY(void)5484 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5485 {
5486 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5487 }
5488
5489 /**
5490 * @brief Check if CSI ready interrupt occurred or not
5491 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5492 * @retval State of bit (1 or 0).
5493 */
LL_RCC_IsActiveFlag_CSIRDY(void)5494 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5495 {
5496 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == RCC_CIFR_CSIRDYF) ? 1UL : 0UL);
5497 }
5498
5499 /**
5500 * @brief Check if HSI ready interrupt occurred or not
5501 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5502 * @retval State of bit (1 or 0).
5503 */
LL_RCC_IsActiveFlag_HSIRDY(void)5504 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5505 {
5506 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5507 }
5508
5509 /**
5510 * @brief Check if HSE ready interrupt occurred or not
5511 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5512 * @retval State of bit (1 or 0).
5513 */
LL_RCC_IsActiveFlag_HSERDY(void)5514 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5515 {
5516 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5517 }
5518
5519 /**
5520 * @brief Check if HSI48 ready interrupt occurred or not
5521 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5522 * @retval State of bit (1 or 0).
5523 */
LL_RCC_IsActiveFlag_HSI48RDY(void)5524 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5525 {
5526 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5527 }
5528 /**
5529 * @brief Check if PLL1 ready interrupt occurred or not
5530 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
5531 * @retval State of bit (1 or 0).
5532 */
LL_RCC_IsActiveFlag_PLL1RDY(void)5533 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5534 {
5535 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
5536 }
5537
5538 /**
5539 * @brief Check if PLL2 ready interrupt occurred or not
5540 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5541 * @retval State of bit (1 or 0).
5542 */
LL_RCC_IsActiveFlag_PLL2RDY(void)5543 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5544 {
5545 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
5546 }
5547
5548 #if defined(RCC_CR_PLL3ON)
5549 /**
5550 * @brief Check if PLL3 ready interrupt occurred or not
5551 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5552 * @retval State of bit (1 or 0).
5553 */
LL_RCC_IsActiveFlag_PLL3RDY(void)5554 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5555 {
5556 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
5557 }
5558 #endif /* PLL3 */
5559
5560 /**
5561 * @brief Check if Clock security system interrupt occurred or not
5562 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5563 * @retval State of bit (1 or 0).
5564 */
LL_RCC_IsActiveFlag_HSECSS(void)5565 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5566 {
5567 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
5568 }
5569
5570 /**
5571 * @brief Check if RCC flag Independent Watchdog reset is set or not.
5572 * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
5573 * @retval State of bit (1 or 0).
5574 */
LL_RCC_IsActiveFlag_IWDGRST(void)5575 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5576 {
5577 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL);
5578 }
5579
5580 /**
5581 * @brief Check if RCC flag Low Power reset is set or not.
5582 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
5583 * @retval State of bit (1 or 0).
5584 */
LL_RCC_IsActiveFlag_LPWRRST(void)5585 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5586 {
5587 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL);
5588 }
5589
5590 /**
5591 * @brief Check if RCC flag Pin reset is set or not.
5592 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5593 * @retval State of bit (1 or 0).
5594 */
LL_RCC_IsActiveFlag_PINRST(void)5595 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5596 {
5597 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL);
5598 }
5599
5600 /**
5601 * @brief Check if RCC flag Software reset is set or not.
5602 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
5603 * @retval State of bit (1 or 0).
5604 */
LL_RCC_IsActiveFlag_SFTRST(void)5605 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5606 {
5607 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL);
5608 }
5609
5610 /**
5611 * @brief Check if RCC flag Window Watchdog reset is set or not.
5612 * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
5613 * @retval State of bit (1 or 0).
5614 */
LL_RCC_IsActiveFlag_WWDGRST(void)5615 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5616 {
5617 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL);
5618 }
5619
5620 /**
5621 * @brief Check if RCC flag BOR reset is set or not.
5622 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5623 * @retval State of bit (1 or 0).
5624 */
LL_RCC_IsActiveFlag_BORRST(void)5625 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5626 {
5627 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == RCC_RSR_BORRSTF) ? 1UL : 0UL);
5628 }
5629
5630 /**
5631 * @brief Set RMVF bit to clear the reset flags.
5632 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5633 * @retval None
5634 */
LL_RCC_ClearResetFlags(void)5635 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5636 {
5637 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5638 }
5639
5640 /**
5641 * @}
5642 */
5643
5644 /** @defgroup RCC_LL_EF_IT_Management IT Management
5645 * @{
5646 */
5647
5648 /**
5649 * @brief Enable LSI ready interrupt
5650 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5651 * @retval None
5652 */
LL_RCC_EnableIT_LSIRDY(void)5653 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5654 {
5655 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5656 }
5657
5658 /**
5659 * @brief Enable LSE ready interrupt
5660 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5661 * @retval None
5662 */
LL_RCC_EnableIT_LSERDY(void)5663 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5664 {
5665 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5666 }
5667
5668 /**
5669 * @brief Enable CSI ready interrupt
5670 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
5671 * @retval None
5672 */
LL_RCC_EnableIT_CSIRDY(void)5673 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
5674 {
5675 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5676 }
5677
5678 /**
5679 * @brief Enable HSI ready interrupt
5680 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5681 * @retval None
5682 */
LL_RCC_EnableIT_HSIRDY(void)5683 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5684 {
5685 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5686 }
5687
5688 /**
5689 * @brief Enable HSE ready interrupt
5690 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5691 * @retval None
5692 */
LL_RCC_EnableIT_HSERDY(void)5693 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5694 {
5695 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5696 }
5697
5698 /**
5699 * @brief Enable HSI48 ready interrupt
5700 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
5701 * @retval None
5702 */
LL_RCC_EnableIT_HSI48RDY(void)5703 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5704 {
5705 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5706 }
5707
5708 /**
5709 * @brief Enable PLL1 ready interrupt
5710 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
5711 * @retval None
5712 */
LL_RCC_EnableIT_PLL1RDY(void)5713 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
5714 {
5715 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5716 }
5717
5718 /**
5719 * @brief Enable PLL2 ready interrupt
5720 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
5721 * @retval None
5722 */
LL_RCC_EnableIT_PLL2RDY(void)5723 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
5724 {
5725 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5726 }
5727
5728 #if defined(RCC_CR_PLL3ON)
5729 /**
5730 * @brief Enable PLL3 ready interrupt
5731 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
5732 * @retval None
5733 */
LL_RCC_EnableIT_PLL3RDY(void)5734 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
5735 {
5736 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5737 }
5738 #endif /* PLL3 */
5739
5740 /**
5741 * @brief Disable LSI ready interrupt
5742 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
5743 * @retval None
5744 */
LL_RCC_DisableIT_LSIRDY(void)5745 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5746 {
5747 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5748 }
5749
5750 /**
5751 * @brief Disable LSE ready interrupt
5752 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
5753 * @retval None
5754 */
LL_RCC_DisableIT_LSERDY(void)5755 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5756 {
5757 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5758 }
5759
5760 /**
5761 * @brief Disable CSI ready interrupt
5762 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
5763 * @retval None
5764 */
LL_RCC_DisableIT_CSIRDY(void)5765 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
5766 {
5767 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5768 }
5769
5770 /**
5771 * @brief Disable HSI ready interrupt
5772 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
5773 * @retval None
5774 */
LL_RCC_DisableIT_HSIRDY(void)5775 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5776 {
5777 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5778 }
5779
5780 /**
5781 * @brief Disable HSE ready interrupt
5782 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
5783 * @retval None
5784 */
LL_RCC_DisableIT_HSERDY(void)5785 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5786 {
5787 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5788 }
5789
5790 /**
5791 * @brief Disable HSI48 ready interrupt
5792 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
5793 * @retval None
5794 */
LL_RCC_DisableIT_HSI48RDY(void)5795 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
5796 {
5797 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5798 }
5799
5800 /**
5801 * @brief Disable PLL1 ready interrupt
5802 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
5803 * @retval None
5804 */
LL_RCC_DisableIT_PLL1RDY(void)5805 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
5806 {
5807 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5808 }
5809
5810 /**
5811 * @brief Disable PLL2 ready interrupt
5812 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
5813 * @retval None
5814 */
LL_RCC_DisableIT_PLL2RDY(void)5815 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
5816 {
5817 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5818 }
5819
5820 #if defined(RCC_CR_PLL3ON)
5821 /**
5822 * @brief Disable PLL3 ready interrupt
5823 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
5824 * @retval None
5825 */
LL_RCC_DisableIT_PLL3RDY(void)5826 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
5827 {
5828 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5829 }
5830 #endif /* PLL3 */
5831
5832 /**
5833 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5834 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5835 * @retval State of bit (1 or 0).
5836 */
LL_RCC_IsEnabledIT_LSIRDY(void)5837 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5838 {
5839 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
5840 }
5841
5842 /**
5843 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5844 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5845 * @retval State of bit (1 or 0).
5846 */
LL_RCC_IsEnabledIT_LSERDY(void)5847 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5848 {
5849 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
5850 }
5851
5852 /**
5853 * @brief Checks if CSI ready interrupt source is enabled or disabled.
5854 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnabledIT_CSIRDY
5855 * @retval State of bit (1 or 0).
5856 */
LL_RCC_IsEnabledIT_CSIRDY(void)5857 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_CSIRDY(void)
5858 {
5859 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
5860 }
5861
5862 /**
5863 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5864 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5865 * @retval State of bit (1 or 0).
5866 */
LL_RCC_IsEnabledIT_HSIRDY(void)5867 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5868 {
5869 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
5870 }
5871
5872 /**
5873 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5874 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5875 * @retval State of bit (1 or 0).
5876 */
LL_RCC_IsEnabledIT_HSERDY(void)5877 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5878 {
5879 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
5880 }
5881
5882 /**
5883 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
5884 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
5885 * @retval State of bit (1 or 0).
5886 */
LL_RCC_IsEnabledIT_HSI48RDY(void)5887 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
5888 {
5889 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
5890 }
5891 /**
5892 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
5893 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
5894 * @retval State of bit (1 or 0).
5895 */
LL_RCC_IsEnabledIT_PLL1RDY(void)5896 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
5897 {
5898 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
5899 }
5900
5901 /**
5902 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
5903 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
5904 * @retval State of bit (1 or 0).
5905 */
LL_RCC_IsEnabledIT_PLL2RDY(void)5906 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
5907 {
5908 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
5909 }
5910
5911 #if defined(RCC_CR_PLL3ON)
5912 /**
5913 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
5914 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY
5915 * @retval State of bit (1 or 0).
5916 */
LL_RCC_IsEnabledIT_PLL3RDY(void)5917 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
5918 {
5919 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
5920 }
5921 #endif /* PLL3 */
5922
5923 /**
5924 * @}
5925 */
5926
5927 /** @defgroup RCC_LL_EF_Security_Services Security Services
5928 * @{
5929 */
5930
5931 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
5932 /**
5933 * @brief Configure RCC resources security
5934 * @note Only available from secure state when system implements security (TZEN=1)
5935 * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
5936 * SECCFGR HSESEC LL_RCC_ConfigSecure\n
5937 * SECCFGR CSISEC LL_RCC_ConfigSecure\n
5938 * SECCFGR LSISEC LL_RCC_ConfigSecure\n
5939 * SECCFGR LSESEC LL_RCC_ConfigSecure\n
5940 * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
5941 * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
5942 * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
5943 * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n
5944 * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n
5945 * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n
5946 * SECCFGR RMVFSEC LL_RCC_ConfigSecure\n
5947 * SECCFGR CKPERSELSEC LL_RCC_ConfigSecure
5948 * @param Configuration This parameter shall be the full combination of the following values:
5949 * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC
5950 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
5951 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
5952 * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC
5953 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
5954 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
5955 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
5956 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
5957 * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC
5958 * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC
5959 * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC
5960 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
5961 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
5962 * @arg @ref LL_RCC_CKPERSEL_SEC or LL_RCC_CKPERSEL_NSEC
5963 * @retval None
5964 */
LL_RCC_ConfigSecure(uint32_t Configuration)5965 __STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t Configuration)
5966 {
5967 WRITE_REG(RCC->SECCFGR, Configuration);
5968 }
5969 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
5970
5971 #if defined(RCC_SECCFGR_HSISEC)
5972 /**
5973 * @brief Get RCC resources security status
5974 * @note Only available from secure state when system implements security (TZEN=1)
5975 * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
5976 * SECCFGR HSESEC LL_RCC_GetConfigSecure\n
5977 * SECCFGR CSISEC LL_RCC_GetConfigSecure\n
5978 * SECCFGR LSISEC LL_RCC_GetConfigSecure\n
5979 * SECCFGR LSESEC LL_RCC_GetConfigSecure\n
5980 * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
5981 * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
5982 * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
5983 * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n
5984 * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n
5985 * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n
5986 * SECCFGR RMVFSEC LL_RCC_GetConfigSecure\n
5987 * SECCFGR CKPERSELSEC LL_RCC_GetConfigSecure
5988 * @retval Returned value is the combination of the following values:
5989 * @arg @ref LL_RCC_ALL_SEC or LL_RCC_ALL_NSEC
5990 * @arg @ref LL_RCC_HSI_SEC or LL_RCC_HSI_NSEC
5991 * @arg @ref LL_RCC_HSE_SEC or LL_RCC_HSE_NSEC
5992 * @arg @ref LL_RCC_CSI_SEC or LL_RCC_CSI_NSEC
5993 * @arg @ref LL_RCC_LSE_SEC or LL_RCC_LSE_NSEC
5994 * @arg @ref LL_RCC_LSI_SEC or LL_RCC_LSI_NSEC
5995 * @arg @ref LL_RCC_SYSCLK_SEC or LL_RCC_SYSCLK_NSEC
5996 * @arg @ref LL_RCC_PRESCALERS_SEC or LL_RCC_PRESCALERS_NSEC
5997 * @arg @ref LL_RCC_PLL1_SEC or LL_RCC_PLL1_NSEC
5998 * @arg @ref LL_RCC_PLL2_SEC or LL_RCC_PLL2_NSEC
5999 * @arg @ref LL_RCC_PLL3_SEC or LL_RCC_PLL3_NSEC
6000 * @arg @ref LL_RCC_HSI48_SEC or LL_RCC_HSI48_NSEC
6001 * @arg @ref LL_RCC_RESET_FLAGS_SEC or LL_RCC_RESET_FLAGS_NSEC
6002 * @arg @ref LL_RCC_CKPERSEL_SEC or LL_RCC_CKPERSEL_NSEC
6003 * @retval None
6004 */
LL_RCC_GetConfigSecure(void)6005 __STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
6006 {
6007 return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
6008 }
6009 #endif /* RCC_SECCFGR_HSISEC */
6010
6011 /**
6012 * @}
6013 */
6014
6015 #if defined(USE_FULL_LL_DRIVER)
6016 /** @defgroup RCC_LL_EF_Init De-initialization function
6017 * @{
6018 */
6019 ErrorStatus LL_RCC_DeInit(void);
6020 /**
6021 * @}
6022 */
6023
6024 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6025 * @{
6026 */
6027
6028 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6029
6030 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6031 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6032 #if defined(RCC_CR_PLL3ON)
6033 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks);
6034 #endif /* PLL3 */
6035 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *pRCC_Clocks);
6036 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6037 #if defined(UART4)
6038 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
6039 #endif /* UART4 */
6040 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6041 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource);
6042 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6043 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6044 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6045 #if defined (SAI1)
6046 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6047 #endif /* SAI1 */
6048 #if defined(SDMMC1)
6049 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6050 #endif /* SDMMC1 */
6051 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6052 #if defined(USB_DRD_FS)
6053 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6054 #endif /* USB_DRD_FS */
6055 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource);
6056 uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource);
6057 #if defined(OCTOSPI1)
6058 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
6059 #endif /* OCTOSPI1 */
6060 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6061 #if defined(CEC)
6062 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6063 #endif /* CEC */
6064 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6065 /**
6066 * @}
6067 */
6068
6069 #endif /* USE_FULL_LL_DRIVER */
6070
6071 /**
6072 * @}
6073 */
6074
6075 /**
6076 * @}
6077 */
6078
6079 #endif /* defined(RCC) */
6080
6081 /**
6082 * @}
6083 */
6084
6085 #ifdef __cplusplus
6086 }
6087 #endif
6088
6089 #endif /* __STM32H5xx_LL_RCC_H */
6090
