1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_RCC_H 21 #define STM32N6xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 #include "stm32n6xx_ll_bus.h" 30 #include "stm32n6xx_ll_rcc.h" 31 32 /** @addtogroup STM32N6xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup RCC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup RCC_Exported_Types RCC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief RCC PLL configuration structure definition 48 * (allow to configure the PLL in integer and fractional modes) 49 * Only PLLState field is applicable when its value is different from RCC_PLL_ON 50 */ 51 typedef struct 52 { 53 uint32_t PLLState; /*!< The new state of the PLL. 54 This parameter can be a value of @ref RCC_PLL_Config */ 55 56 uint32_t PLLSource; /*!< PLL entry clock source. 57 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 58 59 uint32_t PLLM; /*!< Division factor M for PLL VCO input clock. 60 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 61 62 uint32_t PLLFractional; /*!< Fractional part of he VCO mulliplication factor. 63 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFFFF */ 64 65 uint32_t PLLN; /*!< Multiplication factor N for PLL VCO output clock. 66 In integer mode, this parameter must be a number between Min_Data = 10 and Max_Data = 2500. 67 In fractional mode, this parameter must be a number between Min_Data = 20 and Max_Data = 500.*/ 68 69 uint32_t PLLP1; /*!< Division factor P1 for system clock. 70 This parameter must be a number between Min_Data = 1 and Max_Data = 7 */ 71 72 uint32_t PLLP2; /*!< Division factor P2 for system clock. 73 This parameter must be a number between Min_Data = 1 and Max_Data = 7 */ 74 75 } RCC_PLLInitTypeDef; 76 77 /** 78 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) and PLLs configuration structure definition 79 */ 80 typedef struct 81 { 82 uint32_t OscillatorType; /*!< The oscillators to be configured. 83 This parameter can be a value of @ref RCC_Oscillator_Type */ 84 85 uint32_t HSEState; /*!< The new state of the HSE. 86 This parameter can be a value of @ref RCC_HSE_Config */ 87 88 uint32_t LSEState; /*!< The new state of the LSE. 89 This parameter can be a value of @ref RCC_LSE_Config */ 90 91 uint32_t HSIState; /*!< The new state of the HSI. 92 This parameter can be a value of @ref RCC_HSI_Config */ 93 94 uint32_t HSIDiv; /*!< The division factor of the HSI. 95 This parameter can be a value of @ref RCC_HSI_Div */ 96 97 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 98 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 99 100 uint32_t LSIState; /*!< The new state of the LSI. 101 This parameter can be a value of @ref RCC_LSI_Config */ 102 103 uint32_t MSIState; /*!< The new state of the MSI. 104 This parameter can be a value of @ref RCC_MSI_Config */ 105 106 uint32_t MSIFrequency; /*!< The MSI frequency selection. 107 This parameter can be a value of @ref RCC_MSI_Frequency */ 108 109 uint32_t MSICalibrationValue; /*!< The calibration trimming value. 110 This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ 111 112 RCC_PLLInitTypeDef PLL1; /*!< PLL1 structure parameters */ 113 114 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ 115 116 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ 117 118 RCC_PLLInitTypeDef PLL4; /*!< PLL4 structure parameters */ 119 120 } RCC_OscInitTypeDef; 121 122 /** 123 * @brief RCC extended interconnection structure definition 124 */ 125 typedef struct 126 { 127 uint32_t ClockSelection; /*!< Specifies ICx clock source. 128 This parameter can be a value of @ref RCC_IC_Clock_Source */ 129 130 uint32_t ClockDivider; /*!< Specifies ICx clock divider. 131 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 132 } RCC_ICInitTypeDef; 133 134 /** 135 * @brief RCC System, AHB and APB busses clock configuration structure definition 136 */ 137 typedef struct 138 { 139 uint32_t ClockType; /*!< The clock to be configured. 140 This parameter can be a value of @ref RCC_Clock_Type */ 141 142 uint32_t CPUCLKSource; /*!< The clock source used as CPU clock (CPUCLK). 143 This parameter can be a value of @ref RCC_CPU_Clock_Source */ 144 145 uint32_t SYSCLKSource; /*!< The clock source used as system bus clock (SYSCLK). 146 This parameter can be a value of @ref RCC_System_Bus_Clock_Source */ 147 148 uint32_t AHBCLKDivider; /*!< The AHB clock divider for HCLK. 149 This clock is derived from the system clock divided by the system clock divider. 150 This parameter can be a value of @ref RCC_HCLK_Clock_Source */ 151 152 uint32_t APB1CLKDivider; /*!< The APB1 clock divider for PCLK1. 153 This clock is derived from the AHB clock (HCLK). 154 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 155 156 uint32_t APB2CLKDivider; /*!< The APB2 clock divider for PCLK2. 157 This clock is derived from the AHB clock (HCLK). 158 This parameter can be a value of @ref RCC_APB2_Clock_Source */ 159 160 uint32_t APB4CLKDivider; /*!< The APB4 clock divider for PCLK4. 161 This clock is derived from the AHB clock (HCLK). 162 This parameter can be a value of @ref RCC_APB4_Clock_Source */ 163 164 uint32_t APB5CLKDivider; /*!< The APB5 clock divider for PCLK5. 165 This clock is derived from the AHB clock (HCLK). 166 This parameter can be a value of @ref RCC_APB5_Clock_Source */ 167 168 RCC_ICInitTypeDef IC1Selection; /*!< IC1 parameters. 169 This parameter shall be used when IC1 is selected as CPU clock source (sysa_ck) */ 170 171 RCC_ICInitTypeDef IC2Selection; /*!< IC2 parameters. 172 This parameter shall be used when IC2 is selected as system bus clock source (sysb_ck) */ 173 174 RCC_ICInitTypeDef IC6Selection; /*!< IC6 parameters. 175 This parameter shall be used when IC6 is selected as system bus clock source (sysc_ck) */ 176 177 RCC_ICInitTypeDef IC11Selection; /*!< IC11 parameters. 178 This parameter shall be used when IC11 is selected as system bus clock source (sysd_ck) */ 179 } RCC_ClkInitTypeDef; 180 181 /** 182 * @} 183 */ 184 185 /* Exported constants --------------------------------------------------------*/ 186 187 /** @defgroup RCC_Exported_Constants RCC Exported Constants 188 * @{ 189 */ 190 191 /** @defgroup RCC_Oscillator_Type Oscillator Type 192 * @{ 193 */ 194 #define RCC_OSCILLATORTYPE_NONE 0x00U /*!< Oscillator configuration unchanged */ 195 #define RCC_OSCILLATORTYPE_HSE 0x01U /*!< HSE selected */ 196 #define RCC_OSCILLATORTYPE_HSI 0x02U /*!< HSI selected */ 197 #define RCC_OSCILLATORTYPE_LSE 0x04U /*!< LSE selected */ 198 #define RCC_OSCILLATORTYPE_LSI 0x08U /*!< LSI selected */ 199 #define RCC_OSCILLATORTYPE_MSI 0x10U /*!< MSI selected */ 200 /** 201 * @} 202 */ 203 204 /** @defgroup RCC_HSE_Config HSE Config 205 * @{ 206 */ 207 #define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ 208 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 209 #define RCC_HSE_BYPASS (RCC_HSECFGR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass analog clock activation */ 210 #define RCC_HSE_BYPASS_DIGITAL (RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass digital clock activation */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup RCC_LSE_Config LSE Config 216 * @{ 217 */ 218 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 219 #define RCC_LSE_ON RCC_CR_LSEON /*!< LSE clock activation */ 220 #define RCC_LSE_BYPASS (RCC_LSECFGR_LSEBYP | RCC_CR_LSEON) /*!< LSE bypass analog clock activation */ 221 #define RCC_LSE_BYPASS_DIGITAL (RCC_LSECFGR_LSEEXT | RCC_LSECFGR_LSEBYP | RCC_CR_LSEON) /*!< LSE bypass digital clock activation */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup RCC_HSI_Config HSI Config 227 * @{ 228 */ 229 #define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ 230 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup RCC_HSI_Div HSI Clock Divider 236 * @{ 237 */ 238 #define RCC_HSI_DIV1 LL_RCC_HSI_DIV_1 /*!< HSI clock is not divided */ 239 #define RCC_HSI_DIV2 LL_RCC_HSI_DIV_2 /*!< HSI clock is divided by 2 */ 240 #define RCC_HSI_DIV4 LL_RCC_HSI_DIV_4 /*!< HSI clock is divided by 4 */ 241 #define RCC_HSI_DIV8 LL_RCC_HSI_DIV_8 /*!< HSI clock is divided by 8 */ 242 /** 243 * @} 244 */ 245 246 /** @defgroup RCC_HSI_Calibration_Default HSI Calibration default 247 * @{ 248 */ 249 #define RCC_HSICALIBRATION_DEFAULT 0U /*!< Default HSI calibration trimming value */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup RCC_LSI_Config LSI Config 255 * @{ 256 */ 257 #define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ 258 #define RCC_LSI_ON RCC_CR_LSION /*!< LSI clock activation */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup RCC_MSI_Config MSI Config 264 * @{ 265 */ 266 #define RCC_MSI_OFF 0U /*!< MSI clock deactivation */ 267 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup RCC_MSI_Frequency MSI Frequency 273 * @{ 274 */ 275 #define RCC_MSI_FREQ_4MHZ LL_RCC_MSI_FREQ_4MHZ /*!< MSI 4MHz selection */ 276 #define RCC_MSI_FREQ_16MHZ LL_RCC_MSI_FREQ_16MHZ /*!< MSI 16MHz selection */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup RCC_MSI_Calibration_Default MSI Calibration default 282 * @{ 283 */ 284 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup RCC_PLL_Config PLL Config 290 * @{ 291 */ 292 #define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ 293 #define RCC_PLL_OFF 1U /*!< PLL deactivation */ 294 #define RCC_PLL_ON 2U /*!< PLL activation */ 295 #define RCC_PLL_BYPASS 3U /*!< PLL activation in bypass mode with FREF set as source */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 301 * @{ 302 */ 303 #define RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSI /*!< HSI clock selected as PLL entry clock source */ 304 #define RCC_PLLSOURCE_MSI LL_RCC_PLLSOURCE_MSI /*!< MSI clock selected as PLL entry clock source */ 305 #define RCC_PLLSOURCE_HSE LL_RCC_PLLSOURCE_HSE /*!< HSE clock selected as PLL entry clock source */ 306 #define RCC_PLLSOURCE_PIN LL_RCC_PLLSOURCE_I2S_CKIN /*!< External clock I2S_CKIN selected as PLL entry clock source */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup RCC_Clock_Type Clock Type 312 * @{ 313 */ 314 #define RCC_CLOCKTYPE_CPUCLK 0x01U /*!< CPU clock to configure */ 315 #define RCC_CLOCKTYPE_SYSCLK 0x02U /*!< System bus clock to configure for AXI */ 316 #define RCC_CLOCKTYPE_HCLK 0x04U /*!< HCLK to configure for AHB */ 317 #define RCC_CLOCKTYPE_PCLK1 0x08U /*!< PCLK1 to configure for APB1 */ 318 #define RCC_CLOCKTYPE_PCLK2 0x10U /*!< PCLK2 to configure for APB2 */ 319 #define RCC_CLOCKTYPE_PCLK4 0x20U /*!< PCLK4 to configure for APB4 */ 320 #define RCC_CLOCKTYPE_PCLK5 0x40U /*!< PCLK5 to configure for APB5 */ 321 /** 322 * @} 323 */ 324 325 /** @defgroup RCC_CPU_Clock_Source CPU Clock Source 326 * @{ 327 */ 328 #define RCC_CPUCLKSOURCE_HSI LL_RCC_CPU_CLKSOURCE_HSI /*!< HSI selection as CPU clock */ 329 #define RCC_CPUCLKSOURCE_MSI LL_RCC_CPU_CLKSOURCE_MSI /*!< MSI selection as CPU clock */ 330 #define RCC_CPUCLKSOURCE_HSE LL_RCC_CPU_CLKSOURCE_HSE /*!< HSE selection as CPU clock */ 331 #define RCC_CPUCLKSOURCE_IC1 LL_RCC_CPU_CLKSOURCE_IC1 /*!< IC1 selection as CPU clock */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_CPU_Clock_Source_Status CPU Clock Source Status 337 * @{ 338 */ 339 #define RCC_CPUCLKSOURCE_STATUS_HSI LL_RCC_CPU_CLKSOURCE_STATUS_HSI /*!< HSI used as CPU clock */ 340 #define RCC_CPUCLKSOURCE_STATUS_MSI LL_RCC_CPU_CLKSOURCE_STATUS_MSI /*!< MSI used as CPU clock */ 341 #define RCC_CPUCLKSOURCE_STATUS_HSE LL_RCC_CPU_CLKSOURCE_STATUS_HSE /*!< HSE used as CPU clock */ 342 #define RCC_CPUCLKSOURCE_STATUS_IC1 LL_RCC_CPU_CLKSOURCE_STATUS_IC1 /*!< IC1 used as CPU clock */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup RCC_System_Bus_Clock_Source System Bus Clock Source 348 * @{ 349 */ 350 #define RCC_SYSCLKSOURCE_HSI LL_RCC_SYS_CLKSOURCE_HSI /*!< HSI selection as system bus clocks */ 351 #define RCC_SYSCLKSOURCE_MSI LL_RCC_SYS_CLKSOURCE_MSI /*!< MSI selection as system bus clocks */ 352 #define RCC_SYSCLKSOURCE_HSE LL_RCC_SYS_CLKSOURCE_HSE /*!< HSE selection as system bus clocks */ 353 #define RCC_SYSCLKSOURCE_IC2_IC6_IC11 LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11 /*!< IC2/IC6/IC11 selection as system bus clocks */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup RCC_System_Bus_Clock_Source_Status System Bus Clock Source Status 359 * @{ 360 */ 361 #define RCC_SYSCLKSOURCE_STATUS_HSI LL_RCC_SYS_CLKSOURCE_STATUS_HSI /*!< HSI used as system bus clocks */ 362 #define RCC_SYSCLKSOURCE_STATUS_MSI LL_RCC_SYS_CLKSOURCE_STATUS_MSI /*!< MSI used as system bus clocks */ 363 #define RCC_SYSCLKSOURCE_STATUS_HSE LL_RCC_SYS_CLKSOURCE_STATUS_HSE /*!< HSE used as system bus clocks */ 364 #define RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11 LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11 /*!< IC2/IC6/IC11 used as system bus clocks */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup RCC_HCLK_Clock_Source HCLK Clock Source 370 * @{ 371 */ 372 #define RCC_HCLK_DIV1 LL_RCC_AHB_DIV_1 /*!< HCLK not divided */ 373 #define RCC_HCLK_DIV2 LL_RCC_AHB_DIV_2 /*!< HCLK divided by 2 */ 374 #define RCC_HCLK_DIV4 LL_RCC_AHB_DIV_4 /*!< HCLK divided by 4 */ 375 #define RCC_HCLK_DIV8 LL_RCC_AHB_DIV_8 /*!< HCLK divided by 8 */ 376 #define RCC_HCLK_DIV16 LL_RCC_AHB_DIV_16 /*!< HCLK divided by 16 */ 377 #define RCC_HCLK_DIV32 LL_RCC_AHB_DIV_32 /*!< HCLK divided by 32 */ 378 #define RCC_HCLK_DIV64 LL_RCC_AHB_DIV_64 /*!< HCLK divided by 64 */ 379 #define RCC_HCLK_DIV128 LL_RCC_AHB_DIV_128 /*!< HCLK divided by 128 */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup RCC_APB1_Clock_Source APB1 Clock Source 385 * @{ 386 */ 387 #define RCC_APB1_DIV1 LL_RCC_APB1_DIV_1 /*!< APB1 not divided */ 388 #define RCC_APB1_DIV2 LL_RCC_APB1_DIV_2 /*!< APB1 divided by 2 */ 389 #define RCC_APB1_DIV4 LL_RCC_APB1_DIV_4 /*!< APB1 divided by 4 */ 390 #define RCC_APB1_DIV8 LL_RCC_APB1_DIV_8 /*!< APB1 divided by 8 */ 391 #define RCC_APB1_DIV16 LL_RCC_APB1_DIV_16 /*!< APB1 divided by 16 */ 392 #define RCC_APB1_DIV32 LL_RCC_APB1_DIV_32 /*!< APB1 divided by 32 */ 393 #define RCC_APB1_DIV64 LL_RCC_APB1_DIV_64 /*!< APB1 divided by 64 */ 394 #define RCC_APB1_DIV128 LL_RCC_APB1_DIV_128 /*!< APB1 divided by 128 */ 395 /** 396 * @} 397 */ 398 399 /** @defgroup RCC_APB2_Clock_Source APB2 Clock Source 400 * @{ 401 */ 402 #define RCC_APB2_DIV1 LL_RCC_APB2_DIV_1 /*!< APB2 not divided */ 403 #define RCC_APB2_DIV2 LL_RCC_APB2_DIV_2 /*!< APB2 divided by 2 */ 404 #define RCC_APB2_DIV4 LL_RCC_APB2_DIV_4 /*!< APB2 divided by 4 */ 405 #define RCC_APB2_DIV8 LL_RCC_APB2_DIV_8 /*!< APB2 divided by 8 */ 406 #define RCC_APB2_DIV16 LL_RCC_APB2_DIV_16 /*!< APB2 divided by 16 */ 407 #define RCC_APB2_DIV32 LL_RCC_APB2_DIV_32 /*!< APB2 divided by 32 */ 408 #define RCC_APB2_DIV64 LL_RCC_APB2_DIV_64 /*!< APB2 divided by 64 */ 409 #define RCC_APB2_DIV128 LL_RCC_APB2_DIV_128 /*!< APB2 divided by 128 */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup RCC_APB4_Clock_Source APB4 Clock Source 415 * @{ 416 */ 417 #define RCC_APB4_DIV1 LL_RCC_APB4_DIV_1 /*!< APB4 not divided */ 418 #define RCC_APB4_DIV2 LL_RCC_APB4_DIV_2 /*!< APB4 divided by 2 */ 419 #define RCC_APB4_DIV4 LL_RCC_APB4_DIV_4 /*!< APB4 divided by 4 */ 420 #define RCC_APB4_DIV8 LL_RCC_APB4_DIV_8 /*!< APB4 divided by 8 */ 421 #define RCC_APB4_DIV16 LL_RCC_APB4_DIV_16 /*!< APB4 divided by 16 */ 422 #define RCC_APB4_DIV32 LL_RCC_APB4_DIV_32 /*!< APB4 divided by 32 */ 423 #define RCC_APB4_DIV64 LL_RCC_APB4_DIV_64 /*!< APB4 divided by 64 */ 424 #define RCC_APB4_DIV128 LL_RCC_APB4_DIV_128 /*!< APB4 divided by 128 */ 425 /** 426 * @} 427 */ 428 429 /** @defgroup RCC_APB5_Clock_Source APB5 Clock Source 430 * @{ 431 */ 432 #define RCC_APB5_DIV1 LL_RCC_APB5_DIV_1 /*!< APB5 not divided */ 433 #define RCC_APB5_DIV2 LL_RCC_APB5_DIV_2 /*!< APB5 divided by 2 */ 434 #define RCC_APB5_DIV4 LL_RCC_APB5_DIV_4 /*!< APB5 divided by 4 */ 435 #define RCC_APB5_DIV8 LL_RCC_APB5_DIV_8 /*!< APB5 divided by 8 */ 436 #define RCC_APB5_DIV16 LL_RCC_APB5_DIV_16 /*!< APB5 divided by 16 */ 437 #define RCC_APB5_DIV32 LL_RCC_APB5_DIV_32 /*!< APB5 divided by 32 */ 438 #define RCC_APB5_DIV64 LL_RCC_APB5_DIV_64 /*!< APB5 divided by 64 */ 439 #define RCC_APB5_DIV128 LL_RCC_APB5_DIV_128 /*!< APB5 divided by 128 */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCC_IC_Clock_Source IC Clock Source 445 * @{ 446 */ 447 #define RCC_ICCLKSOURCE_PLL1 LL_RCC_ICCLKSOURCE_PLL1 /*!< ICx clock source selection is PLL1 output */ 448 #define RCC_ICCLKSOURCE_PLL2 LL_RCC_ICCLKSOURCE_PLL2 /*!< ICx clock source selection is PLL2 output */ 449 #define RCC_ICCLKSOURCE_PLL3 LL_RCC_ICCLKSOURCE_PLL3 /*!< ICx clock source selection is PLL3 output */ 450 #define RCC_ICCLKSOURCE_PLL4 LL_RCC_ICCLKSOURCE_PLL4 /*!< ICx clock source selection is PLL4 output */ 451 /** 452 * @} 453 */ 454 455 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 456 * @{ 457 */ 458 #define RCC_RTCCLKSOURCE_DISABLE 0U /*!< No clock used as RTC clock */ 459 #define RCC_RTCCLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 460 #define RCC_RTCCLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 461 #define RCC_RTCCLKSOURCE_HSE_DIV1 ((0x00U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1 used as RTC clock */ 462 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((0x01U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2 used as RTC clock */ 463 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((0x02U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3 used as RTC clock */ 464 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x03U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ 465 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((0x04U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 5 used as RTC clock */ 466 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((0x05U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 6 used as RTC clock */ 467 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((0x06U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 7 used as RTC clock */ 468 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((0x07U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 8 used as RTC clock */ 469 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x08U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ 470 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((0x09U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 10 used as RTC clock */ 471 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((0x0AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 11 used as RTC clock */ 472 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((0x0BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 12 used as RTC clock */ 473 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((0x0CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 13 used as RTC clock */ 474 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((0x0DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 14 used as RTC clock */ 475 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((0x0EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 15 used as RTC clock */ 476 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x0FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ 477 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((0x10U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 17 used as RTC clock */ 478 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((0x11U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 18 used as RTC clock */ 479 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((0x12U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 19 used as RTC clock */ 480 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((0x13U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 20 used as RTC clock */ 481 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((0x14U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 21 used as RTC clock */ 482 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((0x15U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 22 used as RTC clock */ 483 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((0x16U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 23 used as RTC clock */ 484 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((0x17U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 24 used as RTC clock */ 485 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x18U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ 486 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((0x19U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 26 used as RTC clock */ 487 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((0x1AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 27 used as RTC clock */ 488 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((0x1BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 28 used as RTC clock */ 489 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((0x1CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 29 used as RTC clock */ 490 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((0x1DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 30 used as RTC clock */ 491 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((0x1EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 31 used as RTC clock */ 492 #define RCC_RTCCLKSOURCE_HSE_DIV32 ((0x1FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 493 #define RCC_RTCCLKSOURCE_HSE_DIV33 ((0x20U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 33 used as RTC clock */ 494 #define RCC_RTCCLKSOURCE_HSE_DIV34 ((0x21U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 34 used as RTC clock */ 495 #define RCC_RTCCLKSOURCE_HSE_DIV35 ((0x22U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 35 used as RTC clock */ 496 #define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x23U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ 497 #define RCC_RTCCLKSOURCE_HSE_DIV37 ((0x24U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 37 used as RTC clock */ 498 #define RCC_RTCCLKSOURCE_HSE_DIV38 ((0x25U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 38 used as RTC clock */ 499 #define RCC_RTCCLKSOURCE_HSE_DIV39 ((0x26U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 39 used as RTC clock */ 500 #define RCC_RTCCLKSOURCE_HSE_DIV40 ((0x27U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 40 used as RTC clock */ 501 #define RCC_RTCCLKSOURCE_HSE_DIV41 ((0x28U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 41 used as RTC clock */ 502 #define RCC_RTCCLKSOURCE_HSE_DIV42 ((0x29U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 42 used as RTC clock */ 503 #define RCC_RTCCLKSOURCE_HSE_DIV43 ((0x2AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 43 used as RTC clock */ 504 #define RCC_RTCCLKSOURCE_HSE_DIV44 ((0x2BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 44 used as RTC clock */ 505 #define RCC_RTCCLKSOURCE_HSE_DIV45 ((0x2CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 45 used as RTC clock */ 506 #define RCC_RTCCLKSOURCE_HSE_DIV46 ((0x2DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 46 used as RTC clock */ 507 #define RCC_RTCCLKSOURCE_HSE_DIV47 ((0x2EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 47 used as RTC clock */ 508 #define RCC_RTCCLKSOURCE_HSE_DIV48 ((0x2FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 48 used as RTC clock */ 509 #define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x30U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ 510 #define RCC_RTCCLKSOURCE_HSE_DIV50 ((0x31U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 50 used as RTC clock */ 511 #define RCC_RTCCLKSOURCE_HSE_DIV51 ((0x32U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 51 used as RTC clock */ 512 #define RCC_RTCCLKSOURCE_HSE_DIV52 ((0x33U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 52 used as RTC clock */ 513 #define RCC_RTCCLKSOURCE_HSE_DIV53 ((0x34U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 53 used as RTC clock */ 514 #define RCC_RTCCLKSOURCE_HSE_DIV54 ((0x35U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 54 used as RTC clock */ 515 #define RCC_RTCCLKSOURCE_HSE_DIV55 ((0x36U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 55 used as RTC clock */ 516 #define RCC_RTCCLKSOURCE_HSE_DIV56 ((0x37U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 56 used as RTC clock */ 517 #define RCC_RTCCLKSOURCE_HSE_DIV57 ((0x38U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 57 used as RTC clock */ 518 #define RCC_RTCCLKSOURCE_HSE_DIV58 ((0x39U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 58 used as RTC clock */ 519 #define RCC_RTCCLKSOURCE_HSE_DIV59 ((0x3AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 59 used as RTC clock */ 520 #define RCC_RTCCLKSOURCE_HSE_DIV60 ((0x3BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 60 used as RTC clock */ 521 #define RCC_RTCCLKSOURCE_HSE_DIV61 ((0x3CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 61 used as RTC clock */ 522 #define RCC_RTCCLKSOURCE_HSE_DIV62 ((0x3DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 62 used as RTC clock */ 523 #define RCC_RTCCLKSOURCE_HSE_DIV63 ((0x3EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 63 used as RTC clock */ 524 #define RCC_RTCCLKSOURCE_HSE_DIV64 ((0x3FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 64 used as RTC clock */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCC_MCOx_Index MCOx Index 530 * @{ 531 */ 532 #define RCC_MCO1 0U /*!< Microcontroller Clock Output 1 */ 533 #define RCC_MCO2 1U /*!< Microcontroller Clock Output 2 */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 539 * @{ 540 */ 541 #define RCC_MCO1SOURCE_HSI LL_RCC_MCO1SOURCE_HSI /*!< HSI clock selected as MCO1 source (reset) */ 542 #define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE clock selected as MCO1 source */ 543 #define RCC_MCO1SOURCE_MSI LL_RCC_MCO1SOURCE_MSI /*!< MSI clock selected as MCO1 source */ 544 #define RCC_MCO1SOURCE_LSI LL_RCC_MCO1SOURCE_LSI /*!< HSI clock selected as MCO1 source */ 545 #define RCC_MCO1SOURCE_HSE LL_RCC_MCO1SOURCE_HSE /*!< HSE clock selected as MCO1 source */ 546 #define RCC_MCO1SOURCE_IC5 LL_RCC_MCO1SOURCE_IC5 /*!< IC5 clock selected as MCO1 source */ 547 #define RCC_MCO1SOURCE_IC10 LL_RCC_MCO1SOURCE_IC10 /*!< IC10 clock selected as MCO1 source */ 548 #define RCC_MCO1SOURCE_SYSA LL_RCC_MCO1SOURCE_SYSA /*!< SYSA CPU clock selected as MCO1 source */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 554 * @{ 555 */ 556 #define RCC_MCO2SOURCE_HSI LL_RCC_MCO2SOURCE_HSI /*!< HSI clock selected as MCO2 source (reset) */ 557 #define RCC_MCO2SOURCE_LSE LL_RCC_MCO2SOURCE_LSE /*!< LSE clock selected as MCO2 source */ 558 #define RCC_MCO2SOURCE_MSI LL_RCC_MCO2SOURCE_MSI /*!< MSI clock selected as MCO2 source */ 559 #define RCC_MCO2SOURCE_LSI LL_RCC_MCO2SOURCE_LSI /*!< LSI clock selected as MCO2 source */ 560 #define RCC_MCO2SOURCE_HSE LL_RCC_MCO2SOURCE_HSE /*!< HSE clock selected as MCO2 source */ 561 #define RCC_MCO2SOURCE_IC15 LL_RCC_MCO2SOURCE_IC15 /*!< IC15 clock selected as MCO2 source */ 562 #define RCC_MCO2SOURCE_IC20 LL_RCC_MCO2SOURCE_IC20 /*!< IC20 clock selected as MCO2 source */ 563 #define RCC_MCO2SOURCE_SYSB LL_RCC_MCO2SOURCE_SYSB /*!< SYSB bus clock selected as MCO2 source */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 569 * @{ 570 */ 571 #define RCC_MCODIV_1 LL_RCC_MCO1_DIV_1 /*!< MCO divided by 1 */ 572 #define RCC_MCODIV_2 LL_RCC_MCO1_DIV_2 /*!< MCO divided by 2 */ 573 #define RCC_MCODIV_3 LL_RCC_MCO1_DIV_3 /*!< MCO divided by 3 */ 574 #define RCC_MCODIV_4 LL_RCC_MCO1_DIV_4 /*!< MCO divided by 4 */ 575 #define RCC_MCODIV_5 LL_RCC_MCO1_DIV_5 /*!< MCO divided by 5 */ 576 #define RCC_MCODIV_6 LL_RCC_MCO1_DIV_6 /*!< MCO divided by 6 */ 577 #define RCC_MCODIV_7 LL_RCC_MCO1_DIV_7 /*!< MCO divided by 7 */ 578 #define RCC_MCODIV_8 LL_RCC_MCO1_DIV_8 /*!< MCO divided by 8 */ 579 #define RCC_MCODIV_9 LL_RCC_MCO1_DIV_9 /*!< MCO divided by 9 */ 580 #define RCC_MCODIV_10 LL_RCC_MCO1_DIV_10 /*!< MCO divided by 10 */ 581 #define RCC_MCODIV_11 LL_RCC_MCO1_DIV_11 /*!< MCO divided by 11 */ 582 #define RCC_MCODIV_12 LL_RCC_MCO1_DIV_12 /*!< MCO divided by 12 */ 583 #define RCC_MCODIV_13 LL_RCC_MCO1_DIV_13 /*!< MCO divided by 13 */ 584 #define RCC_MCODIV_14 LL_RCC_MCO1_DIV_14 /*!< MCO divided by 14 */ 585 #define RCC_MCODIV_15 LL_RCC_MCO1_DIV_15 /*!< MCO divided by 15 */ 586 #define RCC_MCODIV_16 LL_RCC_MCO1_DIV_16 /*!< MCO divided by 16 (reset) */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup RCC_Interrupt Interrupt 592 * @{ 593 */ 594 #define RCC_IT_LSIRDY RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt */ 595 #define RCC_IT_LSERDY RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt */ 596 #define RCC_IT_MSIRDY RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt */ 597 #define RCC_IT_HSIRDY RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt */ 598 #define RCC_IT_HSERDY RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt */ 599 #define RCC_IT_PLL1RDY RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt */ 600 #define RCC_IT_PLL2RDY RCC_CIER_PLL2RDYIE /*!< PLL2 Ready Interrupt */ 601 #define RCC_IT_PLL3RDY RCC_CIER_PLL3RDYIE /*!< PLL3 Ready Interrupt */ 602 #define RCC_IT_PLL4RDY RCC_CIER_PLL4RDYIE /*!< PLL4 Ready Interrupt */ 603 #define RCC_IT_LSECSS RCC_CIER_LSECSSIE /*!< LSE Clock Security System Interrupt */ 604 #define RCC_IT_HSECSS RCC_CIER_HSECSSIE /*!< HSE Clock Security System Interrupt */ 605 #define RCC_IT_WKUP RCC_CIER_WKUPIE /*!< CPU Wakeup Interrupt */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup RCC_Flag Flag 611 * Elements values convention: XXXYYYYYb 612 * - YYYYY : Flag position in the register 613 * - XXX : Register index 614 * - 001: SR register 615 * - 010: LSECFGR register 616 * - 011: HSECFGR register 617 * - 100: RSR register 618 * @{ 619 */ 620 /* Flags in the SR register */ 621 #define RCC_FLAG_LSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSIRDY_Pos) /*!< LSI ready flag */ 622 #define RCC_FLAG_LSERDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_LSERDY_Pos) /*!< LSE ready flag */ 623 #define RCC_FLAG_HSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSIRDY_Pos) /*!< HSI ready flag */ 624 #define RCC_FLAG_MSIRDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_MSIRDY_Pos) /*!< MSI ready flag */ 625 #define RCC_FLAG_HSERDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_HSERDY_Pos) /*!< HSE ready flag */ 626 #define RCC_FLAG_PLL1RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL1RDY_Pos) /*!< PLL1 ready flag */ 627 #define RCC_FLAG_PLL2RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL2RDY_Pos) /*!< PLL2 ready flag */ 628 #define RCC_FLAG_PLL3RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL3RDY_Pos) /*!< PLL3 ready flag */ 629 #define RCC_FLAG_PLL4RDY ((RCC_SR_REG_INDEX << 5U) | RCC_SR_PLL4RDY_Pos) /*!< PLL4 ready flag */ 630 631 /* Flags in the LSECFGR register */ 632 #define RCC_FLAG_LSECSSD ((RCC_LSECFGR_REG_INDEX << 5U) | RCC_LSECFGR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 633 634 /* Flags in the HSECFGR register */ 635 #define RCC_FLAG_HSECSSD ((RCC_HSECFGR_REG_INDEX << 5U) | RCC_HSECFGR_HSECSSD_Pos) /*!< HSE Clock Security System failure detection flag */ 636 637 /* Flags in the RSR register */ 638 #define RCC_FLAG_LCKRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LCKRSTF_Pos) /*!< CPU Lockup reset flag */ 639 #define RCC_FLAG_BORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos) /*!< BOR reset flag */ 640 #define RCC_FLAG_PINRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos) /*!< PIN reset flag */ 641 #define RCC_FLAG_PORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PORRSTF_Pos) /*!< Power-on reset flag */ 642 #define RCC_FLAG_SFTRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos) /*!< Software Reset flag */ 643 #define RCC_FLAG_IWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 644 #define RCC_FLAG_WWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 645 #define RCC_FLAG_LPWRRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 646 647 /** 648 * @} 649 */ 650 651 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 652 * @{ 653 */ 654 #define RCC_LSEDRIVE_LOW LL_RCC_LSEDRIVE_LOW /*!< LSE low drive capability */ 655 #define RCC_LSEDRIVE_MEDIUMLOW LL_RCC_LSEDRIVE_MEDIUMLOW /*!< LSE medium low drive capability */ 656 #define RCC_LSEDRIVE_MEDIUMHIGH LL_RCC_LSEDRIVE_MEDIUMHIGH /*!< LSE medium high drive capability */ 657 #define RCC_LSEDRIVE_HIGH LL_RCC_LSEDRIVE_HIGH /*!< LSE high drive capability */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup RCC_Stop_WakeUpClock Stop WakeUp Clock 663 * @{ 664 */ 665 #define RCC_STOP_WAKEUPCLOCK_HSI LL_RCC_SYSWAKEUP_CLKSOURCE_HSI /*!< HSI selected as wake up system clock from system Stop (default after reset) */ 666 #define RCC_STOP_WAKEUPCLOCK_MSI LL_RCC_SYSWAKEUP_CLKSOURCE_MSI /*!< MSI selected as wake up system clock from system Stop */ 667 /** 668 * @} 669 */ 670 671 672 /** @defgroup RCC_items RCC items 673 * @brief RCC items to configure attributes on 674 * @{ 675 */ 676 #define RCC_ITEM_LSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSISEC) 677 #define RCC_ITEM_LSE (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_LSESEC) 678 #define RCC_ITEM_MSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_MSISEC) 679 #define RCC_ITEM_HSI (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSISEC) 680 #define RCC_ITEM_HSE (RCC_ITEM_GROUP_OSC | RCC_SECCFGR0_HSESEC) 681 #define RCC_ITEM_PLL1 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL1SEC) 682 #define RCC_ITEM_PLL2 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL2SEC) 683 #define RCC_ITEM_PLL3 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL3SEC) 684 #define RCC_ITEM_PLL4 (RCC_ITEM_GROUP_PLL | RCC_SECCFGR1_PLL4SEC) 685 #define RCC_ITEM_IC1 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC1SEC) 686 #define RCC_ITEM_IC2 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC2SEC) 687 #define RCC_ITEM_IC3 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC3SEC) 688 #define RCC_ITEM_IC4 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC4SEC) 689 #define RCC_ITEM_IC5 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC5SEC) 690 #define RCC_ITEM_IC6 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC6SEC) 691 #define RCC_ITEM_IC7 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC7SEC) 692 #define RCC_ITEM_IC8 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC8SEC) 693 #define RCC_ITEM_IC9 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC9SEC) 694 #define RCC_ITEM_IC10 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC10SEC) 695 #define RCC_ITEM_IC11 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC11SEC) 696 #define RCC_ITEM_IC12 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC12SEC) 697 #define RCC_ITEM_IC13 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC13SEC) 698 #define RCC_ITEM_IC14 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC14SEC) 699 #define RCC_ITEM_IC15 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC15SEC) 700 #define RCC_ITEM_IC16 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC16SEC) 701 #define RCC_ITEM_IC17 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC17SEC) 702 #define RCC_ITEM_IC18 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC18SEC) 703 #define RCC_ITEM_IC19 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC19SEC) 704 #define RCC_ITEM_IC20 (RCC_ITEM_GROUP_IC | RCC_SECCFGR2_IC20SEC) 705 #define RCC_ITEM_MOD (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_MODSEC) 706 #define RCC_ITEM_SYS (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_SYSSEC) 707 #define RCC_ITEM_BUS (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_BUSSEC) 708 #define RCC_ITEM_PER (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_PERSEC) 709 #define RCC_ITEM_INT (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_INTSEC) 710 #define RCC_ITEM_RST (RCC_ITEM_GROUP_SYSCFG | RCC_SECCFGR3_RSTSEC) 711 #define RCC_ITEM_ACLKN (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNSEC) 712 #define RCC_ITEM_ACLKNC (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_ACLKNCSEC) 713 #define RCC_ITEM_AHBM (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHBMSEC) 714 #define RCC_ITEM_AHB1 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB1SEC) 715 #define RCC_ITEM_AHB2 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB2SEC) 716 #define RCC_ITEM_AHB3 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB3SEC) 717 #define RCC_ITEM_AHB4 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB4SEC) 718 #define RCC_ITEM_AHB5 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_AHB5SEC) 719 #define RCC_ITEM_APB1 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB1SEC) 720 #define RCC_ITEM_APB2 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB2SEC) 721 #define RCC_ITEM_APB3 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB3SEC) 722 #define RCC_ITEM_APB4 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB4SEC) 723 #define RCC_ITEM_APB5 (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_APB5SEC) 724 #define RCC_ITEM_NOC (RCC_ITEM_GROUP_BUS | RCC_SECCFGR4_NOCSEC) 725 #define RCC_ITEM_AXISRAM3 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM3PUB) 726 #define RCC_ITEM_AXISRAM4 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM4PUB) 727 #define RCC_ITEM_AXISRAM5 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM5PUB) 728 #define RCC_ITEM_AXISRAM6 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM6PUB) 729 #define RCC_ITEM_AHBSRAM1 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM1PUB) 730 #define RCC_ITEM_AHBSRAM2 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AHBSRAM2PUB) 731 #define RCC_ITEM_BKPSRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_BKPSRAMPUB) 732 #define RCC_ITEM_AXISRAM1 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM1PUB) 733 #define RCC_ITEM_AXISRAM2 (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_AXISRAM2PUB) 734 #define RCC_ITEM_FLEXRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_FLEXRAMPUB) 735 #if defined(CACHEAXI) 736 #define RCC_ITEM_CACHEAXIRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_CACHEAXIRAMPUB) 737 #else 738 #define RCC_ITEM_CACHEAXIRAM (RCC_ITEM_GROUP_MEM) 739 #endif /* defined(CACHEAXI) */ 740 #define RCC_ITEM_VENCRAM (RCC_ITEM_GROUP_MEM | RCC_PUBCFGR5_VENCRAMPUB) 741 742 #define RCC_ITEM_ALL (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE | \ 743 RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4 | RCC_ITEM_IC1 | \ 744 RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | RCC_ITEM_IC6 | \ 745 RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | RCC_ITEM_IC11 | \ 746 RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | RCC_ITEM_IC16 | \ 747 RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20 | RCC_ITEM_MOD | \ 748 RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | RCC_ITEM_RST | \ 749 RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \ 750 RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \ 751 RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC | RCC_ITEM_AXISRAM3 | \ 752 RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | RCC_ITEM_AHBSRAM1 | \ 753 RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | RCC_ITEM_AXISRAM2 | \ 754 RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM) 755 756 #define RCC_ITEM_ALL_CLK (RCC_ITEM_LSI | RCC_ITEM_LSE | RCC_ITEM_MSI | RCC_ITEM_HSI | RCC_ITEM_HSE) 757 #define RCC_ITEM_ALL_PLL (RCC_ITEM_PLL1 | RCC_ITEM_PLL2 | RCC_ITEM_PLL3 | RCC_ITEM_PLL4) 758 #define RCC_ITEM_ALL_ICx (RCC_ITEM_IC1 | RCC_ITEM_IC2 | RCC_ITEM_IC3 | RCC_ITEM_IC4 | RCC_ITEM_IC5 | \ 759 RCC_ITEM_IC6 | RCC_ITEM_IC7 | RCC_ITEM_IC8 | RCC_ITEM_IC9 | RCC_ITEM_IC10 | \ 760 RCC_ITEM_IC11 | RCC_ITEM_IC12 | RCC_ITEM_IC13 | RCC_ITEM_IC14 | RCC_ITEM_IC15 | \ 761 RCC_ITEM_IC16 | RCC_ITEM_IC17 | RCC_ITEM_IC18 | RCC_ITEM_IC19 | RCC_ITEM_IC20) 762 #define RCC_ITEM_ALL_SYSCFG (RCC_ITEM_MOD | RCC_ITEM_SYS | RCC_ITEM_BUS | RCC_ITEM_PER | RCC_ITEM_INT | \ 763 RCC_ITEM_RST) 764 #define RCC_ITEM_ALL_BUS (RCC_ITEM_ACLKN | RCC_ITEM_ACLKNC | RCC_ITEM_AHBM | RCC_ITEM_AHB1 | RCC_ITEM_AHB2 | \ 765 RCC_ITEM_AHB3 | RCC_ITEM_AHB4 | RCC_ITEM_AHB5 | RCC_ITEM_APB1 | RCC_ITEM_APB2 | \ 766 RCC_ITEM_APB3 | RCC_ITEM_APB4 | RCC_ITEM_APB5 | RCC_ITEM_NOC) 767 #define RCC_ITEM_ALL_MEM (RCC_ITEM_AXISRAM3 | RCC_ITEM_AXISRAM4 | RCC_ITEM_AXISRAM5 | RCC_ITEM_AXISRAM6 | \ 768 RCC_ITEM_AHBSRAM1 | RCC_ITEM_AHBSRAM2 | RCC_ITEM_BKPSRAM | RCC_ITEM_AXISRAM1 | \ 769 RCC_ITEM_AXISRAM2 | RCC_ITEM_FLEXRAM | RCC_ITEM_CACHEAXIRAM | RCC_ITEM_VENCRAM) 770 /** 771 * @} 772 */ 773 774 /** @defgroup RCC_attributes RCC attributes 775 * @brief RCC privilege/non-privilege, secure/non-secure, public/non-public and lock attributes 776 * @note Configuration registers of a SECURED item are only accessible from secure state. 777 * @note Configuration registers of a PRIVILEGED item are only writable from privileged state. 778 * @note Configuration registers of a PUBLIC and SECURED item are visible from NS (and S) software. 779 * @note Setting an item to LOCKED, definitively locks the SEC and PRIV attribute setting for this item. 780 * @{ 781 */ 782 #define RCC_ATTR_PRIV (RCC_ATTR_PRIV_MASK | 0x01U) /*!< attribute is privileged */ 783 #define RCC_ATTR_NPRIV RCC_ATTR_PRIV_MASK /*!< attribute is unprivileged */ 784 785 #define RCC_ATTR_SEC (RCC_ATTR_SEC_MASK | 0x04U) /*!< attribute is secure */ 786 #define RCC_ATTR_NSEC RCC_ATTR_SEC_MASK /*!< attribute is non-secure */ 787 788 #define RCC_ATTR_PUB (RCC_ATTR_PUB_MASK | 0x10U) /*!< attribute is public */ 789 #define RCC_ATTR_NPUB RCC_ATTR_PUB_MASK /*!< attribute is not public */ 790 791 #define RCC_ATTR_LOCK (RCC_ATTR_LOCK_MASK | 0x40U) /*!< attribute is locked */ 792 #define RCC_ATTR_NLOCK RCC_ATTR_LOCK_MASK /*!< attribute is not locked */ 793 /** 794 * @} 795 */ 796 797 /** 798 * @} 799 */ 800 801 /* Exported macros -----------------------------------------------------------*/ 802 803 /** @defgroup RCC_Exported_Macros RCC Exported Macros 804 * @{ 805 */ 806 807 /** @defgroup RCC_Embedded_Mem_Clock_Enable_Disable Embedded Memory Clock Enable Disable 808 * @brief Enable or disable the Embedded Memory clock. 809 * @note After reset, some embedded memory clocks are disabled 810 * and the application software has to enable these memory clocks before using them. 811 * @{ 812 */ 813 814 #define __HAL_RCC_AXISRAM1_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM1) 815 #define __HAL_RCC_AXISRAM1_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM1) 816 817 #define __HAL_RCC_AXISRAM2_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM2) 818 #define __HAL_RCC_AXISRAM2_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM2) 819 820 #define __HAL_RCC_AXISRAM3_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM3) 821 #define __HAL_RCC_AXISRAM3_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM3) 822 823 #define __HAL_RCC_AXISRAM4_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM4) 824 #define __HAL_RCC_AXISRAM4_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM4) 825 826 #define __HAL_RCC_AXISRAM5_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM5) 827 #define __HAL_RCC_AXISRAM5_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM5) 828 829 #define __HAL_RCC_AXISRAM6_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AXISRAM6) 830 #define __HAL_RCC_AXISRAM6_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AXISRAM6) 831 832 #define __HAL_RCC_AHBSRAM1_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AHBSRAM1) 833 #define __HAL_RCC_AHBSRAM1_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AHBSRAM1) 834 835 #define __HAL_RCC_AHBSRAM2_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_AHBSRAM2) 836 #define __HAL_RCC_AHBSRAM2_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_AHBSRAM2) 837 838 #define __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_BKPSRAM) 839 #define __HAL_RCC_BKPSRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_BKPSRAM) 840 841 #define __HAL_RCC_FLEXRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_FLEXRAM) 842 #define __HAL_RCC_FLEXRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_FLEXRAM) 843 844 #define __HAL_RCC_CACHEAXIRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_CACHEAXIRAM) 845 #define __HAL_RCC_CACHEAXIRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_CACHEAXIRAM) 846 847 #define __HAL_RCC_VENCRAM_MEM_CLK_ENABLE() LL_MEM_EnableClock(LL_MEM_VENCRAM) 848 #define __HAL_RCC_VENCRAM_MEM_CLK_DISABLE() LL_MEM_DisableClock(LL_MEM_VENCRAM) 849 850 /** 851 * @} 852 */ 853 854 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 855 * @brief Enable or disable the AHB1 peripheral clock. 856 * @note After reset, the peripheral clock (used for registers read/write access) 857 * is disabled and the application software has to enable this clock before 858 * using it. 859 * @{ 860 */ 861 862 #define __HAL_RCC_ADC12_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC12) 863 #define __HAL_RCC_ADC12_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_ADC12) 864 865 #define __HAL_RCC_GPDMA1_CLK_ENABLE() LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPDMA1) 866 #define __HAL_RCC_GPDMA1_CLK_DISABLE() LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_GPDMA1) 867 868 /** 869 * @} 870 */ 871 872 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 873 * @brief Enable or disable the AHB2 peripheral clock. 874 * @note After reset, the peripheral clock (used for registers read/write access) 875 * is disabled and the application software has to enable this clock before 876 * using it. 877 * @{ 878 */ 879 880 #define __HAL_RCC_ADF1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADF1) 881 #define __HAL_RCC_ADF1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADF1) 882 883 #define __HAL_RCC_MDF1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_MDF1) 884 #define __HAL_RCC_MDF1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_MDF1) 885 886 #define __HAL_RCC_RAMCFG_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_RAMCFG) 887 #define __HAL_RCC_RAMCFG_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_RAMCFG) 888 889 /** 890 * @} 891 */ 892 893 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 894 * @brief Enable or disable the AHB3 peripheral clock. 895 * @note After reset, the peripheral clock (used for registers read/write access) 896 * is disabled and the application software has to enable this clock before 897 * using it. 898 * @note IAC, RIFSC and RISAF peripheral clocks are always security-protected and thus hidden 899 * to the non-secure application. 900 * @{ 901 */ 902 903 #if defined(CRYP) 904 #define __HAL_RCC_CRYP_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_CRYP) 905 #define __HAL_RCC_CRYP_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_CRYP) 906 #endif /* CRYP */ 907 908 #define __HAL_RCC_HASH_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HASH) 909 #define __HAL_RCC_HASH_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HASH) 910 911 #if defined (CPU_IN_SECURE_STATE) 912 #define __HAL_RCC_IAC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IAC) 913 #define __HAL_RCC_IAC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IAC) 914 #endif /* CPU_IN_SECURE_STATE */ 915 916 #define __HAL_RCC_PKA_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA) 917 #define __HAL_RCC_PKA_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA) 918 919 #if defined (CPU_IN_SECURE_STATE) 920 #define __HAL_RCC_RIFSC_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RIFSC) 921 #define __HAL_RCC_RIFSC_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RIFSC) 922 #endif /* CPU_IN_SECURE_STATE */ 923 924 #if defined (CPU_IN_SECURE_STATE) 925 #define __HAL_RCC_RISAF_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RISAF) 926 #define __HAL_RCC_RISAF_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RISAF) 927 #endif /* CPU_IN_SECURE_STATE */ 928 929 #define __HAL_RCC_RNG_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG) 930 #define __HAL_RCC_RNG_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG) 931 932 #if defined(SAES) 933 #define __HAL_RCC_SAES_CLK_ENABLE() LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_SAES) 934 #define __HAL_RCC_SAES_CLK_DISABLE() LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_SAES) 935 #endif /* SAES */ 936 937 /** 938 * @} 939 */ 940 941 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable 942 * @brief Enable or disable the AHB4 peripheral clock. 943 * @note After reset, the peripheral clock (used for registers read/write access) 944 * is disabled and the application software has to enable this clock before 945 * using it. 946 * @note PWR peripheral clock is always security-protected and thus hidden to the non-secure 947 * application. 948 * @{ 949 */ 950 951 #define __HAL_RCC_CRC_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_CRC) 952 #define __HAL_RCC_CRC_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_CRC) 953 954 #define __HAL_RCC_GPIOA_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA) 955 #define __HAL_RCC_GPIOA_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOA) 956 957 #define __HAL_RCC_GPIOB_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB) 958 #define __HAL_RCC_GPIOB_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOB) 959 960 #define __HAL_RCC_GPIOC_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC) 961 #define __HAL_RCC_GPIOC_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOC) 962 963 #define __HAL_RCC_GPIOD_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD) 964 #define __HAL_RCC_GPIOD_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOD) 965 966 #define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOE) 967 #define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOE) 968 969 #define __HAL_RCC_GPIOF_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOF) 970 #define __HAL_RCC_GPIOF_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOF) 971 972 #define __HAL_RCC_GPIOG_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG) 973 #define __HAL_RCC_GPIOG_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOG) 974 975 #define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH) 976 #define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOH) 977 978 #define __HAL_RCC_GPION_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPION) 979 #define __HAL_RCC_GPION_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPION) 980 981 #define __HAL_RCC_GPIOO_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOO) 982 #define __HAL_RCC_GPIOO_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOO) 983 984 #define __HAL_RCC_GPIOP_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOP) 985 #define __HAL_RCC_GPIOP_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOP) 986 987 #define __HAL_RCC_GPIOQ_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOQ) 988 #define __HAL_RCC_GPIOQ_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_GPIOQ) 989 990 #if defined (CPU_IN_SECURE_STATE) 991 #define __HAL_RCC_PWR_CLK_ENABLE() LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR) 992 #define __HAL_RCC_PWR_CLK_DISABLE() LL_AHB4_GRP1_DisableClock(LL_AHB4_GRP1_PERIPH_PWR) 993 #endif /* CPU_IN_SECURE_STATE */ 994 995 /** 996 * @} 997 */ 998 999 /** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable AHB5 Peripheral Clock Enable Disable 1000 * @brief Enable or disable the AHB5 peripheral clock. 1001 * @note After reset, the peripheral clock (used for registers read/write access) 1002 * is disabled and the application software has to enable this clock before 1003 * using it. 1004 * @{ 1005 */ 1006 1007 #define __HAL_RCC_DMA2D_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_DMA2D) 1008 #define __HAL_RCC_DMA2D_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_DMA2D) 1009 1010 #if defined(ETH1) 1011 #define __HAL_RCC_ETH1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1) 1012 #define __HAL_RCC_ETH1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1) 1013 1014 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) 1015 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) 1016 1017 #define __HAL_RCC_ETH1TX_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1TX) 1018 #define __HAL_RCC_ETH1TX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1TX) 1019 1020 #define __HAL_RCC_ETH1RX_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_ETH1RX) 1021 #define __HAL_RCC_ETH1RX_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_ETH1RX) 1022 #endif /* ETH1 */ 1023 1024 #define __HAL_RCC_FMC_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_FMC) 1025 #define __HAL_RCC_FMC_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_FMC) 1026 1027 #if defined(GFXMMU) 1028 #define __HAL_RCC_GFXMMU_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GFXMMU) 1029 #define __HAL_RCC_GFXMMU_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GFXMMU) 1030 #endif /* GFXMMU */ 1031 1032 #if defined(GPU2D) 1033 #define __HAL_RCC_GPU2D_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_GPU2D) 1034 #define __HAL_RCC_GPU2D_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_GPU2D) 1035 #endif /* GPU2D */ 1036 1037 #define __HAL_RCC_HPDMA1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_HPDMA1) 1038 #define __HAL_RCC_HPDMA1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_HPDMA1) 1039 1040 #if defined(JPEG) 1041 #define __HAL_RCC_JPEG_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_JPEG) 1042 #define __HAL_RCC_JPEG_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_JPEG) 1043 #endif /* JPEG */ 1044 1045 #define __HAL_RCC_XSPI1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI1) 1046 #define __HAL_RCC_XSPI1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI1) 1047 1048 #define __HAL_RCC_XSPI2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI2) 1049 #define __HAL_RCC_XSPI2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI2) 1050 1051 #define __HAL_RCC_XSPI3_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPI3) 1052 #define __HAL_RCC_XSPI3_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPI3) 1053 1054 #define __HAL_RCC_XSPIM_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_XSPIM) 1055 #define __HAL_RCC_XSPIM_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_XSPIM) 1056 1057 #define __HAL_RCC_MCE1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE1) 1058 #define __HAL_RCC_MCE1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE1) 1059 1060 #define __HAL_RCC_MCE2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE2) 1061 #define __HAL_RCC_MCE2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE2) 1062 1063 #define __HAL_RCC_MCE3_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE3) 1064 #define __HAL_RCC_MCE3_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE3) 1065 1066 #define __HAL_RCC_MCE4_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_MCE4) 1067 #define __HAL_RCC_MCE4_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_MCE4) 1068 1069 #define __HAL_RCC_CACHEAXI_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) 1070 #define __HAL_RCC_CACHEAXI_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) 1071 1072 #define __HAL_RCC_NPU_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_NPU) 1073 #define __HAL_RCC_NPU_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_NPU) 1074 1075 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_PSSI) 1076 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_PSSI) 1077 1078 #define __HAL_RCC_SDMMC1_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC1) 1079 #define __HAL_RCC_SDMMC1_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC1) 1080 1081 #define __HAL_RCC_SDMMC2_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_SDMMC2) 1082 #define __HAL_RCC_SDMMC2_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_SDMMC2) 1083 1084 #define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG1) 1085 #define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG1) 1086 1087 #define __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) 1088 #define __HAL_RCC_USB1_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) 1089 1090 #define __HAL_RCC_USB2_OTG_HS_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTG2) 1091 #define __HAL_RCC_USB2_OTG_HS_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTG2) 1092 1093 #define __HAL_RCC_USB2_OTG_HS_PHY_CLK_ENABLE() LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) 1094 #define __HAL_RCC_USB2_OTG_HS_PHY_CLK_DISABLE() LL_AHB5_GRP1_DisableClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) 1095 1096 /** 1097 * @} 1098 */ 1099 1100 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1101 * @brief Enable or disable the APB1 peripheral clock. 1102 * @note After reset, the peripheral clock (used for registers read/write access) 1103 * is disabled and the application software has to enable this clock before 1104 * using it. 1105 * @{ 1106 */ 1107 1108 #define __HAL_RCC_FDCAN_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_FDCAN) 1109 #define __HAL_RCC_FDCAN_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_FDCAN) 1110 1111 #define __HAL_RCC_I2C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1) 1112 #define __HAL_RCC_I2C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1) 1113 1114 #define __HAL_RCC_I2C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2) 1115 #define __HAL_RCC_I2C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2) 1116 1117 #define __HAL_RCC_I2C3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3) 1118 #define __HAL_RCC_I2C3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3) 1119 1120 #define __HAL_RCC_I3C1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C1) 1121 #define __HAL_RCC_I3C1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C1) 1122 1123 #define __HAL_RCC_I3C2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I3C2) 1124 #define __HAL_RCC_I3C2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I3C2) 1125 1126 #define __HAL_RCC_LPTIM1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1127 #define __HAL_RCC_LPTIM1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1128 1129 #define __HAL_RCC_MDIOS_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_MDIOS) 1130 #define __HAL_RCC_MDIOS_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_MDIOS) 1131 1132 #define __HAL_RCC_SPDIFRX1_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) 1133 #define __HAL_RCC_SPDIFRX1_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) 1134 1135 #define __HAL_RCC_SPI2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2) 1136 #define __HAL_RCC_SPI2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2) 1137 1138 #define __HAL_RCC_SPI3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3) 1139 #define __HAL_RCC_SPI3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI3) 1140 1141 #define __HAL_RCC_TIM2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2) 1142 #define __HAL_RCC_TIM2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2) 1143 1144 #define __HAL_RCC_TIM3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3) 1145 #define __HAL_RCC_TIM3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3) 1146 1147 #define __HAL_RCC_TIM4_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4) 1148 #define __HAL_RCC_TIM4_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM4) 1149 1150 #define __HAL_RCC_TIM5_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5) 1151 #define __HAL_RCC_TIM5_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM5) 1152 1153 #define __HAL_RCC_TIM6_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6) 1154 #define __HAL_RCC_TIM6_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM6) 1155 1156 #define __HAL_RCC_TIM7_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7) 1157 #define __HAL_RCC_TIM7_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM7) 1158 1159 #define __HAL_RCC_TIM10_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM10) 1160 #define __HAL_RCC_TIM10_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM10) 1161 1162 #define __HAL_RCC_TIM11_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM11) 1163 #define __HAL_RCC_TIM11_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM11) 1164 1165 #define __HAL_RCC_TIM12_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12) 1166 #define __HAL_RCC_TIM12_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM12) 1167 1168 #define __HAL_RCC_TIM13_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM13) 1169 #define __HAL_RCC_TIM13_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM13) 1170 1171 #define __HAL_RCC_TIM14_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM14) 1172 #define __HAL_RCC_TIM14_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM14) 1173 1174 #define __HAL_RCC_USART2_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) 1175 #define __HAL_RCC_USART2_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2) 1176 1177 #define __HAL_RCC_USART3_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3) 1178 #define __HAL_RCC_USART3_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART3) 1179 1180 #define __HAL_RCC_UART4_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4) 1181 #define __HAL_RCC_UART4_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART4) 1182 1183 #define __HAL_RCC_UART5_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5) 1184 #define __HAL_RCC_UART5_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART5) 1185 1186 #define __HAL_RCC_UART7_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART7) 1187 #define __HAL_RCC_UART7_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART7) 1188 1189 #define __HAL_RCC_UART8_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART8) 1190 #define __HAL_RCC_UART8_CLK_DISABLE() LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UART8) 1191 1192 #define __HAL_RCC_UCPD1_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1) 1193 #define __HAL_RCC_UCPD1_CLK_DISABLE() LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1) 1194 1195 #define __HAL_RCC_WWDG_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG) 1196 1197 /** 1198 * @} 1199 */ 1200 1201 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1202 * @brief Enable or disable the APB2 peripheral clock. 1203 * @note After reset, the peripheral clock (used for registers read/write access) 1204 * is disabled and the application software has to enable this clock before 1205 * using it. 1206 * @{ 1207 */ 1208 1209 #define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1) 1210 #define __HAL_RCC_SAI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI1) 1211 1212 #define __HAL_RCC_SAI2_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI2) 1213 #define __HAL_RCC_SAI2_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SAI2) 1214 1215 #define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1) 1216 #define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1) 1217 1218 #define __HAL_RCC_SPI4_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4) 1219 #define __HAL_RCC_SPI4_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI4) 1220 1221 #define __HAL_RCC_SPI5_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5) 1222 #define __HAL_RCC_SPI5_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI5) 1223 1224 #define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1) 1225 #define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1) 1226 1227 #define __HAL_RCC_TIM8_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM8) 1228 #define __HAL_RCC_TIM8_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM8) 1229 1230 #define __HAL_RCC_TIM9_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM9) 1231 #define __HAL_RCC_TIM9_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM9) 1232 1233 #define __HAL_RCC_TIM15_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM15) 1234 #define __HAL_RCC_TIM15_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM15) 1235 1236 #define __HAL_RCC_TIM16_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16) 1237 #define __HAL_RCC_TIM16_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16) 1238 1239 #define __HAL_RCC_TIM17_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17) 1240 #define __HAL_RCC_TIM17_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17) 1241 1242 #define __HAL_RCC_TIM18_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM18) 1243 #define __HAL_RCC_TIM18_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM18) 1244 1245 #define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1) 1246 #define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1) 1247 1248 #define __HAL_RCC_USART6_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6) 1249 #define __HAL_RCC_USART6_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART6) 1250 1251 #define __HAL_RCC_UART9_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_UART9) 1252 #define __HAL_RCC_UART9_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_UART9) 1253 1254 #define __HAL_RCC_USART10_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART10) 1255 #define __HAL_RCC_USART10_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART10) 1256 1257 /** 1258 * @} 1259 */ 1260 1261 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1262 * @brief Enable or disable the APB3 peripheral clock. 1263 * @note After reset, the peripheral clock (used for registers read/write access) 1264 * is disabled and the application software has to enable this clock before 1265 * using it. 1266 * @{ 1267 */ 1268 1269 #define __HAL_RCC_DBGMCU_CLK_ENABLE() LL_BUS_EnableClock(LL_APB3); 1270 #define __HAL_RCC_DBGMCU_CLK_DISABLE() LL_BUS_DisableClock(LL_APB3); 1271 1272 /** 1273 * @} 1274 */ 1275 1276 /** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable APB4 Peripheral Clock Enable Disable 1277 * @brief Enable or disable the APB4 peripheral clock. 1278 * @note After reset, the peripheral clock (used for registers read/write access) 1279 * is disabled and the application software has to enable this clock before 1280 * using it. 1281 * @note BSEC peripheral clock is always security-protected and thus hidden to the non-secure 1282 * application. 1283 * @{ 1284 */ 1285 1286 #if defined (CPU_IN_SECURE_STATE) 1287 #define __HAL_RCC_BSEC_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC) 1288 #define __HAL_RCC_BSEC_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_BSEC) 1289 #endif /* CPU_IN_SECURE_STATE */ 1290 1291 #define __HAL_RCC_DTS_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_DTS) 1292 #define __HAL_RCC_DTS_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_DTS) 1293 1294 #define __HAL_RCC_HDP_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_HDP) 1295 #define __HAL_RCC_HDP_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_HDP) 1296 1297 #define __HAL_RCC_I2C4_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_I2C4) 1298 #define __HAL_RCC_I2C4_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_I2C4) 1299 1300 #define __HAL_RCC_LPTIM2_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM2) 1301 #define __HAL_RCC_LPTIM2_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM2) 1302 1303 #define __HAL_RCC_LPTIM3_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM3) 1304 #define __HAL_RCC_LPTIM3_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM3) 1305 1306 #define __HAL_RCC_LPTIM4_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM4) 1307 #define __HAL_RCC_LPTIM4_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM4) 1308 1309 #define __HAL_RCC_LPTIM5_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPTIM5) 1310 #define __HAL_RCC_LPTIM5_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPTIM5) 1311 1312 #define __HAL_RCC_LPUART1_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPUART1) 1313 #define __HAL_RCC_LPUART1_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_LPUART1) 1314 1315 #define __HAL_RCC_RTC_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTC) 1316 #define __HAL_RCC_RTC_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTC) 1317 1318 #define __HAL_RCC_RTCAPB_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_RTCAPB) 1319 #define __HAL_RCC_RTCAPB_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_RTCAPB) 1320 1321 #define __HAL_RCC_SPI6_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SPI6) 1322 #define __HAL_RCC_SPI6_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_SPI6) 1323 1324 #define __HAL_RCC_SYSCFG_CLK_ENABLE() LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG) 1325 #define __HAL_RCC_SYSCFG_CLK_DISABLE() LL_APB4_GRP2_DisableClock(LL_APB4_GRP2_PERIPH_SYSCFG) 1326 1327 #define __HAL_RCC_VREFBUF_CLK_ENABLE() LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_VREFBUF) 1328 #define __HAL_RCC_VREFBUF_CLK_DISABLE() LL_APB4_GRP1_DisableClock(LL_APB4_GRP1_PERIPH_VREFBUF) 1329 1330 /** 1331 * @} 1332 */ 1333 1334 /** @defgroup RCC_APB5_Peripheral_Clock_Enable_Disable APB5 Peripheral Clock Enable Disable 1335 * @brief Enable or disable the APB5 peripheral clock. 1336 * @note After reset, the peripheral clock (used for registers read/write access) 1337 * is disabled and the application software has to enable this clock before 1338 * using it. 1339 * @{ 1340 */ 1341 1342 #define __HAL_RCC_CSI_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_CSI) 1343 #define __HAL_RCC_CSI_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_CSI) 1344 1345 #define __HAL_RCC_DCMIPP_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_DCMIPP) 1346 #define __HAL_RCC_DCMIPP_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_DCMIPP) 1347 1348 #define __HAL_RCC_GFXTIM_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_GFXTIM) 1349 #define __HAL_RCC_GFXTIM_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_GFXTIM) 1350 1351 #define __HAL_RCC_LTDC_CLK_ENABLE() LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_LTDC) 1352 #define __HAL_RCC_LTDC_CLK_DISABLE() LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_LTDC) 1353 1354 #define __HAL_RCC_VENC_CLK_ENABLE() do { \ 1355 LL_APB5_GRP1_EnableClock(LL_APB5_GRP1_PERIPH_VENC); \ 1356 LL_BUS_EnableClock(LL_APB5); \ 1357 } while(0) 1358 #define __HAL_RCC_VENC_CLK_DISABLE() do { \ 1359 LL_BUS_DisableClock(LL_APB5); \ 1360 LL_APB5_GRP1_DisableClock(LL_APB5_GRP1_PERIPH_VENC); \ 1361 } while(0) 1362 1363 /** 1364 * @} 1365 */ 1366 1367 /** @defgroup RCC_MISC_Configuration_Clock_Enable_Disable Misc Configuration Clock Enable Disable 1368 * @brief Enable or disable the misc configuration clock. 1369 * @note After reset, the misc configuration clock is disabled and 1370 * the application software has to enable this clock before using it. 1371 * @note DBG clock is always security-protected and thus hidden to the non-secure application. 1372 * @{ 1373 */ 1374 1375 #if defined (CPU_IN_SECURE_STATE) 1376 #define __HAL_RCC_DBG_CLK_ENABLE() LL_MISC_EnableClock(LL_DBG) 1377 #define __HAL_RCC_DBG_CLK_DISABLE() LL_MISC_DisableClock(LL_DBG) 1378 #endif /* CPU_IN_SECURE_STATE */ 1379 1380 #define __HAL_RCC_XSPIPHYCOMP_CLK_ENABLE() LL_MISC_EnableClock(LL_XSPIPHYCOMP) 1381 #define __HAL_RCC_XSPIPHYCOMP_CLK_DISABLE() LL_MISC_DisableClock(LL_XSPIPHYCOMP) 1382 1383 #define __HAL_RCC_PER_CLK_ENABLE() LL_MISC_EnableClock(LL_PER) 1384 #define __HAL_RCC_PER_CLK_DISABLE() LL_MISC_DisableClock(LL_PER) 1385 1386 /** 1387 * @} 1388 */ 1389 1390 /** @defgroup RCC_Embedded_Mem_Clock_Status Embedded Memory Clock Enabled Status 1391 * @brief Check whether the embedded memory clock is enabled or not. 1392 * @note After reset, some embedded memory clocks are disabled 1393 * and the application software has to enable these memory clocks before using them. 1394 * @{ 1395 */ 1396 1397 #define __HAL_RCC_AXISRAM1_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM1) 1398 #define __HAL_RCC_AXISRAM2_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM2) 1399 #define __HAL_RCC_AXISRAM3_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM3) 1400 #define __HAL_RCC_AXISRAM4_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM4) 1401 #define __HAL_RCC_AXISRAM5_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM5) 1402 #define __HAL_RCC_AXISRAM6_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AXISRAM6) 1403 #define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM1) 1404 #define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_AHBSRAM2) 1405 #define __HAL_RCC_BKPSRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_BKPSRAM) 1406 #define __HAL_RCC_FLEXRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_FLEXRAM) 1407 #define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_CACHEAXIRAM) 1408 #define __HAL_RCC_VENCRAM_MEM_IS_CLK_ENABLED() LL_MEM_IsEnabledClock(LL_MEM_VENCRAM) 1409 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup RCC_AHB1_Clock_Enable_Status AHB1 Peripheral Clock Enabled Status 1415 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1416 * @note After reset, the peripheral clock (used for registers read/write access) 1417 * is disabled and the application software has to enable this clock before 1418 * using it. 1419 * @{ 1420 */ 1421 1422 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ADC12) 1423 1424 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_GPDMA1) 1425 1426 /** 1427 * @} 1428 */ 1429 1430 /** @defgroup RCC_AHB2_Clock_Enable_Status AHB2 Peripheral Clock Enabled Status 1431 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1432 * @note After reset, the peripheral clock (used for registers read/write access) 1433 * is disabled and the application software has to enable this clock before 1434 * using it. 1435 * @{ 1436 */ 1437 1438 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADF1) 1439 1440 #define __HAL_RCC_MDF1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_MDF1) 1441 1442 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_RAMCFG) 1443 1444 /** 1445 * @} 1446 */ 1447 1448 /** @defgroup RCC_AHB3_Clock_Enable_Status AHB3 Peripheral Clock Enabled Status 1449 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1450 * @note After reset, the peripheral clock (used for registers read/write access) 1451 * is disabled and the application software has to enable this clock before 1452 * using it. 1453 * @{ 1454 */ 1455 1456 #if defined(CRYP) 1457 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_CRYP) 1458 #endif /* CRYP */ 1459 1460 #define __HAL_RCC_HASH_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HASH) 1461 1462 #define __HAL_RCC_IAC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IAC) 1463 1464 #define __HAL_RCC_PKA_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA) 1465 1466 #define __HAL_RCC_RIFSC_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RIFSC) 1467 1468 #define __HAL_RCC_RISAF_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RISAF) 1469 1470 #define __HAL_RCC_RNG_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG) 1471 1472 #if defined(SAES) 1473 #define __HAL_RCC_SAES_IS_CLK_ENABLED() LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_SAES) 1474 #endif /* SAES */ 1475 1476 /** 1477 * @} 1478 */ 1479 1480 /** @defgroup RCC_AHB4_Clock_Enable_Status AHB4 Peripheral Clock Enabled Status 1481 * @brief Check whether the AHB4 peripheral clock is enabled or not. 1482 * @note After reset, the peripheral clock (used for registers read/write access) 1483 * is disabled and the application software has to enable this clock before 1484 * using it. 1485 * @{ 1486 */ 1487 1488 #define __HAL_RCC_CRC_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_CRC) 1489 1490 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOA) 1491 1492 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOB) 1493 1494 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOC) 1495 1496 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOD) 1497 1498 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOE) 1499 1500 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOF) 1501 1502 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOG) 1503 1504 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOH) 1505 1506 #define __HAL_RCC_GPION_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPION) 1507 1508 #define __HAL_RCC_GPIOO_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOO) 1509 1510 #define __HAL_RCC_GPIOP_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOP) 1511 1512 #define __HAL_RCC_GPIOQ_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_GPIOQ) 1513 1514 #define __HAL_RCC_PWR_IS_CLK_ENABLED() LL_AHB4_GRP1_IsEnabledClock(LL_AHB4_GRP1_PERIPH_PWR) 1515 1516 /** 1517 * @} 1518 */ 1519 1520 /** @defgroup RCC_AHB5_Clock_Enable_Status AHB5 Peripheral Clock Enabled Status 1521 * @brief Check whether the AHB5 peripheral clock is enabled or not. 1522 * @note After reset, the peripheral clock (used for registers read/write access) 1523 * is disabled and the application software has to enable this clock before 1524 * using it. 1525 * @{ 1526 */ 1527 1528 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_DMA2D) 1529 1530 #if defined(ETH1) 1531 #define __HAL_RCC_ETH1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1) 1532 1533 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1MAC) 1534 1535 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1TX) 1536 1537 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_ETH1RX) 1538 #endif /* ETH1 */ 1539 1540 #define __HAL_RCC_FMC_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_FMC) 1541 1542 #if defined(GFXMMU) 1543 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GFXMMU) 1544 #endif /* GFXMMU */ 1545 1546 #if defined(GPU2D) 1547 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_GPU2D) 1548 #endif /* GPU2D */ 1549 1550 #define __HAL_RCC_HPDMA1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_HPDMA1) 1551 1552 #if defined(JPEG) 1553 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_JPEG) 1554 #endif /* JPEG */ 1555 1556 #define __HAL_RCC_XSPI1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI1) 1557 1558 #define __HAL_RCC_XSPI2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI2) 1559 1560 #define __HAL_RCC_XSPI3_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPI3) 1561 1562 #define __HAL_RCC_XSPIM_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_XSPIM) 1563 1564 #define __HAL_RCC_MCE1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE1) 1565 1566 #define __HAL_RCC_MCE2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE2) 1567 1568 #define __HAL_RCC_MCE3_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE3) 1569 1570 #define __HAL_RCC_MCE4_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_MCE4) 1571 1572 #define __HAL_RCC_CACHEAXI_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_CACHEAXI) 1573 1574 #define __HAL_RCC_NPU_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_NPU) 1575 1576 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_PSSI) 1577 1578 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC1) 1579 1580 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_SDMMC2) 1581 1582 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG1) 1583 1584 #define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY1) 1585 1586 #define __HAL_RCC_USB2_OTG_HS_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTG2) 1587 1588 #define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_ENABLED() LL_AHB5_GRP1_IsEnabledClock(LL_AHB5_GRP1_PERIPH_OTGPHY2) 1589 1590 /** 1591 * @} 1592 */ 1593 1594 /** @defgroup RCC_APB1_Clock_Enable_Status APB1 Peripheral Clock Enabled Status 1595 * @brief Check whether the APB1 peripheral clock is enabled or not. 1596 * @note After reset, the peripheral clock (used for registers read/write access) 1597 * is disabled and the application software has to enable this clock before 1598 * using it. 1599 * @{ 1600 */ 1601 1602 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_FDCAN) 1603 1604 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1) 1605 1606 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2) 1607 1608 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3) 1609 1610 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C1) 1611 1612 #define __HAL_RCC_I3C2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I3C2) 1613 1614 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1) 1615 1616 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_MDIOS) 1617 1618 #define __HAL_RCC_SPDIFRX1_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPDIFRX1) 1619 1620 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2) 1621 1622 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3) 1623 1624 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2) 1625 1626 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM3) 1627 1628 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM4) 1629 1630 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM5) 1631 1632 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM6) 1633 1634 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM7) 1635 1636 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM10) 1637 1638 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM11) 1639 1640 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12) 1641 1642 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM13) 1643 1644 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM14) 1645 1646 #define __HAL_RCC_USART2_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2) 1647 1648 #define __HAL_RCC_USART3_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART3) 1649 1650 #define __HAL_RCC_UART4_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART4) 1651 1652 #define __HAL_RCC_UART5_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART5) 1653 1654 #define __HAL_RCC_UART7_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART7) 1655 1656 #define __HAL_RCC_UART8_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_UART8) 1657 1658 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_UCPD1) 1659 1660 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG) 1661 1662 /** 1663 * @} 1664 */ 1665 1666 /** @defgroup RCC_APB2_Clock_Enable_Status APB2 Peripheral Clock Enabled Status 1667 * @brief Check whether the APB2 peripheral clock is enabled or not. 1668 * @note After reset, the peripheral clock (used for registers read/write access) 1669 * is disabled and the application software has to enable this clock before 1670 * using it. 1671 * @{ 1672 */ 1673 1674 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI1) 1675 1676 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SAI2) 1677 1678 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1) 1679 1680 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI4) 1681 1682 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI5) 1683 1684 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1) 1685 1686 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM8) 1687 1688 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM9) 1689 1690 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM15) 1691 1692 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16) 1693 1694 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17) 1695 1696 #define __HAL_RCC_TIM18_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM18) 1697 1698 #define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1) 1699 1700 #define __HAL_RCC_USART6_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART6) 1701 1702 #define __HAL_RCC_UART9_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_UART9) 1703 1704 #define __HAL_RCC_USART10_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART10) 1705 1706 /** 1707 * @} 1708 */ 1709 1710 1711 /** @defgroup RCC_APB3_Clock_Enable_Status APB3 Peripheral Clock Enabled Status 1712 * @brief Check whether the APB3 peripheral clock is enabled or not. 1713 * @note After reset, the peripheral clock (used for registers read/write access) 1714 * is disabled and the application software has to enable this clock before 1715 * using it. 1716 * @{ 1717 */ 1718 1719 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() LL_BUS_IsEnabledClock(LL_APB3); 1720 1721 /** 1722 * @} 1723 */ 1724 1725 /** @defgroup RCC_APB4_Clock_Enable_Status APB4 Peripheral Clock Enabled Status 1726 * @brief Check whether the APB4 peripheral clock is enabled or not. 1727 * @note After reset, the peripheral clock (used for registers read/write access) 1728 * is disabled and the application software has to enable this clock before 1729 * using it. 1730 * @{ 1731 */ 1732 1733 #define __HAL_RCC_BSEC_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_BSEC) 1734 1735 #define __HAL_RCC_DTS_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_DTS) 1736 1737 #define __HAL_RCC_HDP_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_HDP) 1738 1739 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_I2C4) 1740 1741 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM2) 1742 1743 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM3) 1744 1745 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM4) 1746 1747 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPTIM5) 1748 1749 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_LPUART1) 1750 1751 #define __HAL_RCC_RTC_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTC) 1752 1753 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_RTCAPB) 1754 1755 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_SPI6) 1756 1757 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() LL_APB4_GRP2_IsEnabledClock(LL_APB4_GRP2_PERIPH_SYSCFG) 1758 1759 #define __HAL_RCC_VREFBUF_IS_CLK_ENABLED() LL_APB4_GRP1_IsEnabledClock(LL_APB4_GRP1_PERIPH_VREFBUF) 1760 1761 /** 1762 * @} 1763 */ 1764 1765 /** @defgroup RCC_APB5_Clock_Enable_Status APB5 Peripheral Clock Enabled Status 1766 * @brief Check whether the APB5 peripheral clock is enabled or not. 1767 * @note After reset, the peripheral clock (used for registers read/write access) 1768 * is disabled and the application software has to enable this clock before 1769 * using it. 1770 * @{ 1771 */ 1772 1773 #define __HAL_RCC_CSI_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_CSI) 1774 1775 #define __HAL_RCC_DCMIPP_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_DCMIPP) 1776 1777 #define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_GFXTIM) 1778 1779 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_LTDC) 1780 1781 #define __HAL_RCC_VENC_IS_CLK_ENABLED() LL_APB5_GRP1_IsEnabledClock(LL_APB5_GRP1_PERIPH_VENC) 1782 1783 /** 1784 * @} 1785 */ 1786 1787 /** @defgroup RCC_MISC_Configuration_Clock_Enable_Status Misc Configuration Clock Enabled Status 1788 * @brief Check whether the misc configuration clock is enabled or not. 1789 * @note After reset, the misc configuration clock is disabled and 1790 * the application software has to enable this clock before using it. 1791 * @{ 1792 */ 1793 1794 #define __HAL_RCC_DBG_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_DBG) 1795 1796 #define __HAL_RCC_MCO1_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_MCO1) 1797 1798 #define __HAL_RCC_MCO2_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_MCO2) 1799 1800 #define __HAL_RCC_XSPIPHYCOMP_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_XSPIPHYCOMP) 1801 1802 #define __HAL_RCC_PER_IS_CLK_ENABLED() LL_MISC_IsEnabledClock(LL_PER) 1803 1804 /** 1805 * @} 1806 */ 1807 1808 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1809 * @brief Force or release AHB1 peripheral reset. 1810 * @{ 1811 */ 1812 1813 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTSR, 0x00000030UL); 1814 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTSR, 0UL) 1815 1816 #define __HAL_RCC_GPDMA1_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1) 1817 #define __HAL_RCC_GPDMA1_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1) 1818 1819 #define __HAL_RCC_ADC12_FORCE_RESET() LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ADC12) 1820 #define __HAL_RCC_ADC12_RELEASE_RESET() LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12) 1821 1822 /** 1823 * @} 1824 */ 1825 1826 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1827 * @brief Force or release AHB2 peripheral reset. 1828 * @{ 1829 */ 1830 1831 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTSR, 0x00031000UL); 1832 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTSR, 0UL) 1833 1834 #define __HAL_RCC_ADF1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADF1) 1835 #define __HAL_RCC_ADF1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADF1) 1836 1837 #define __HAL_RCC_MDF1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_MDF1) 1838 #define __HAL_RCC_MDF1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_MDF1) 1839 1840 #define __HAL_RCC_RAMCFG_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RAMCFG) 1841 #define __HAL_RCC_RAMCFG_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RAMCFG) 1842 1843 /** 1844 * @} 1845 */ 1846 1847 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1848 * @brief Force or release AHB3 peripheral reset. 1849 * @note IAC peripheral reset is always security-protected and thus hidden to the non-secure 1850 * application. 1851 * @{ 1852 */ 1853 1854 #if defined (CPU_IN_SECURE_STATE) 1855 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0x00000517UL); 1856 #else 1857 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0x00000117UL); 1858 #endif /* CPU_IN_SECURE_STATE */ 1859 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTSR, 0UL) 1860 1861 #if defined (CPU_IN_SECURE_STATE) 1862 #define __HAL_RCC_IAC_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IAC) 1863 #define __HAL_RCC_IAC_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IAC) 1864 #endif /* CPU_IN_SECURE_STATE */ 1865 1866 #if defined(CRYP) 1867 #define __HAL_RCC_CRYP_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_CRYP) 1868 #define __HAL_RCC_CRYP_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_CRYP) 1869 #endif /* CRYP */ 1870 1871 #define __HAL_RCC_HASH_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HASH) 1872 #define __HAL_RCC_HASH_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HASH) 1873 1874 #define __HAL_RCC_PKA_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA) 1875 #define __HAL_RCC_PKA_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA) 1876 1877 #define __HAL_RCC_RNG_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG) 1878 #define __HAL_RCC_RNG_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG) 1879 1880 #if defined(SAES) 1881 #define __HAL_RCC_SAES_FORCE_RESET() LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_SAES) 1882 #define __HAL_RCC_SAES_RELEASE_RESET() LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_SAES) 1883 #endif /* SAES */ 1884 1885 /** 1886 * @} 1887 */ 1888 1889 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 1890 * @brief Force or release AHB4 peripheral reset. 1891 * @note PWR peripheral reset is always security-protected and thus hidden to the non-secure 1892 * application. 1893 * @{ 1894 */ 1895 1896 #if defined (CPU_IN_SECURE_STATE) 1897 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0x000DE0FFUL); 1898 #else 1899 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0x0005E0FFUL); 1900 #endif /* CPU_IN_SECURE_STATE */ 1901 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTSR, 0UL) 1902 1903 #define __HAL_RCC_CRC_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC) 1904 #define __HAL_RCC_CRC_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC) 1905 1906 #define __HAL_RCC_GPIOA_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA) 1907 #define __HAL_RCC_GPIOA_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA) 1908 1909 #define __HAL_RCC_GPIOB_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB) 1910 #define __HAL_RCC_GPIOB_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB) 1911 1912 #define __HAL_RCC_GPIOC_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC) 1913 #define __HAL_RCC_GPIOC_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC) 1914 1915 #define __HAL_RCC_GPIOD_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD) 1916 #define __HAL_RCC_GPIOD_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD) 1917 1918 #define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE) 1919 #define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE) 1920 1921 #define __HAL_RCC_GPIOF_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF) 1922 #define __HAL_RCC_GPIOF_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF) 1923 1924 #define __HAL_RCC_GPIOG_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG) 1925 #define __HAL_RCC_GPIOG_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG) 1926 1927 #define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH) 1928 #define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH) 1929 1930 #define __HAL_RCC_GPION_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPION) 1931 #define __HAL_RCC_GPION_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPION) 1932 1933 #define __HAL_RCC_GPIOO_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOO) 1934 #define __HAL_RCC_GPIOO_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOO) 1935 1936 #define __HAL_RCC_GPIOP_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOP) 1937 #define __HAL_RCC_GPIOP_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOP) 1938 1939 #define __HAL_RCC_GPIOQ_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOQ) 1940 #define __HAL_RCC_GPIOQ_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOQ) 1941 1942 #if defined (CPU_IN_SECURE_STATE) 1943 #define __HAL_RCC_PWR_FORCE_RESET() LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_PWR) 1944 #define __HAL_RCC_PWR_RELEASE_RESET() LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_PWR) 1945 #endif /* CPU_IN_SECURE_STATE */ 1946 1947 /** 1948 * @} 1949 */ 1950 1951 /** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset 1952 * @brief Force or release AHB5 peripheral reset. 1953 * @{ 1954 */ 1955 1956 /* Caution: The two following macros should only be called from code running in internal RAM 1957 * since it resets the external peripheral memory interfaces. 1958 */ 1959 #define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTSR, 0xFF9A31FBUL) 1960 #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTSR, 0UL) 1961 1962 #define __HAL_RCC_DMA2D_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_DMA2D) 1963 #define __HAL_RCC_DMA2D_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_DMA2D) 1964 1965 #if defined(ETH1) 1966 #define __HAL_RCC_ETH1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_ETH1); 1967 #define __HAL_RCC_ETH1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_ETH1); 1968 #endif /* ETH1 */ 1969 1970 #define __HAL_RCC_FMC_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_FMC) 1971 #define __HAL_RCC_FMC_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_FMC) 1972 1973 #if defined(GFXMMU) 1974 #define __HAL_RCC_GFXMMU_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GFXMMU) 1975 #define __HAL_RCC_GFXMMU_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GFXMMU) 1976 #endif /* GFXMMU */ 1977 1978 #if defined(GPU2D) 1979 #define __HAL_RCC_GPU2D_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_GPU2D) 1980 #define __HAL_RCC_GPU2D_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_GPU2D) 1981 #endif /* GPU2D */ 1982 1983 #define __HAL_RCC_HPDMA1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_HPDMA1) 1984 #define __HAL_RCC_HPDMA1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_HPDMA1) 1985 1986 #define __HAL_RCC_XSPI1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI1) 1987 #define __HAL_RCC_XSPI1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI1) 1988 1989 #define __HAL_RCC_XSPI2_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI2) 1990 #define __HAL_RCC_XSPI2_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI2) 1991 1992 #define __HAL_RCC_XSPI3_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPI3); 1993 #define __HAL_RCC_XSPI3_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPI3); 1994 1995 #define __HAL_RCC_XSPIM_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_XSPIM) 1996 #define __HAL_RCC_XSPIM_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_XSPIM) 1997 1998 #if defined(JPEG) 1999 #define __HAL_RCC_JPEG_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_JPEG) 2000 #define __HAL_RCC_JPEG_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_JPEG) 2001 #endif /* JPEG */ 2002 2003 #define __HAL_RCC_CACHEAXI_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_CACHEAXI); 2004 #define __HAL_RCC_CACHEAXI_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_CACHEAXI); 2005 2006 #define __HAL_RCC_NPU_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_NPU); 2007 #define __HAL_RCC_NPU_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_NPU); 2008 2009 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_PSSI) 2010 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_PSSI) 2011 2012 #define __HAL_RCC_SDMMC1_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC1) 2013 #define __HAL_RCC_SDMMC1_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC1) 2014 2015 #define __HAL_RCC_SDMMC2_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_SDMMC2) 2016 #define __HAL_RCC_SDMMC2_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_SDMMC2) 2017 2018 #define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1) 2019 #define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1) 2020 2021 #define __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY1); 2022 #define __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY1); 2023 2024 #define __HAL_RCC_USB1_OTG_HS_CTL_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL); 2025 #define __HAL_RCC_USB1_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG1PHYCTL); 2026 2027 #define __HAL_RCC_USB2_OTG_HS_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2) 2028 #define __HAL_RCC_USB2_OTG_HS_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2) 2029 2030 #define __HAL_RCC_USB2_OTG_HS_PHY_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTGPHY2); 2031 #define __HAL_RCC_USB2_OTG_HS_PHY_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTGPHY2); 2032 2033 #define __HAL_RCC_USB2_OTG_HS_CTL_FORCE_RESET() LL_AHB5_GRP1_ForceReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL); 2034 #define __HAL_RCC_USB2_OTG_HS_CTL_RELEASE_RESET() LL_AHB5_GRP1_ReleaseReset(LL_AHB5_GRP1_PERIPH_OTG2PHYCTL); 2035 2036 /** 2037 * @} 2038 */ 2039 2040 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2041 * @brief Force or release APB1 peripheral reset. 2042 * @{ 2043 */ 2044 2045 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2046 WRITE_REG(RCC->APB1RSTSR1, 0xC3FFF3FFUL); \ 2047 WRITE_REG(RCC->APB1RSTSR2, 0x00040120UL); \ 2048 } while(0) 2049 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2050 WRITE_REG(RCC->APB1RSTSR1, 0UL); \ 2051 WRITE_REG(RCC->APB1RSTSR2, 0UL); \ 2052 } while(0) 2053 2054 #define __HAL_RCC_FDCAN_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_FDCAN) 2055 #define __HAL_RCC_FDCAN_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_FDCAN) 2056 2057 #define __HAL_RCC_I2C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1) 2058 #define __HAL_RCC_I2C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1) 2059 2060 #define __HAL_RCC_I2C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2) 2061 #define __HAL_RCC_I2C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2) 2062 2063 #define __HAL_RCC_I2C3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3) 2064 #define __HAL_RCC_I2C3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3) 2065 2066 #define __HAL_RCC_I3C1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C1) 2067 #define __HAL_RCC_I3C1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C1) 2068 2069 #define __HAL_RCC_I3C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I3C2) 2070 #define __HAL_RCC_I3C2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I3C2) 2071 2072 #define __HAL_RCC_LPTIM1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1) 2073 #define __HAL_RCC_LPTIM1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1) 2074 2075 #define __HAL_RCC_MDIOS_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_MDIOS) 2076 #define __HAL_RCC_MDIOS_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_MDIOS) 2077 2078 #define __HAL_RCC_SPDIFRX1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPDIFRX1) 2079 #define __HAL_RCC_SPDIFRX1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPDIFRX1) 2080 2081 #define __HAL_RCC_SPI2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2) 2082 #define __HAL_RCC_SPI2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2) 2083 2084 #define __HAL_RCC_SPI3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3) 2085 #define __HAL_RCC_SPI3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3) 2086 2087 #define __HAL_RCC_TIM2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2) 2088 #define __HAL_RCC_TIM2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2) 2089 2090 #define __HAL_RCC_TIM3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3) 2091 #define __HAL_RCC_TIM3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3) 2092 2093 #define __HAL_RCC_TIM4_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4) 2094 #define __HAL_RCC_TIM4_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4) 2095 2096 #define __HAL_RCC_TIM5_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5) 2097 #define __HAL_RCC_TIM5_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5) 2098 2099 #define __HAL_RCC_TIM6_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6) 2100 #define __HAL_RCC_TIM6_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6) 2101 2102 #define __HAL_RCC_TIM7_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7) 2103 #define __HAL_RCC_TIM7_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7) 2104 2105 #define __HAL_RCC_TIM10_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM10) 2106 #define __HAL_RCC_TIM10_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM10) 2107 2108 #define __HAL_RCC_TIM11_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM11) 2109 #define __HAL_RCC_TIM11_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM11) 2110 2111 #define __HAL_RCC_TIM12_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12) 2112 #define __HAL_RCC_TIM12_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12) 2113 2114 #define __HAL_RCC_TIM13_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13) 2115 #define __HAL_RCC_TIM13_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13) 2116 2117 #define __HAL_RCC_TIM14_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14) 2118 #define __HAL_RCC_TIM14_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14) 2119 2120 #define __HAL_RCC_UCPD1_FORCE_RESET() LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1) 2121 #define __HAL_RCC_UCPD1_RELEASE_RESET() LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1) 2122 2123 #define __HAL_RCC_USART2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2) 2124 #define __HAL_RCC_USART2_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2) 2125 2126 #define __HAL_RCC_USART3_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3) 2127 #define __HAL_RCC_USART3_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3) 2128 2129 #define __HAL_RCC_UART4_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4) 2130 #define __HAL_RCC_UART4_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4) 2131 2132 #define __HAL_RCC_UART5_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5) 2133 #define __HAL_RCC_UART5_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5) 2134 2135 #define __HAL_RCC_UART7_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7) 2136 #define __HAL_RCC_UART7_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7) 2137 2138 #define __HAL_RCC_UART8_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8) 2139 #define __HAL_RCC_UART8_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8) 2140 2141 /** 2142 * @} 2143 */ 2144 2145 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2146 * @brief Force or release APB2 peripheral reset. 2147 * @{ 2148 */ 2149 2150 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTSR, 0x007FB0F3UL) 2151 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTSR, 0UL) 2152 2153 #define __HAL_RCC_SAI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI1) 2154 #define __HAL_RCC_SAI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI1) 2155 2156 #define __HAL_RCC_SAI2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SAI2) 2157 #define __HAL_RCC_SAI2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SAI2) 2158 2159 #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1) 2160 #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1) 2161 2162 #define __HAL_RCC_SPI4_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4) 2163 #define __HAL_RCC_SPI4_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4) 2164 2165 #define __HAL_RCC_SPI5_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5) 2166 #define __HAL_RCC_SPI5_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5) 2167 2168 #define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1) 2169 #define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1) 2170 2171 #define __HAL_RCC_TIM8_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8) 2172 #define __HAL_RCC_TIM8_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8) 2173 2174 #define __HAL_RCC_TIM9_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9) 2175 #define __HAL_RCC_TIM9_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9) 2176 2177 #define __HAL_RCC_TIM15_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15) 2178 #define __HAL_RCC_TIM15_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15) 2179 2180 #define __HAL_RCC_TIM16_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16) 2181 #define __HAL_RCC_TIM16_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16) 2182 2183 #define __HAL_RCC_TIM17_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17) 2184 #define __HAL_RCC_TIM17_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17) 2185 2186 #define __HAL_RCC_TIM18_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM18) 2187 #define __HAL_RCC_TIM18_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM18) 2188 2189 #define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1) 2190 #define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1) 2191 2192 #define __HAL_RCC_USART6_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6) 2193 #define __HAL_RCC_USART6_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6) 2194 2195 #define __HAL_RCC_UART9_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9) 2196 #define __HAL_RCC_UART9_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9) 2197 2198 #define __HAL_RCC_USART10_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10) 2199 #define __HAL_RCC_USART10_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10) 2200 2201 /** 2202 * @} 2203 */ 2204 2205 /** @defgroup RCC_APB4_Force_Release_Reset APB4 Peripheral Force Release Reset 2206 * @brief Force or release APB4 peripheral reset. 2207 * @{ 2208 */ 2209 2210 #define __HAL_RCC_APB4_FORCE_RESET() do { \ 2211 WRITE_REG(RCC->APB4RSTSR1, 0x00019EACUL); \ 2212 WRITE_REG(RCC->APB4RSTSR2, 0x00000005UL); \ 2213 } while(0) 2214 #define __HAL_RCC_APB4_RELEASE_RESET() do { \ 2215 WRITE_REG(RCC->APB4RSTSR1, 0UL); \ 2216 WRITE_REG(RCC->APB4RSTSR2, 0UL); \ 2217 } while(0) 2218 2219 #define __HAL_RCC_DTS_FORCE_RESET() LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_DTS) 2220 #define __HAL_RCC_DTS_RELEASE_RESET() LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_DTS) 2221 2222 #define __HAL_RCC_HDP_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_HDP) 2223 #define __HAL_RCC_HDP_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_HDP) 2224 2225 #define __HAL_RCC_I2C4_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_I2C4) 2226 #define __HAL_RCC_I2C4_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_I2C4) 2227 2228 #define __HAL_RCC_LPTIM2_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2) 2229 #define __HAL_RCC_LPTIM2_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2) 2230 2231 #define __HAL_RCC_LPTIM3_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3) 2232 #define __HAL_RCC_LPTIM3_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3) 2233 2234 #define __HAL_RCC_LPTIM4_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4) 2235 #define __HAL_RCC_LPTIM4_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4) 2236 2237 #define __HAL_RCC_LPTIM5_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5) 2238 #define __HAL_RCC_LPTIM5_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5) 2239 2240 #define __HAL_RCC_LPUART1_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1) 2241 #define __HAL_RCC_LPUART1_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1) 2242 2243 #define __HAL_RCC_RTC_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_RTC) 2244 #define __HAL_RCC_RTC_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_RTC) 2245 2246 #define __HAL_RCC_SPI6_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6) 2247 #define __HAL_RCC_SPI6_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6) 2248 2249 #define __HAL_RCC_SYSCFG_FORCE_RESET() LL_APB4_GRP2_ForceReset(LL_APB4_GRP2_PERIPH_SYSCFG) 2250 #define __HAL_RCC_SYSCFG_RELEASE_RESET() LL_APB4_GRP2_ReleaseReset(LL_APB4_GRP2_PERIPH_SYSCFG) 2251 2252 #define __HAL_RCC_VREFBUF_FORCE_RESET() LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_VREFBUF) 2253 #define __HAL_RCC_VREFBUF_RELEASE_RESET() LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_VREFBUF) 2254 2255 /** 2256 * @} 2257 */ 2258 2259 /** @defgroup RCC_APB5_Force_Release_Reset APB5 Peripheral Force Release Reset 2260 * @brief Force or release APB5 peripheral reset. 2261 * @{ 2262 */ 2263 2264 #define __HAL_RCC_APB5_FORCE_RESET() WRITE_REG(RCC->APB5RSTSR, 0x00000076UL) 2265 #define __HAL_RCC_APB5_RELEASE_RESET() WRITE_REG(RCC->APB5RSTSR, 0UL) 2266 2267 #define __HAL_RCC_CSI_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_CSI) 2268 #define __HAL_RCC_CSI_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_CSI) 2269 2270 #define __HAL_RCC_DCMIPP_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_DCMIPP) 2271 #define __HAL_RCC_DCMIPP_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_DCMIPP) 2272 2273 #define __HAL_RCC_GFXTIM_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_GFXTIM) 2274 #define __HAL_RCC_GFXTIM_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_GFXTIM) 2275 2276 #define __HAL_RCC_LTDC_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_LTDC) 2277 #define __HAL_RCC_LTDC_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_LTDC) 2278 2279 #define __HAL_RCC_VENC_FORCE_RESET() LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_VENC) 2280 #define __HAL_RCC_VENC_RELEASE_RESET() LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_VENC) 2281 2282 /** 2283 * @} 2284 */ 2285 2286 /** @defgroup RCC_MISC_Configuration_Force_Release_Reset Misc Configuration Force Release Reset 2287 * @brief Force or release misc configuration reset. 2288 * @note DBG reset is always security-protected and thus hidden to the non-secure application. 2289 * @{ 2290 */ 2291 2292 #if defined (CPU_IN_SECURE_STATE) 2293 #define __HAL_RCC_DBG_FORCE_RESET() LL_MISC_ForceReset(LL_DBG) 2294 #define __HAL_RCC_DBG_RELEASE_RESET() LL_MISC_ReleaseReset(LL_DBG) 2295 #endif /* CPU_IN_SECURE_STATE */ 2296 2297 #define __HAL_RCC_XSPIPHY1_FORCE_RESET() LL_MISC_ForceReset(LL_XSPIPHY1) 2298 #define __HAL_RCC_XSPIPHY1_RELEASE_RESET() LL_MISC_ReleaseReset(LL_XSPIPHY1) 2299 2300 #define __HAL_RCC_XSPIPHY2_FORCE_RESET() LL_MISC_ForceReset(LL_XSPIPHY2) 2301 #define __HAL_RCC_XSPIPHY2_RELEASE_RESET() LL_MISC_ReleaseReset(LL_XSPIPHY2) 2302 2303 #define __HAL_RCC_SDMMC1DLL_FORCE_RESET() LL_MISC_ForceReset(LL_SDMMC1DLL) 2304 #define __HAL_RCC_SDMMC1DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC1DLL) 2305 2306 #define __HAL_RCC_SDMMC2DLL_FORCE_RESET() LL_MISC_ForceReset(LL_SDMMC2DLL) 2307 #define __HAL_RCC_SDMMC2DLL_RELEASE_RESET() LL_MISC_ReleaseReset(LL_SDMMC2DLL) 2308 2309 /** 2310 * @} 2311 */ 2312 2313 2314 /** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Disable Embedded memory Clock Sleep Enable Disable 2315 * @brief Enable or disable the embedded memory clock during Low Power (Sleep) mode. 2316 * @note Embedded memory clock gating in SLEEP mode can be used to further reduce 2317 * power consumption. 2318 * @note By default, all embedded memory clocks are disabled during SLEEP mode. 2319 * @{ 2320 */ 2321 #define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM1) 2322 #define __HAL_RCC_AXISRAM1_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM1) 2323 2324 #define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM2) 2325 #define __HAL_RCC_AXISRAM2_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM2) 2326 2327 #define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM3) 2328 #define __HAL_RCC_AXISRAM3_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM3) 2329 2330 #define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM4) 2331 #define __HAL_RCC_AXISRAM4_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM4) 2332 2333 #define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM5) 2334 #define __HAL_RCC_AXISRAM5_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM5) 2335 2336 #define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AXISRAM6) 2337 #define __HAL_RCC_AXISRAM6_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AXISRAM6) 2338 2339 #define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM1) 2340 #define __HAL_RCC_AHBSRAM1_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM1) 2341 2342 #define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_AHBSRAM2) 2343 #define __HAL_RCC_AHBSRAM2_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_AHBSRAM2) 2344 2345 #define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_BKPSRAM) 2346 #define __HAL_RCC_BKPSRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_BKPSRAM) 2347 2348 #define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_FLEXRAM) 2349 #define __HAL_RCC_FLEXRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_FLEXRAM) 2350 2351 #define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_CACHEAXIRAM) 2352 #define __HAL_RCC_CACHEAXIRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_CACHEAXIRAM) 2353 2354 #define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_ENABLE() LL_MEM_EnableClockLowPower(LL_MEM_VENCRAM) 2355 #define __HAL_RCC_VENCRAM_MEM_CLK_SLEEP_DISABLE() LL_MEM_DisableClockLowPower(LL_MEM_VENCRAM) 2356 2357 /** 2358 * @} 2359 */ 2360 2361 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2362 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2363 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2364 * power consumption. 2365 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2366 * @{ 2367 */ 2368 2369 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) 2370 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) 2371 2372 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() LL_AHB1_GRP1_EnableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) 2373 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) 2374 2375 /** 2376 * @} 2377 */ 2378 2379 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2380 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2381 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2382 * power consumption. 2383 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2384 * @{ 2385 */ 2386 2387 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) 2388 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) 2389 2390 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) 2391 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) 2392 2393 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) 2394 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) 2395 2396 /** 2397 * @} 2398 */ 2399 2400 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2401 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2402 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2403 * power consumption. 2404 * @note By default, all peripheral clocks except IAC are disabled during SLEEP mode. 2405 * @note IAC, RIFSC and RIFAF peripheral clocks are always security-protected and thus hidden 2406 * to the non-secure application. 2407 * @{ 2408 */ 2409 2410 #if defined(CRYP) 2411 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) 2412 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) 2413 #endif /* CRYP */ 2414 2415 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) 2416 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) 2417 2418 #if defined (CPU_IN_SECURE_STATE) 2419 #define __HAL_RCC_IAC_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) 2420 #define __HAL_RCC_IAC_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) 2421 #endif /* CPU_IN_SECURE_STATE */ 2422 2423 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) 2424 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) 2425 2426 #if defined (CPU_IN_SECURE_STATE) 2427 #define __HAL_RCC_RIFSC_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) 2428 #define __HAL_RCC_RIFSC_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) 2429 #endif /* CPU_IN_SECURE_STATE */ 2430 2431 #if defined (CPU_IN_SECURE_STATE) 2432 #define __HAL_RCC_RISAF_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) 2433 #define __HAL_RCC_RISAF_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) 2434 #endif /* CPU_IN_SECURE_STATE */ 2435 2436 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) 2437 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) 2438 2439 #if defined(SAES) 2440 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() LL_AHB3_GRP1_EnableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) 2441 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() LL_AHB3_GRP1_DisableClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) 2442 #endif /* SAES */ 2443 2444 /** 2445 * @} 2446 */ 2447 2448 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable 2449 * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 2450 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2451 * power consumption. 2452 * @note By default, all peripheral clocks except PWR are disabled during SLEEP mode. 2453 * @note PWR is always security-protected and thus hidden for non-secure application 2454 * @{ 2455 */ 2456 2457 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) 2458 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) 2459 2460 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) 2461 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) 2462 2463 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) 2464 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) 2465 2466 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) 2467 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) 2468 2469 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) 2470 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) 2471 2472 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) 2473 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) 2474 2475 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) 2476 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) 2477 2478 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) 2479 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) 2480 2481 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) 2482 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) 2483 2484 #define __HAL_RCC_GPION_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) 2485 #define __HAL_RCC_GPION_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) 2486 2487 #define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) 2488 #define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) 2489 2490 #define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) 2491 #define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) 2492 2493 #define __HAL_RCC_GPIOQ_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) 2494 #define __HAL_RCC_GPIOQ_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) 2495 2496 #if defined (CPU_IN_SECURE_STATE) 2497 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() LL_AHB4_GRP1_EnableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) 2498 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() LL_AHB4_GRP1_DisableClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) 2499 #endif /* CPU_IN_SECURE_STATE */ 2500 2501 /** 2502 * @} 2503 */ 2504 2505 /** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5 Peripheral Clock Sleep Enable Disable 2506 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2507 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2508 * power consumption. 2509 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2510 * @{ 2511 */ 2512 2513 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) 2514 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) 2515 2516 #if defined(ETH1) 2517 #define __HAL_RCC_ETH1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) 2518 #define __HAL_RCC_ETH1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) 2519 2520 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) 2521 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) 2522 2523 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) 2524 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) 2525 2526 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) 2527 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) 2528 #endif /* ETH1 */ 2529 2530 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) 2531 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) 2532 2533 #if defined(GFXMMU) 2534 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) 2535 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) 2536 #endif /* GFXMMU */ 2537 2538 #if defined(GPU2D) 2539 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) 2540 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) 2541 #endif /* GPU2D */ 2542 2543 #define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) 2544 #define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) 2545 2546 #if defined(JPEG) 2547 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) 2548 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) 2549 #endif /* JPEG */ 2550 2551 #define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) 2552 #define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) 2553 2554 #define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) 2555 #define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) 2556 2557 #define __HAL_RCC_XSPI3_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) 2558 #define __HAL_RCC_XSPI3_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) 2559 2560 #define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) 2561 #define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) 2562 2563 #define __HAL_RCC_MCE1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) 2564 #define __HAL_RCC_MCE1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) 2565 2566 #define __HAL_RCC_MCE2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) 2567 #define __HAL_RCC_MCE2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) 2568 2569 #define __HAL_RCC_MCE3_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) 2570 #define __HAL_RCC_MCE3_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) 2571 2572 #define __HAL_RCC_MCE4_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) 2573 #define __HAL_RCC_MCE4_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) 2574 2575 #define __HAL_RCC_CACHEAXI_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) 2576 #define __HAL_RCC_CACHEAXI_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) 2577 2578 #define __HAL_RCC_NPU_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) 2579 #define __HAL_RCC_NPU_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) 2580 2581 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) 2582 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) 2583 2584 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) 2585 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) 2586 2587 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) 2588 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) 2589 2590 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) 2591 #define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) 2592 2593 #define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) 2594 #define __HAL_RCC_USB1_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) 2595 2596 #define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) 2597 #define __HAL_RCC_USB2_OTG_HS_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) 2598 2599 #define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_ENABLE() LL_AHB5_GRP1_EnableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) 2600 #define __HAL_RCC_USB2_OTG_HS_PHY_CLK_SLEEP_DISABLE() LL_AHB5_GRP1_DisableClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) 2601 2602 /** 2603 * @} 2604 */ 2605 2606 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2607 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2608 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2609 * power consumption. 2610 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2611 * @{ 2612 */ 2613 2614 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) 2615 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) 2616 2617 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) 2618 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) 2619 2620 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) 2621 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) 2622 2623 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) 2624 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) 2625 2626 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) 2627 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) 2628 2629 #define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) 2630 #define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) 2631 2632 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) 2633 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) 2634 2635 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) 2636 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) 2637 2638 #define __HAL_RCC_SPDIFRX1_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) 2639 #define __HAL_RCC_SPDIFRX1_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) 2640 2641 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) 2642 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) 2643 2644 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) 2645 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) 2646 2647 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) 2648 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) 2649 2650 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) 2651 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) 2652 2653 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) 2654 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) 2655 2656 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) 2657 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) 2658 2659 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) 2660 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) 2661 2662 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) 2663 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) 2664 2665 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) 2666 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) 2667 2668 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) 2669 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) 2670 2671 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) 2672 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) 2673 2674 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) 2675 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) 2676 2677 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) 2678 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) 2679 2680 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART2) 2681 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART2) 2682 2683 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_USART3) 2684 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_USART3) 2685 2686 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART4) 2687 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART4) 2688 2689 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART5) 2690 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART5) 2691 2692 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART7) 2693 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART7) 2694 2695 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_UART8) 2696 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_UART8) 2697 2698 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() LL_APB1_GRP2_EnableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) 2699 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() LL_APB1_GRP2_DisableClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) 2700 2701 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() LL_APB1_GRP1_EnableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) 2702 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() LL_APB1_GRP1_DisableClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) 2703 2704 /** 2705 * @} 2706 */ 2707 2708 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2709 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2710 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2711 * power consumption. 2712 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2713 * @{ 2714 */ 2715 2716 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) 2717 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) 2718 2719 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) 2720 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) 2721 2722 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) 2723 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) 2724 2725 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) 2726 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) 2727 2728 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) 2729 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) 2730 2731 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) 2732 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) 2733 2734 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) 2735 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) 2736 2737 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) 2738 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) 2739 2740 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) 2741 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) 2742 2743 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) 2744 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) 2745 2746 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) 2747 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) 2748 2749 #define __HAL_RCC_TIM18_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) 2750 #define __HAL_RCC_TIM18_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) 2751 2752 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART1) 2753 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART1) 2754 2755 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART6) 2756 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART6) 2757 2758 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_UART9) 2759 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_UART9) 2760 2761 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockLowPower(LL_APB2_GRP1_PERIPH_USART10) 2762 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockLowPower(LL_APB2_GRP1_PERIPH_USART10) 2763 2764 /** 2765 * @} 2766 */ 2767 2768 /** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable APB4 Peripheral Clock Sleep Enable Disable 2769 * @brief Enable or disable the APB4 peripheral clock during Low Power (Sleep) mode. 2770 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2771 * power consumption. 2772 * @note By default, all peripheral clocks except BSEC are disabled during SLEEP mode. 2773 * @note BSEC peripheral clock is always security-protected and thus hidden to the non-secure 2774 * application. 2775 * @{ 2776 */ 2777 2778 #if defined (CPU_IN_SECURE_STATE) 2779 #define __HAL_RCC_BSEC_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) 2780 #define __HAL_RCC_BSEC_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) 2781 #endif /* CPU_IN_SECURE_STATE */ 2782 2783 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_DTS) 2784 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_DTS) 2785 2786 #define __HAL_RCC_HDP_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_HDP) 2787 #define __HAL_RCC_HDP_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_HDP) 2788 2789 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) 2790 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) 2791 2792 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) 2793 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) 2794 2795 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) 2796 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) 2797 2798 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) 2799 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) 2800 2801 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) 2802 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) 2803 2804 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) 2805 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) 2806 2807 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTC) 2808 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTC) 2809 2810 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) 2811 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) 2812 2813 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) 2814 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) 2815 2816 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() LL_APB4_GRP2_EnableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) 2817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() LL_APB4_GRP2_DisableClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) 2818 2819 #define __HAL_RCC_VREFBUF_CLK_SLEEP_ENABLE() LL_APB4_GRP1_EnableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) 2820 #define __HAL_RCC_VREFBUF_CLK_SLEEP_DISABLE() LL_APB4_GRP1_DisableClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) 2821 2822 /** 2823 * @} 2824 */ 2825 2826 /** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable APB5 Peripheral Clock Sleep Enable Disable 2827 * @brief Enable or disable the APB5 peripheral clock during Low Power (Sleep) mode. 2828 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2829 * power consumption. 2830 * @note By default, all peripheral clocks are disabled during SLEEP mode. 2831 * @{ 2832 */ 2833 2834 #define __HAL_RCC_CSI_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_CSI) 2835 #define __HAL_RCC_CSI_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_CSI) 2836 2837 #define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) 2838 #define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) 2839 2840 #define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) 2841 #define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) 2842 2843 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) 2844 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) 2845 2846 #define __HAL_RCC_VENC_CLK_SLEEP_ENABLE() LL_APB5_GRP1_EnableClockLowPower(LL_APB5_GRP1_PERIPH_VENC) 2847 #define __HAL_RCC_VENC_CLK_SLEEP_DISABLE() LL_APB5_GRP1_DisableClockLowPower(LL_APB5_GRP1_PERIPH_VENC) 2848 2849 /** 2850 * @} 2851 */ 2852 2853 /** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Disable Misc Configuration Clock Sleep Enable Disable 2854 * @brief Enable or disable the misc configuration clock during Low Power (Sleep) mode. 2855 * @note After reset, the misc configuration clock is disabled and 2856 * the application software has to enable this clock before using it. 2857 * @note After wakeup from SLEEP mode, the misc configuration clock is enabled again. 2858 * @note DBG clock is always security-protected and thus hidden the non-secure application. 2859 * @{ 2860 */ 2861 2862 #if defined (CPU_IN_SECURE_STATE) 2863 #define __HAL_RCC_DBG_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_DBG) 2864 #define __HAL_RCC_DBG_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_DBG) 2865 #endif /* CPU_IN_SECURE_STATE */ 2866 2867 #define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_XSPIPHYCOMP) 2868 #define __HAL_RCC_XSPIPHYCOMP_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_XSPIPHYCOMP) 2869 2870 #define __HAL_RCC_PER_CLK_SLEEP_ENABLE() LL_MISC_EnableClockLowPower(LL_PER) 2871 #define __HAL_RCC_PER_CLK_SLEEP_DISABLE() LL_MISC_DisableClockLowPower(LL_PER) 2872 2873 /** 2874 * @} 2875 */ 2876 2877 /** @defgroup RCC_Embedded_Mem_Clock_Sleep_Enable_Status Embedded Memory Clock Sleep Enabled Status 2878 * @brief Check whether the embedded memory clock sleep is enabled or not. 2879 * @note After reset, some embedded memory clocks are disabled 2880 * and the application software has to enable these memory clocks before using them. 2881 * @{ 2882 */ 2883 2884 #define __HAL_RCC_AXISRAM1_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM1) 2885 #define __HAL_RCC_AXISRAM2_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM2) 2886 #define __HAL_RCC_AXISRAM3_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM3) 2887 #define __HAL_RCC_AXISRAM4_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM4) 2888 #define __HAL_RCC_AXISRAM5_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM5) 2889 #define __HAL_RCC_AXISRAM6_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AXISRAM6) 2890 #define __HAL_RCC_AHBSRAM1_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM1) 2891 #define __HAL_RCC_AHBSRAM2_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_AHBSRAM2) 2892 #define __HAL_RCC_BKPSRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_BKPSRAM) 2893 #define __HAL_RCC_FLEXRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_FLEXRAM) 2894 #define __HAL_RCC_CACHEAXIRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_CACHEAXIRAM) 2895 #define __HAL_RCC_VENCRAM_MEM_IS_CLK_SLEEP_ENABLED() LL_MEM_IsEnabledClockLowPower(LL_MEM_VENCRAM) 2896 2897 /** 2898 * @} 2899 */ 2900 2901 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Status AHB1 Peripheral Clock Sleep Enabled Status 2902 * @brief Check whether the AHB1 peripheral clock sleep is enabled or not. 2903 * @note After reset, the peripheral clock (used for registers read/write access) 2904 * is disabled and the application software has to enable this clock before 2905 * using it. 2906 * @{ 2907 */ 2908 2909 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_ADC12) 2910 2911 #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() LL_AHB1_GRP1_IsEnabledClockLowPower(LL_AHB1_GRP1_PERIPH_GPDMA1) 2912 2913 /** 2914 * @} 2915 */ 2916 2917 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Status AHB2 Peripheral Clock Sleep Enabled Status 2918 * @brief Check whether the AHB2 peripheral clock sleep is enabled or not. 2919 * @note After reset, the peripheral clock (used for registers read/write access) 2920 * is disabled and the application software has to enable this clock before 2921 * using it. 2922 * @{ 2923 */ 2924 2925 #define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_ADF1) 2926 2927 #define __HAL_RCC_MDF1_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_MDF1) 2928 2929 #define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() LL_AHB2_GRP1_IsEnabledClockLowPower(LL_AHB2_GRP1_PERIPH_RAMCFG) 2930 2931 /** 2932 * @} 2933 */ 2934 2935 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Status AHB3 Peripheral Clock Sleep Enabled Status 2936 * @brief Check whether the AHB3 peripheral clock sleep is enabled or not. 2937 * @note After reset, the peripheral clock (used for registers read/write access) 2938 * is disabled and the application software has to enable this clock before 2939 * using it. 2940 * @{ 2941 */ 2942 2943 #if defined(CRYP) 2944 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_CRYP) 2945 #endif /* CRYP */ 2946 2947 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_HASH) 2948 2949 #define __HAL_RCC_IAC_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_IAC) 2950 2951 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_PKA) 2952 2953 #define __HAL_RCC_RIFSC_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RIFSC) 2954 2955 #define __HAL_RCC_RISAF_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RISAF) 2956 2957 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_RNG) 2958 2959 #if defined(SAES) 2960 #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() LL_AHB3_GRP1_IsEnabledClockLowPower(LL_AHB3_GRP1_PERIPH_SAES) 2961 #endif /* SAES */ 2962 2963 /** 2964 * @} 2965 */ 2966 2967 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Status AHB4 Peripheral Clock Sleep Enabled Status 2968 * @brief Check whether the AHB4 peripheral clock sleep is enabled or not. 2969 * @note After reset, the peripheral clock (used for registers read/write access) 2970 * is disabled and the application software has to enable this clock before 2971 * using it. 2972 * @{ 2973 */ 2974 2975 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_CRC) 2976 2977 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOA) 2978 2979 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOB) 2980 2981 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOC) 2982 2983 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOD) 2984 2985 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOE) 2986 2987 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOF) 2988 2989 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOG) 2990 2991 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOH) 2992 2993 #define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPION) 2994 2995 #define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOO) 2996 2997 #define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOP) 2998 2999 #define __HAL_RCC_GPIOQ_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_GPIOQ) 3000 3001 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() LL_AHB4_GRP1_IsEnabledClockLowPower(LL_AHB4_GRP1_PERIPH_PWR) 3002 3003 /** 3004 * @} 3005 */ 3006 3007 /** @defgroup RCC_AHB5_Clock_Sleep_Enable_Status AHB5 Peripheral Clock Sleep Enabled Status 3008 * @brief Check whether the AHB5 peripheral clock sleep is enabled or not. 3009 * @note After reset, the peripheral clock (used for registers read/write access) 3010 * is disabled and the application software has to enable this clock before 3011 * using it. 3012 * @{ 3013 */ 3014 3015 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_DMA2D) 3016 3017 #if defined(ETH1) 3018 #define __HAL_RCC_ETH1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1) 3019 3020 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1MAC) 3021 3022 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1TX) 3023 3024 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_ETH1RX) 3025 #endif /* ETH1 */ 3026 3027 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_FMC) 3028 3029 #if defined(GFXMMU) 3030 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GFXMMU) 3031 #endif /* GFXMMU */ 3032 3033 #if defined(GPU2D) 3034 #define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_GPU2D) 3035 #endif /* GPU2D */ 3036 3037 #define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_HPDMA1) 3038 3039 #if defined(JPEG) 3040 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_JPEG) 3041 #endif /* JPEG */ 3042 3043 #define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI1) 3044 3045 #define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI2) 3046 3047 #define __HAL_RCC_XSPI3_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPI3) 3048 3049 #define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_XSPIM) 3050 3051 #define __HAL_RCC_MCE1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE1) 3052 3053 #define __HAL_RCC_MCE2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE2) 3054 3055 #define __HAL_RCC_MCE3_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE3) 3056 3057 #define __HAL_RCC_MCE4_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_MCE4) 3058 3059 #define __HAL_RCC_CACHEAXI_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_CACHEAXI) 3060 3061 #define __HAL_RCC_NPU_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_NPU) 3062 3063 #define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_PSSI) 3064 3065 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC1) 3066 3067 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_SDMMC2) 3068 3069 #define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG1) 3070 3071 #define __HAL_RCC_USB1_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY1) 3072 3073 #define __HAL_RCC_USB2_OTG_HS_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTG2) 3074 3075 #define __HAL_RCC_USB2_OTG_HS_PHY_IS_CLK_SLEEP_ENABLED() LL_AHB5_GRP1_IsEnabledClockLowPower(LL_AHB5_GRP1_PERIPH_OTGPHY2) 3076 3077 /** 3078 * @} 3079 */ 3080 3081 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Status APB1 Peripheral Clock Sleep Enabled Status 3082 * @brief Check whether the APB1 peripheral clock sleep is enabled or not. 3083 * @note After reset, the peripheral clock (used for registers read/write access) 3084 * is disabled and the application software has to enable this clock before 3085 * using it. 3086 * @{ 3087 */ 3088 3089 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_FDCAN) 3090 3091 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C1) 3092 3093 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C2) 3094 3095 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I2C3) 3096 3097 #define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C1) 3098 3099 #define __HAL_RCC_I3C2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_I3C2) 3100 3101 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_LPTIM1) 3102 3103 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_MDIOS) 3104 3105 #define __HAL_RCC_SPDIFRX1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPDIFRX1) 3106 3107 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI2) 3108 3109 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_SPI3) 3110 3111 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM2) 3112 3113 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM3) 3114 3115 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM4) 3116 3117 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM5) 3118 3119 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM6) 3120 3121 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM7) 3122 3123 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM10) 3124 3125 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM11) 3126 3127 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM12) 3128 3129 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM13) 3130 3131 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_TIM14) 3132 3133 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART2) 3134 3135 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_USART3) 3136 3137 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART4) 3138 3139 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART5) 3140 3141 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART7) 3142 3143 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_UART8) 3144 3145 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP2_IsEnabledClockLowPower(LL_APB1_GRP2_PERIPH_UCPD1) 3146 3147 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() LL_APB1_GRP1_IsEnabledClockLowPower(LL_APB1_GRP1_PERIPH_WWDG) 3148 3149 /** 3150 * @} 3151 */ 3152 3153 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Status APB2 Peripheral Clock Sleep Enabled Status 3154 * @brief Check whether the APB2 peripheral clock sleep is enabled or not. 3155 * @note After reset, the peripheral clock (used for registers read/write access) 3156 * is disabled and the application software has to enable this clock before 3157 * using it. 3158 * @{ 3159 */ 3160 3161 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI1) 3162 3163 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SAI2) 3164 3165 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI1) 3166 3167 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI4) 3168 3169 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_SPI5) 3170 3171 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM1) 3172 3173 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM8) 3174 3175 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM9) 3176 3177 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM15) 3178 3179 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM16) 3180 3181 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM17) 3182 3183 #define __HAL_RCC_TIM18_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_TIM18) 3184 3185 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART1) 3186 3187 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART6) 3188 3189 #define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_UART9) 3190 3191 #define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() LL_APB2_GRP1_IsEnabledClockLowPower(LL_APB2_GRP1_PERIPH_USART10) 3192 3193 /** 3194 * @} 3195 */ 3196 3197 /** @defgroup RCC_APB4_Clock_Sleep_Enable_Status APB4 Peripheral Clock Sleep Enabled Status 3198 * @brief Check whether the APB4 peripheral clock sleep is enabled or not. 3199 * @note After reset, the peripheral clock (used for registers read/write access) 3200 * is disabled and the application software has to enable this clock before 3201 * using it. 3202 * @{ 3203 */ 3204 3205 #define __HAL_RCC_BSEC_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_BSEC) 3206 3207 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_DTS) 3208 3209 #define __HAL_RCC_HDP_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_HDP) 3210 3211 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_I2C4) 3212 3213 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM2) 3214 3215 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM3) 3216 3217 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM4) 3218 3219 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPTIM5) 3220 3221 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_LPUART1) 3222 3223 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTC) 3224 3225 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_RTCAPB) 3226 3227 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_SPI6) 3228 3229 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP2_IsEnabledClockLowPower(LL_APB4_GRP2_PERIPH_SYSCFG) 3230 3231 #define __HAL_RCC_VREFBUF_IS_CLK_SLEEP_ENABLED() LL_APB4_GRP1_IsEnabledClockLowPower(LL_APB4_GRP1_PERIPH_VREFBUF) 3232 3233 /** 3234 * @} 3235 */ 3236 3237 /** @defgroup RCC_APB5_Clock_Sleep_Enable_Status APB5 Peripheral Clock Sleep Enabled Status 3238 * @brief Check whether the APB5 peripheral clock sleep is enabled or not. 3239 * @note After reset, the peripheral clock (used for registers read/write access) 3240 * is disabled and the application software has to enable this clock before 3241 * using it. 3242 * @{ 3243 */ 3244 3245 #define __HAL_RCC_CSI_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_CSI) 3246 3247 #define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_DCMIPP) 3248 3249 #define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_GFXTIM) 3250 3251 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_LTDC) 3252 3253 #define __HAL_RCC_VENC_IS_CLK_SLEEP_ENABLED() LL_APB5_GRP1_IsEnabledClockLowPower(LL_APB5_GRP1_PERIPH_VENC) 3254 3255 3256 /** 3257 * @} 3258 */ 3259 3260 /** @defgroup RCC_MISC_Configuration_Clock_Sleep_Enable_Status Misc Configuration Clock Sleep Enabled Status 3261 * @brief Check whether the misc configuration clock sleep is enabled or not. 3262 * @note After reset, the misc configuration clock is disabled and 3263 * the application software has to enable this clock before using it. 3264 * @{ 3265 */ 3266 3267 #define __HAL_RCC_DBG_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_DBG) 3268 3269 #define __HAL_RCC_XSPIPHYCOMP_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_XSPIPHYCOMP) 3270 3271 #define __HAL_RCC_PER_IS_CLK_SLEEP_ENABLED() LL_MISC_IsEnabledClockLowPower(LL_PER) 3272 3273 /** 3274 * @} 3275 */ 3276 3277 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 3278 * @note After enabling the HSI, the application software should wait on 3279 * HSIRDY flag to be set indicating that the HSI clock is stable 3280 * and that HSI clock can be used to clock the PLL and/or system clock. 3281 * @note HSI can not be stopped if it is used directly or through the PLL 3282 * as system clock. In this case, you have to select another source 3283 * of the system clock then stop the HSI. 3284 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3285 * @param __STATE__ specifies the new state of the HSI. 3286 * This parameter can be one of the following values: 3287 * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator 3288 * @arg @ref RCC_HSI_ON turn ON the HSI oscillator 3289 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3290 * clock cycles. 3291 */ 3292 #define __HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION, (uint32_t)(__STATE__)) 3293 3294 /** @brief Macro to configure the Internal High Speed oscillator (HSI) clock divider. 3295 * @param __HSIDIV__ specifies the HSI division factor. 3296 * This parameter can be one of the following values: 3297 * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) 3298 * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 3299 * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 3300 * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 3301 */ 3302 #define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) LL_RCC_HSI_SetDivider((uint32_t)(__HSIDIV__)) 3303 3304 /** @brief Macro to get the HSI divider. 3305 * @retval The HSI divider. The returned value can be one of the following values: 3306 * of the following: 3307 * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) 3308 * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 3309 * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 3310 * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 3311 */ 3312 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)LL_RCC_HSI_GetDivider()) 3313 3314 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 3315 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3316 * It is used (enabled by hardware) as system clock source after start-up 3317 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3318 * of the HSE used directly or indirectly as system clock (if the Clock 3319 * Security System CSS is enabled). 3320 * @note HSI can not be stopped if it is used as system clock source. In this case, 3321 * you have to select another source of the system clock then stop the HSI. 3322 * @note After enabling the HSI, the application software should wait on HSIRDY 3323 * flag to be set indicating that HSI clock is stable and can be used as 3324 * system clock source. 3325 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3326 * clock cycles. 3327 */ 3328 #define __HAL_RCC_HSI_ENABLE() LL_RCC_HSI_Enable() 3329 3330 #define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable() 3331 3332 /** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. 3333 * @note The calibration is used to compensate for the variations in voltage 3334 * and temperature that influence the frequency of the internal HSI RC. 3335 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 3336 * (default is RCC_HSICALIBRATION_DEFAULT). 3337 * This parameter must be a number between 0 and 127. 3338 * @retval None 3339 */ 3340 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3341 LL_RCC_HSI_SetCalibTrimming((uint32_t)(__HSICALIBRATIONVALUE__)); 3342 3343 /** 3344 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3345 * in STOP mode to be quickly available as kernel clock for some peripherals. 3346 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3347 * speed because of the HSI start-up time. 3348 * @note The enable of this function has not effect on the HSION bit. 3349 * This parameter can be: ENABLE or DISABLE. 3350 * @retval None 3351 */ 3352 #define __HAL_RCC_HSISTOP_ENABLE() LL_RCC_HSI_EnableInStopMode() 3353 3354 #define __HAL_RCC_HSISTOP_DISABLE() LL_RCC_HSI_DisableInStopMode() 3355 3356 /** 3357 * @brief Macros to enable or disable the Internal oscillator (MSI). 3358 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3359 * It is used (enabled by hardware) as system clock source after 3360 * start-up from Reset, wakeup from STOP and STANDBY mode, or in case 3361 * of failure of the HSE used directly or indirectly as system clock 3362 * (if the Clock Security System CSS is enabled). 3363 * @note MSI can not be stopped if it is used as system clock source. 3364 * In this case, you have to select another source of the system 3365 * clock then stop the MSI. 3366 * @note After enabling the MSI, the application software should wait on 3367 * MSIRDY flag to be set indicating that MSI clock is stable and can 3368 * be used as system clock source. 3369 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3370 * clock cycles. 3371 */ 3372 #define __HAL_RCC_MSI_ENABLE() LL_RCC_MSI_Enable() 3373 3374 #define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable() 3375 3376 /** @brief Macro to configure the Internal oscillator (MSI) frequency. 3377 * @param __FREQ__ specifies the MSI frequency. 3378 * This parameter can be one of the following values: 3379 * @arg RCC_MSI_FREQ_4MHZ 4MHz selection (default after reset) 3380 * @arg RCC_MSI_FREQ_16MHZ 16MHz selection 3381 */ 3382 #define __HAL_RCC_MSI_FREQUENCY_CONFIG(__FREQ__) LL_RCC_MSI_SetFrequency((uint32_t)(__FREQ__)) 3383 3384 /** @brief Macro to adjust the Internal oscillator (MSI) calibration value. 3385 * @note The calibration is used to compensate for the variations in voltage 3386 * and temperature that influence the frequency of the internal MSI RC. 3387 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 3388 * (default is RCC_MSICALIBRATION_DEFAULT). 3389 * This parameter must be a number between 0 and 0x1F. 3390 * @retval None 3391 */ 3392 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 3393 LL_RCC_MSI_SetCalibTrimming((uint32_t)(__MSICALIBRATIONVALUE__)) 3394 3395 /** 3396 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (MSI) 3397 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 3398 * @note Keeping the MSI ON in STOP mode allows to avoid slowing down the communication 3399 * speed because of the MSI start-up time. 3400 * @note The enable of this function has not effect on the MSION bit. 3401 * This parameter can be: ENABLE or DISABLE. 3402 * @retval None 3403 */ 3404 #define __HAL_RCC_MSISTOP_ENABLE() LL_RCC_MSI_EnableInStopMode() 3405 3406 #define __HAL_RCC_MSISTOP_DISABLE() LL_RCC_MSI_DisableInStopMode() 3407 3408 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 3409 * @note After enabling the LSI, the application software should wait on 3410 * LSIRDY flag to be set indicating that LSI clock is stable and can 3411 * be used to clock the IWDG and/or the RTC. 3412 * @note LSI can not be disabled if the IWDG is running. 3413 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 3414 * clock cycles. 3415 */ 3416 #define __HAL_RCC_LSI_ENABLE() LL_RCC_LSI_Enable() 3417 3418 #define __HAL_RCC_LSI_DISABLE() LL_RCC_LSI_Disable() 3419 3420 /** 3421 * @brief Macros to configure the External High Speed oscillator (HSE). 3422 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), 3423 * the application software should wait on HSERDY flag to be set indicating that HSE clock 3424 * is stable and can be used to clock the PLL and/or system clock and peripheral kernel 3425 * clock source. 3426 * @note HSE state can not be changed if it is used directly or through the 3427 * PLL as system clock. In this case, you have to select another source 3428 * of the system clock then change the HSE state (ex. disable it). 3429 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 3430 * @param __STATE__ specifies the new state of the HSE. 3431 * This parameter can be one of the following values: 3432 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 3433 * 6 HSE oscillator clock cycles. 3434 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator. 3435 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock (analog). 3436 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with external digital clock. 3437 */ 3438 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 3439 do { \ 3440 if ((__STATE__) == RCC_HSE_ON) \ 3441 { \ 3442 WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ 3443 } \ 3444 else if ((__STATE__) == RCC_HSE_OFF) \ 3445 { \ 3446 WRITE_REG(RCC->CCR, RCC_CCR_HSEONC); \ 3447 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ 3448 } \ 3449 else if ((__STATE__) == RCC_HSE_BYPASS) \ 3450 { \ 3451 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEBYP); \ 3452 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT); \ 3453 WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ 3454 } \ 3455 else if ((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 3456 { \ 3457 SET_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ 3458 WRITE_REG(RCC->CSR, RCC_CSR_HSEONS); \ 3459 } \ 3460 else \ 3461 { \ 3462 WRITE_REG(RCC->CCR, RCC_CCR_HSEONC); \ 3463 CLEAR_BIT(RCC->HSECFGR, RCC_HSECFGR_HSEEXT | RCC_HSECFGR_HSEBYP); \ 3464 } \ 3465 } while(0) 3466 3467 /** 3468 * @brief Macros to configure the External Low Speed oscillator (LSE). 3469 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 3470 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 3471 * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). 3472 A duty cycle close to 50% is recommended. 3473 * @note As the LSE is in the Backup domain and write access is denied to 3474 * this domain after reset, you have to enable write access using 3475 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3476 * (to be done once after reset). 3477 * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL), the application 3478 * software should wait on LSERDY flag to be set indicating that LSE clock 3479 * is stable and can be used to clock the RTC. 3480 * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) 3481 * @param __STATE__ specifies the new state of the LSE. 3482 * This parameter can be one of the following values: 3483 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 3484 * 6 LSE oscillator clock cycles. 3485 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 3486 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock (analog). 3487 * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. 3488 */ 3489 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 3490 do { \ 3491 if((__STATE__) == RCC_LSE_ON) \ 3492 { \ 3493 WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ 3494 } \ 3495 else if((__STATE__) == RCC_LSE_OFF) \ 3496 { \ 3497 WRITE_REG(RCC->CCR, RCC_CCR_LSEONC); \ 3498 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ 3499 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ 3500 } \ 3501 else if((__STATE__) == RCC_LSE_BYPASS) \ 3502 { \ 3503 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ 3504 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ 3505 WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ 3506 } \ 3507 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 3508 { \ 3509 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ 3510 SET_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ 3511 WRITE_REG(RCC->CSR, RCC_CSR_LSEONS); \ 3512 } \ 3513 else \ 3514 { \ 3515 WRITE_REG(RCC->CCR, RCC_CCR_LSEONC); \ 3516 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEBYP); \ 3517 CLEAR_BIT(RCC->LSECFGR, RCC_LSECFGR_LSEEXT); \ 3518 } \ 3519 } while(0) 3520 3521 /** @brief Macros to enable or disable the the RTC clock. 3522 * @note These macros must be used only after the RTC clock source was selected. 3523 */ 3524 #define __HAL_RCC_RTC_ENABLE() LL_RCC_EnableRTC() 3525 3526 #define __HAL_RCC_RTC_DISABLE() LL_RCC_DisableRTC() 3527 3528 /** @brief Macro to configure the RTC clock (RTCCLK). 3529 * @note As the RTC clock configuration bits are in the Backup domain and write 3530 * access is denied to this domain after reset, you have to enable write 3531 * access using the Power Backup Access macro before to configure 3532 * the RTC clock source (to be done once after reset). 3533 * @note Once the RTC clock is configured it cannot be changed unless the 3534 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() and 3535 * __HAL_RCC_BACKUPRESET_RELEASE() macros, or by a Power On Reset (POR). 3536 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 3537 * This parameter can be one of the following values: 3538 * RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3539 * RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3540 * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected 3541 * as RTC clock, where x:[1,64] 3542 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3543 * work in STOP and STANDBY modes, and can be used as wakeup source. 3544 * However, when the HSE clock is used as RTC clock source, the RTC 3545 * cannot be used in STOP and STANDBY modes. 3546 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3547 * RTC clock source). 3548 */ 3549 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 3550 do { \ 3551 if (((__RTC_CLKSOURCE__) & (RCC_CCIPR7_RTCSEL)) == RCC_CCIPR7_RTCSEL) { \ 3552 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ 3553 } \ 3554 LL_RCC_SetRTCClockSource((__RTC_CLKSOURCE__) & RCC_CCIPR7_RTCSEL); \ 3555 } while(0) 3556 3557 /** @brief Macro to configure the RTC clock prescaler for HSE for RTCCLK. 3558 * @param __RTC_CLKSOURCE__ specifies the RTC clock prescaler for HSE. 3559 * This parameter can be one of the following values: 3560 * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected 3561 * as RTC clock, where x:[1,64] 3562 */ 3563 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) \ 3564 LL_RCC_SetRTC_HSEPrescaler(((__RTC_CLKSOURCE__) & (~RCC_CCIPR7_RTCSEL))) 3565 3566 /** @brief Macros to get the RTC clock (RTCCLK). 3567 * @retval The returned value can be one of the following values: 3568 * RCC_RTCCLKSOURCE_DISABLE No clock selected as RTC clock. 3569 * RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3570 * RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3571 * RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected 3572 * as RTC clock, where x:[1,64] 3573 */ 3574 #define __HAL_RCC_GET_RTC_SOURCE() \ 3575 ((READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL) == RCC_CCIPR7_RTCSEL) ? \ 3576 (READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCPRE) | RCC_CCIPR7_RTCSEL) : READ_BIT(RCC->CCIPR7, RCC_CCIPR7_RTCSEL)) 3577 3578 /** @brief Macros to force or release the Vswitch backup domain reset. 3579 * @note This function resets the RTC peripheral (including the backup registers) 3580 * and the RTC clock source selection in RCC_BDCR register. 3581 * @note The BKPSRAM is not affected by this reset. 3582 */ 3583 #define __HAL_RCC_BACKUPRESET_FORCE() LL_RCC_ForceBackupDomainReset() 3584 3585 #define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset() 3586 3587 /** @brief Macros to enable or disable the PLL1. 3588 * @note After enabling the PLL1, the application software should wait on 3589 * PLL1RDY flag to be set indicating that PLL1 clock is stable and can 3590 * be used as CPU and/or system bus and/or kernel clock source thru ICx. 3591 * @note The PLL1 can not be disabled if it is used as system clock source 3592 * @note The PLL1 is disabled by hardware when entering STOP and STANDBY modes. 3593 */ 3594 #define __HAL_RCC_PLL1_ENABLE() LL_RCC_PLL1_Enable() 3595 3596 #define __HAL_RCC_PLL1_DISABLE() LL_RCC_PLL1_Disable() 3597 3598 /** 3599 * @brief Macros to enable or disable the PLL1 post divider 1, post divider 2 3600 * and PLL1 clock output when not in bypass mode. 3601 */ 3602 #define __HAL_RCC_PLL1CLKOUT_ENABLE() LL_RCC_PLL1P_Enable() 3603 #define __HAL_RCC_PLL1CLKOUT_DISABLE() LL_RCC_PLL1P_Disable() 3604 3605 /** 3606 * @brief Macro to configure the PLL1 in integer mode with clock source, multiplication 3607 * and division factors. 3608 * @note This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed 3609 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3610 * 3611 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3612 * This parameter can be one of the following values: 3613 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3614 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3615 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3616 * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry 3617 * @note This clock source cannot be changed on any PLL if another PLL is already enabled. 3618 * 3619 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3620 * This parameter must be a number between 1 and 63. 3621 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3622 * frequency ranges from 1 to 50 MHz. 3623 * 3624 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 3625 * This parameter must be a number between 16 and 2500. 3626 * 3627 * @param __PLLP1__ specifies the post division factor 1 for system clock. 3628 * This parameter must be a number between 1 and 7. 3629 * 3630 * @param __PLLP2__ specifies the post division factor 2 for system clock. 3631 * This parameter must be a number between 1 and 7. 3632 * 3633 * @retval None 3634 */ 3635 3636 #define __HAL_RCC_PLL1_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ 3637 do { \ 3638 MODIFY_REG(RCC->PLL1CFGR1, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DIVN), \ 3639 ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL1CFGR1_PLL1DIVM_Pos) | (((__PLLN__) << RCC_PLL1CFGR1_PLL1DIVN_Pos)))); \ 3640 MODIFY_REG(RCC->PLL1CFGR2, RCC_PLL1CFGR2_PLL1DIVNFRAC, 0U); \ 3641 MODIFY_REG(RCC->PLL1CFGR3, (RCC_PLL1CFGR3_PLL1PDIV1 | RCC_PLL1CFGR3_PLL1PDIV2), \ 3642 ((((__PLLP1__) << RCC_PLL1CFGR3_PLL1PDIV1_Pos) & RCC_PLL1CFGR3_PLL1PDIV1) | \ 3643 ((((__PLLP2__) << RCC_PLL1CFGR3_PLL1PDIV2_Pos) & RCC_PLL1CFGR3_PLL1PDIV2)))); \ 3644 } while(0) 3645 3646 /** @brief Macro to configure the PLL1 clock source. 3647 * @note This macro must be used only when the PLL1 is disabled or the PLL1 output is bypassed 3648 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3649 * 3650 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3651 * This parameter can be one of the following values: 3652 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3653 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3654 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3655 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry 3656 */ 3657 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL1_SetSource((uin32_t)__PLLSOURCE__) 3658 3659 /** @brief Macro to get the clock source used as PLL1 clock source. 3660 * @retval The oscillator used as PLL clock source. 3661 * The returned value can be one of the following values: 3662 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3663 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3664 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3665 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. 3666 */ 3667 #define __HAL_RCC_GET_PLL1_OSCSOURCE() LL_RCC_PLL1_GetSource() 3668 3669 /** 3670 * @brief Macro to configure the PLL1 clock Fractional Part Of The Multiplication Factor 3671 * @note This configuration cannot be requested when the PLL1 has been enabled. 3672 * 3673 * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO. 3674 * It should be a value between 0 and 2^24. 3675 * @retval None 3676 */ 3677 #define __HAL_RCC_PLL1_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL1_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) 3678 3679 /** 3680 * @brief Macro to enable the PLL1 clock Fractional mode 3681 * @note This configuration cannot be requested when the PLL1 has been enabled. 3682 * @retval None 3683 */ 3684 #define __HAL_RCC_PLL1_FRACN_ENABLE() LL_RCC_PLL1_EnableFractionalModulationSpreadSpectrum() 3685 3686 /** 3687 * @brief Macro to disable the PLL1 clock Fractional mode 3688 * @note This configuration cannot be requested when the PLL1 has been enabled. 3689 * @retval None 3690 */ 3691 #define __HAL_RCC_PLL1_FRACN_DISABLE() LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum() 3692 3693 /** @brief Macros to enable or disable PLL2. 3694 * @note After enabling PLL2, the application software should wait on 3695 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 3696 * be used as CPU and/or system bus and/or kernel clock source thru ICx. 3697 * @note PLL2 is disabled by hardware when entering Stop and Standby modes. 3698 */ 3699 #define __HAL_RCC_PLL2_ENABLE() LL_RCC_PLL2_Enable() 3700 #define __HAL_RCC_PLL2_DISABLE() LL_RCC_PLL2_Disable() 3701 3702 /** 3703 * @brief Macros to enable or disable the PLL2 post divider 1, post divider 2 3704 * and PLL2 clock output when not in bypass mode. 3705 */ 3706 #define __HAL_RCC_PLL2CLKOUT_ENABLE() LL_RCC_PLL2P_Enable() 3707 #define __HAL_RCC_PLL2CLKOUT_DISABLE() LL_RCC_PLL2P_Disable() 3708 3709 /** 3710 * @brief Macro to configure the PLL2 in integer mode with clock source, multiplication 3711 * and division factors. 3712 * @note This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed 3713 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3714 * 3715 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3716 * This parameter can be one of the following values: 3717 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3718 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3719 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3720 * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry 3721 * @note This clock source cannot be changed on any PLL if another PLL is already enabled. 3722 * 3723 * @param __PLLM__ specifies the division factor for PLL VCO input clock 3724 * This parameter must be a number between 1 and 63. 3725 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3726 * frequency ranges from 1 to 50 MHz. 3727 * 3728 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 3729 * This parameter must be a number between 16 and 2500. 3730 * @param __PLLP1__ specifies the post division factor 1 for system clock. 3731 * This parameter must be a number between 1 and 7. 3732 * @param __PLLP2__ specifies the post division factor 2 for system clock. 3733 * This parameter must be a number between 1 and 7. 3734 * 3735 * @retval None 3736 */ 3737 3738 #define __HAL_RCC_PLL2_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ 3739 do { \ 3740 MODIFY_REG(RCC->PLL2CFGR1, (RCC_PLL2CFGR1_PLL2SEL | RCC_PLL2CFGR1_PLL2BYP | RCC_PLL2CFGR1_PLL2DIVM | RCC_PLL2CFGR1_PLL2DIVN), \ 3741 ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL2CFGR1_PLL2DIVM_Pos) | (((__PLLN__) << RCC_PLL2CFGR1_PLL2DIVN_Pos)))); \ 3742 MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_PLL2DIVNFRAC, 0U); \ 3743 MODIFY_REG(RCC->PLL2CFGR3, (RCC_PLL2CFGR3_PLL2PDIV1 | RCC_PLL2CFGR3_PLL2PDIV2), \ 3744 ((((__PLLP1__) << RCC_PLL2CFGR3_PLL2PDIV1_Pos) & RCC_PLL2CFGR3_PLL2PDIV1) | \ 3745 ((((__PLLP2__) << RCC_PLL2CFGR3_PLL2PDIV2_Pos) & RCC_PLL2CFGR3_PLL2PDIV2)))); \ 3746 } while(0) 3747 3748 3749 /** @brief Macro to configure the PLL2 clock source. 3750 * @note This macro must be used only when the PLL2 is disabled or the PLL2 output is bypassed 3751 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3752 * 3753 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3754 * This parameter can be one of the following values: 3755 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3756 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3757 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3758 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry 3759 */ 3760 #define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL2_SetSource((uin32_t)__PLLSOURCE__) 3761 3762 /** @brief Macro to get the clock source used as PLL2 clock source. 3763 * @retval The oscillator used as PLL clock source. 3764 * The returned value can be one of the following values: 3765 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3766 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3767 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3768 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. 3769 */ 3770 #define __HAL_RCC_GET_PLL2_OSCSOURCE() LL_RCC_PLL2_GetSource() 3771 3772 /** 3773 * @brief Macro to configure the PLL2 clock Fractional Part Of The Multiplication Factor 3774 * @note This configuration cannot be requested when the PLL2 has been enabled. 3775 * 3776 * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL2 VCO. 3777 * It should be a value between 0 and 2^24. 3778 * @retval None 3779 */ 3780 #define __HAL_RCC_PLL2_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL2_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) 3781 3782 /** 3783 * @brief Macro to enable the PLL2 clock Fractional mode 3784 * @note This configuration cannot be requested when the PLL2 has been enabled. 3785 * @retval None 3786 */ 3787 #define __HAL_RCC_PLL2_FRACN_ENABLE() LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum() 3788 3789 /** 3790 * @brief Macro to disable the PLL2 clock Fractional mode 3791 * @note This configuration cannot be requested when the PLL2 has been enabled. 3792 * @retval None 3793 */ 3794 #define __HAL_RCC_PLL2_FRACN_DISABLE() LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum() 3795 3796 /** @brief Macros to enable or disable PLL3. 3797 * @note After enabling PLL3, the application software should wait on 3798 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 3799 * be used as CPU and/or system bus and/or kernel clock source thru ICx. 3800 * @note PLL3 is disabled by hardware when entering Stop and Standby modes. 3801 */ 3802 #define __HAL_RCC_PLL3_ENABLE() LL_RCC_PLL3_Enable() 3803 #define __HAL_RCC_PLL3_DISABLE() LL_RCC_PLL3_Disable() 3804 3805 /** 3806 * @brief Macros to enable or disable the PLL3 post divider 1, post divider 2 3807 * and PLL3 clock output when not in bypass mode. 3808 */ 3809 #define __HAL_RCC_PLL3CLKOUT_ENABLE() LL_RCC_PLL3P_Enable() 3810 #define __HAL_RCC_PLL3CLKOUT_DISABLE() LL_RCC_PLL3P_Disable() 3811 3812 /** 3813 * @brief Macro to configure the PLL3 in integer mode with clock source, multiplication 3814 * and division factors. 3815 * @note This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed 3816 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3817 * 3818 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3819 * This parameter can be one of the following values: 3820 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3821 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3822 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3823 * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry 3824 * @note This clock source cannot be changed on any PLL if another PLL is already enabled. 3825 * 3826 * @param __PLLM__ specifies the division factor for PLL VCO input clock 3827 * This parameter must be a number between 1 and 63. 3828 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3829 * frequency ranges from 1 to 50 MHz. 3830 * 3831 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 3832 * This parameter must be a number between 16 and 2500. 3833 * @param __PLLP1__ specifies the post division factor 1 for system clock. 3834 * This parameter must be a number between 1 and 7. 3835 * @param __PLLP2__ specifies the post division factor 2 for system clock. 3836 * This parameter must be a number between 1 and 7. 3837 * 3838 * @retval None 3839 */ 3840 3841 #define __HAL_RCC_PLL3_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ 3842 do { \ 3843 MODIFY_REG(RCC->PLL3CFGR1, (RCC_PLL3CFGR1_PLL3SEL | RCC_PLL3CFGR1_PLL3BYP | RCC_PLL3CFGR1_PLL3DIVM | RCC_PLL3CFGR1_PLL3DIVN), \ 3844 ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL3CFGR1_PLL3DIVM_Pos) | (((__PLLN__) << RCC_PLL3CFGR1_PLL3DIVN_Pos)))); \ 3845 MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_PLL3DIVNFRAC, 0U); \ 3846 MODIFY_REG(RCC->PLL3CFGR3, (RCC_PLL3CFGR3_PLL3PDIV1 | RCC_PLL3CFGR3_PLL3PDIV2), \ 3847 ((((__PLLP1__) << RCC_PLL3CFGR3_PLL3PDIV1_Pos) & RCC_PLL3CFGR3_PLL3PDIV1) | \ 3848 ((((__PLLP2__) << RCC_PLL3CFGR3_PLL3PDIV2_Pos) & RCC_PLL3CFGR3_PLL3PDIV2)))); \ 3849 } while(0) 3850 3851 3852 /** @brief Macro to configure the PLL3 clock source. 3853 * @note This macro must be used only when the PLL3 is disabled or the PLL3 output is bypassed 3854 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3855 * 3856 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3857 * This parameter can be one of the following values: 3858 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3859 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3860 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3861 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry 3862 */ 3863 #define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL3_SetSource((uin32_t)__PLLSOURCE__) 3864 3865 /** @brief Macro to get the clock source used as PLL3 clock source. 3866 * @retval The oscillator used as PLL clock source. 3867 * The returned value can be one of the following values: 3868 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3869 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3870 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3871 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. 3872 */ 3873 #define __HAL_RCC_GET_PLL3_OSCSOURCE() LL_RCC_PLL3_GetSource() 3874 3875 /** 3876 * @brief Macro to configure the PLL3 clock Fractional Part Of The Multiplication Factor 3877 * @note This configuration cannot be requested when the PLL3 has been enabled. 3878 * 3879 * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO. 3880 * It should be a value between 0 and 2^24. 3881 * @retval None 3882 */ 3883 #define __HAL_RCC_PLL3_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL3_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) 3884 3885 /** 3886 * @brief Macro to enable the PLL3 clock Fractional mode 3887 * @note This configuration cannot be requested when the PLL3 has been enabled. 3888 * @retval None 3889 */ 3890 #define __HAL_RCC_PLL3_FRACN_ENABLE() LL_RCC_PLL3_EnableFractionalModulationSpreadSpectrum() 3891 3892 /** 3893 * @brief Macro to disable the PLL3 clock Fractional mode 3894 * @note This configuration cannot be requested when the PLL3 has been enabled. 3895 * @retval None 3896 */ 3897 #define __HAL_RCC_PLL3_FRACN_DISABLE() LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum() 3898 3899 /** @brief Macros to enable or disable PLL4. 3900 * @note After enabling PLL4, the application software should wait on 3901 * PLL4RDY flag to be set indicating that PLL4 clock is stable and can 3902 * be used as CPU and/or system bus and/or kernel clock source thru ICx. 3903 * @note PLL4 is disabled by hardware when entering Stop and Standby modes. 3904 */ 3905 #define __HAL_RCC_PLL4_ENABLE() LL_RCC_PLL4_Enable() 3906 #define __HAL_RCC_PLL4_DISABLE() LL_RCC_PLL4_Disable() 3907 3908 /** 3909 * @brief Macros to enable or disable the PLL4 post divider 1, post divider 2 3910 * and PLL4 clock output when not in bypass mode. 3911 */ 3912 #define __HAL_RCC_PLL4CLKOUT_ENABLE() LL_RCC_PLL4P_Enable() 3913 #define __HAL_RCC_PLL4CLKOUT_DISABLE() LL_RCC_PLL4P_Disable() 3914 3915 /** 3916 * @brief Macro to configure the PLL4 in integer mode with clock source, multiplication 3917 * and division factors. 3918 * @note This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed 3919 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3920 * 3921 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3922 * This parameter can be one of the following values: 3923 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3924 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3925 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3926 * @arg @ref RCC_PLLSOURCE_PIN I2S_CKIN clock selected as PLL clock entry 3927 * @note This clock source cannot be changed on any PLL if another PLL is already enabled. 3928 * 3929 * @param __PLLM__ specifies the division factor for PLL VCO input clock 3930 * This parameter must be a number between 1 and 63. 3931 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3932 * frequency ranges from 1 to 50 MHz. 3933 * 3934 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock 3935 * This parameter must be a number between 16 and 2500. 3936 * @param __PLLP1__ specifies the post division factor 1 for system clock. 3937 * This parameter must be a number between 1 and 7. 3938 * @param __PLLP2__ specifies the post division factor 2 for system clock. 3939 * This parameter must be a number between 1 and 7. 3940 * 3941 * @retval None 3942 */ 3943 3944 #define __HAL_RCC_PLL4_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP1__, __PLLP2__) \ 3945 do { \ 3946 MODIFY_REG(RCC->PLL4CFGR1, (RCC_PLL4CFGR1_PLL4SEL | RCC_PLL4CFGR1_PLL4BYP | RCC_PLL4CFGR1_PLL4DIVM | RCC_PLL4CFGR1_PLL4DIVN), \ 3947 ((__PLLSOURCE__) | ( (__PLLM__) << RCC_PLL4CFGR1_PLL4DIVM_Pos) | (((__PLLN__) << RCC_PLL4CFGR1_PLL4DIVN_Pos)))); \ 3948 MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_PLL4DIVNFRAC, 0U); \ 3949 MODIFY_REG(RCC->PLL4CFGR3, (RCC_PLL4CFGR3_PLL4PDIV1 | RCC_PLL4CFGR3_PLL4PDIV2), \ 3950 ((((__PLLP1__) << RCC_PLL4CFGR3_PLL4PDIV1_Pos) & RCC_PLL4CFGR3_PLL4PDIV1) | \ 3951 ((((__PLLP2__) << RCC_PLL4CFGR3_PLL4PDIV2_Pos) & RCC_PLL4CFGR3_PLL4PDIV2)))); \ 3952 } while(0) 3953 3954 3955 /** @brief Macro to configure the PLL4 clock source. 3956 * @note This macro must be used only when the PLL4 is disabled or the PLL4 output is bypassed 3957 * and driven by the PLL reference clock. This macro switches off the bypass mode. 3958 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3959 * This parameter can be one of the following values: 3960 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3961 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3962 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3963 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN clock selected as PLL clock entry 3964 */ 3965 #define __HAL_RCC_PLL4_PLLSOURCE_CONFIG(__PLLSOURCE__) LL_RCC_PLL4_SetSource((uin32_t)__PLLSOURCE__) 3966 3967 /** @brief Macro to get the clock source used as PLL4 clock source. 3968 * @retval The oscillator used as PLL clock source. 3969 * The returned value can be one of the following values: 3970 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3971 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3972 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3973 * @arg @ref RCC_PLLSOURCE_PIN External I2S_CKIN is used as PLL clock source. 3974 */ 3975 #define __HAL_RCC_GET_PLL4_OSCSOURCE() LL_RCC_PLL4_GetSource() 3976 3977 /** 3978 * @brief Macro to configure the PLL4 clock Fractional Part Of The Multiplication Factor 3979 * @note This configuration cannot be requested when the PLL4 has been enabled. 3980 * 3981 * @param __PLLDIVNFRAC__ specifies Fractional Part Of The Multiplication Factor for PLL4 VCO. 3982 * It should be a value between 0 and 2^24. 3983 * @retval None 3984 */ 3985 #define __HAL_RCC_PLL4_DIVNFRAC_CONFIG(__PLLDIVNFRAC__) LL_RCC_PLL4_SetFRACN((uint32_t)(__PLLDIVNFRAC__)) 3986 3987 /** 3988 * @brief Macro to enable the PLL4 clock Fractional mode 3989 * @note This configuration cannot be requested when the PLL4 has been enabled. 3990 * @retval None 3991 */ 3992 #define __HAL_RCC_PLL4_FRACN_ENABLE() LL_RCC_PLL4_EnableFractionalModulationSpreadSpectrum() 3993 3994 3995 /** 3996 * @brief Macro to disable the PLL4 clock Fractional mode 3997 * @note This configuration cannot be requested when the PLL4 has been enabled. 3998 * @retval None 3999 */ 4000 #define __HAL_RCC_PLL4_FRACN_DISABLE() LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum() 4001 4002 /** 4003 * @brief Macro to configure the CPU clock source. 4004 * @param __CPUCLKSOURCE__ specifies the CPU clock source. 4005 * This parameter can be one of the following values: 4006 * @arg @ref RCC_CPUCLKSOURCE_HSI HSI oscillator is used as CPU clock source. 4007 * @arg @ref RCC_CPUCLKSOURCE_MSI MSI oscillator is used as CPU clock source. 4008 * @arg @ref RCC_CPUCLKSOURCE_HSE HSE oscillator is used as CPU clock source. 4009 * @arg @ref RCC_CPUCLKSOURCE_IC1 IC1 output is used as CPU clock source. 4010 * @retval None 4011 */ 4012 #define __HAL_RCC_CPUCLK_CONFIG(__CPUCLKSOURCE__) LL_RCC_SetCpuClkSource((uint32_t)(__CPUCLKSOURCE__)) 4013 4014 /** @brief Macro to get the clock source used as CPU clock. 4015 * @retval The clock source used as CPU clock. 4016 * The returned value can be one of the following values: 4017 * @arg @ref RCC_CPUCLKSOURCE_STATUS_HSI HSI used as CPU clock. 4018 * @arg @ref RCC_CPUCLKSOURCE_STATUS_MSI MSI used as CPU clock. 4019 * @arg @ref RCC_CPUCLKSOURCE_STATUS_HSE HSE used as CPU clock. 4020 * @arg @ref RCC_CPUCLKSOURCE_STATUS_IC1 IC1 used as CPU clock. 4021 */ 4022 #define __HAL_RCC_GET_CPUCLK_SOURCE() LL_RCC_GetCpuClkSource() 4023 4024 4025 /** 4026 * @brief Macro to configure the system bus clock source. 4027 * @param __SYSCLKSOURCE__ specifies the system clock source. 4028 * This parameter can be one of the following values: 4029 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system bus clock source. 4030 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system bus clock source. 4031 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system bus clock source. 4032 * @arg @ref RCC_SYSCLKSOURCE_IC2_IC6_IC11 IC2, IC6 and IC11 outputs are used as system bus clock source. 4033 * @retval None 4034 */ 4035 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) LL_RCC_SetSysClkSource((uint32_t)(__SYSCLKSOURCE__)) 4036 4037 /** @brief Macro to get the clock source used as system bus clock. 4038 * @retval The clock source used as system clock. 4039 * The returned value can be one of the following values: 4040 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system bus clock. 4041 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system bus clock. 4042 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system bus clock. 4043 * @arg @ref RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11 IC2, IC6 and IC11 outputs used as system bus clock. 4044 */ 4045 #define __HAL_RCC_GET_SYSCLK_SOURCE() LL_RCC_GetSysClkSource() 4046 4047 /** 4048 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4049 * @note As the LSE is in the Backup domain and write access is denied to 4050 * this domain after reset, you have to enable write access using 4051 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4052 * (to be done once after reset). 4053 * @note This parameter cannot be updated while LSE is ON. 4054 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 4055 * This parameter can be one of the following values: 4056 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4057 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4058 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4059 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4060 * @retval None 4061 */ 4062 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) LL_RCC_LSE_SetDriveCapability((uint32_t)(__LSEDRIVE__)) 4063 4064 /** 4065 * @brief Macro to configure the wake up from stop clock. 4066 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop 4067 * This parameter can be one of the following values: 4068 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4069 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 4070 * @retval None 4071 */ 4072 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) LL_RCC_SetSysWakeUpClkSource((uint32_t)(__STOPWUCLK__)) 4073 4074 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 4075 * @{ 4076 */ 4077 4078 /** 4079 * @brief Macros to enable or disable the MCO1 clock output 4080 * @retval None 4081 */ 4082 #define __HAL_RCC_MCO1_ENABLE() LL_RCC_EnableMCO(LL_RCC_MCO1) 4083 4084 #define __HAL_RCC_MCO1_DISABLE() LL_RCC_DisableMCO(LL_RCC_MCO1) 4085 4086 /** 4087 * @brief Macros to enable or disable the MCO2 clock output 4088 * @retval None 4089 */ 4090 #define __HAL_RCC_MCO2_ENABLE() LL_RCC_EnableMCO(LL_RCC_MCO2) 4091 4092 #define __HAL_RCC_MCO2_DISABLE() LL_RCC_DisableMCO(LL_RCC_MCO2) 4093 4094 4095 /** @brief Macro to configure the MCO1 clock. 4096 * @note MCO1 clock output shall be enabled with __HAL_RCC_MCO1_ENABLE() 4097 * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch). 4098 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4099 * This parameter can be one of the following values: 4100 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source 4101 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source 4102 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO1 source 4103 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO1 source 4104 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source 4105 * @arg @ref RCC_MCO1SOURCE_IC5 IC5 clock selected as MCO1 source 4106 * @arg @ref RCC_MCO1SOURCE_IC10 IC10 clock selected as MCO1 source 4107 * @arg @ref RCC_MCO1SOURCE_SYSA SYSA CPU clock selected as MCO1 source 4108 * @param __MCODIV__ specifies the MCO clock prescaler. 4109 * This parameter can be one of the following values: 4110 * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCO1 clock 4111 */ 4112 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__) 4113 4114 /** @brief Macro to configure the MCO2 clock. 4115 * @note MCO2 clock output shall be enabled with __HAL_RCC_MCO2_ENABLE() 4116 * @note The MCO switch to the new clock source only occurs when the previous clock source is active (dynamic switch). 4117 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4118 * This parameter can be one of the following values: 4119 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source 4120 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source 4121 * @arg @ref RCC_MCO2SOURCE_MSI MSI clock selected as MCO2 source 4122 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source 4123 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source 4124 * @arg @ref RCC_MCO2SOURCE_IC15 IC15 clock selected as MCO2 source 4125 * @arg @ref RCC_MCO2SOURCE_IC20 IC20 clock selected as MCO2 source 4126 * @arg @ref RCC_MCO2SOURCE_SYSB SYSB bus clock selected as MCO2 source 4127 * @param __MCODIV__ specifies the MCO clock prescaler. 4128 * This parameter can be one of the following values: 4129 * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCO2 clock 4130 */ 4131 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO(__MCOCLKSOURCE__, __MCODIV__) 4132 4133 /** 4134 * @} 4135 */ 4136 4137 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4138 * @brief macros to manage the specified RCC Flags and interrupts. 4139 * @{ 4140 */ 4141 /** @brief Enable RCC interrupt. 4142 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 4143 * This parameter can be any combination of the following values: 4144 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4145 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4146 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4147 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4148 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4149 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4150 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4151 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4152 * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt 4153 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4154 * @arg @ref RCC_IT_HSECSS HSE clock security system interrupt 4155 * @arg @ref RCC_IT_WKUP CPU wakeup interrupt 4156 */ 4157 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4158 4159 /** @brief Disable RCC interrupt. 4160 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 4161 * This parameter can be any combination of the following values: 4162 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4163 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4164 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4165 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4166 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4167 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4168 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4169 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4170 * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt 4171 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4172 * @arg @ref RCC_IT_HSECSS HSE clock security system interrupt 4173 * @arg @ref RCC_IT_WKUP CPU wakeup interrupt 4174 */ 4175 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4176 4177 /** @brief Clear the RCC's interrupt pending bits 4178 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4179 * This parameter can be any combination of the following values: 4180 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4181 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4182 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4183 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4184 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4185 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4186 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4187 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4188 * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt 4189 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4190 * @arg @ref RCC_IT_HSECSS HSE clock security interrupt 4191 * @arg @ref RCC_IT_WKUP CPU wakeup interrupt 4192 */ 4193 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4194 4195 /** @brief Check whether the RCC interrupt has occurred or not. 4196 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 4197 * This parameter can be one of the following values: 4198 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4199 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4200 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4201 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4202 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4203 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4204 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4205 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4206 * @arg @ref RCC_IT_PLL4RDY PLL4 ready interrupt 4207 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4208 * @arg @ref RCC_IT_HSECSS HSE clock security interrupt 4209 * @arg @ref RCC_IT_WKUP CPU wakeup interrupt 4210 * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). 4211 */ 4212 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 4213 4214 /** @brief Set RMVF bit to clear the reset flags. 4215 * The reset flags are: RCC_FLAG_LCKRST, RCC_FLAG_BORRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, 4216 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4217 */ 4218 #define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags() 4219 4220 /** @brief Check whether the selected RCC flag is set or not. 4221 * @param __FLAG__ specifies the flag to check. 4222 * This parameter can be one of the following values: 4223 * @arg @ref RCC_FLAG_LCKRST CPU lockup reset flag 4224 * @arg @ref RCC_FLAG_BORRST BOR reset flag 4225 * @arg @ref RCC_FLAG_PINRST Pin reset flag 4226 * @arg @ref RCC_FLAG_PORRST Power-on reset flag 4227 * @arg @ref RCC_FLAG_SFTRST Software reset flag 4228 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset flag 4229 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset flag 4230 * @arg @ref RCC_FLAG_LPWRRST Low Power reset flag 4231 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection flag 4232 * @arg @ref RCC_FLAG_HSECSSD Clock security system failure on HSE oscillator detection flag 4233 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready flag 4234 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready flag 4235 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready flag 4236 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready flag 4237 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready flag 4238 * @arg @ref RCC_FLAG_PLL1RDY PLL1 ready flag 4239 * @arg @ref RCC_FLAG_PLL2RDY PLL2 ready flag 4240 * @arg @ref RCC_FLAG_PLL3RDY PLL3 ready flag 4241 * @arg @ref RCC_FLAG_PLL4RDY PLL4 ready flag 4242 * @retval The new state of __FLAG__ (TRUE or FALSE). 4243 */ 4244 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX) ? RCC->RSR : \ 4245 ((((__FLAG__) >> 5U) == RCC_LSECFGR_REG_INDEX) ? RCC->LSECFGR : \ 4246 ((((__FLAG__) >> 5U) == RCC_HSECFGR_REG_INDEX) ? RCC->HSECFGR : RCC->SR)))) \ 4247 & (1UL << ((__FLAG__) & RCC_FLAG_POS_MASK))) != 0U) ? 1U : 0U) 4248 4249 /** 4250 * @} 4251 */ 4252 4253 /** @defgroup RCC_Attributes_Management Attribute Management 4254 * @brief macros to manage the RCC Attributes. 4255 * @{ 4256 */ 4257 4258 /** @brief Check whether an item attribute is secured 4259 * @param __ATTRIBUTES__ specifies the item attributes 4260 * This parameter is a combination of @ref RCC_attributes 4261 * @retval 1 if the item attribute is secured, 0 otherwise. 4262 */ 4263 #define HAL_RCC_ATTRIBUTES_IS_SEC(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_SEC) == RCC_ATTR_SEC) ? 1U : 0U) 4264 4265 /** @brief Check whether an item attribute is privileged 4266 * @param __ATTRIBUTES__ specifies the item attributes 4267 * This parameter is a combination of @ref RCC_attributes 4268 * @retval 1 if the item attribute is privileged, 0 otherwise. 4269 */ 4270 #define HAL_RCC_ATTRIBUTES_IS_PRIV(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) ? 1U : 0U) 4271 4272 /** @brief Check whether an item attribute is public 4273 * @param __ATTRIBUTES__ specifies the item attributes 4274 * This parameter is a combination of @ref RCC_attributes 4275 * @retval 1 if the item attribute is public, 0 otherwise. 4276 */ 4277 #define HAL_RCC_ATTRIBUTES_IS_PUB(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_PUB) == RCC_ATTR_PUB) ? 1U : 0U) 4278 4279 /** @brief Check whether an item attribute is locked 4280 * @param __ATTRIBUTES__ specifies the item attributes 4281 * This parameter is a combination of @ref RCC_attributes 4282 * @retval 1 if the item attribute is locked, 0 otherwise. 4283 */ 4284 #define HAL_RCC_ATTRIBUTES_IS_LOCK(__ATTRIBUTES__) (((__ATTRIBUTES__ & RCC_ATTR_LOCK) == RCC_ATTR_LOCK) ? 1U : 0U) 4285 4286 /** 4287 * @} 4288 */ 4289 4290 /** 4291 * @} 4292 */ 4293 4294 /* Include RCC HAL Extension module */ 4295 #include "stm32n6xx_hal_rcc_ex.h" 4296 4297 /* Exported functions --------------------------------------------------------*/ 4298 /** @addtogroup RCC_Exported_Functions 4299 * @{ 4300 */ 4301 4302 /** @addtogroup RCC_Exported_Functions_Group1 4303 * @{ 4304 */ 4305 /* Initialization and de-initialization functions ******************************/ 4306 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4307 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); 4308 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pRCC_ClkInitStruct); 4309 4310 /** 4311 * @} 4312 */ 4313 4314 /** @addtogroup RCC_Exported_Functions_Group2 4315 * @{ 4316 */ 4317 /* Peripheral Control functions ************************************************/ 4318 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4319 void HAL_RCC_EnableCSS(void); 4320 uint32_t HAL_RCC_GetCpuClockFreq(void); 4321 uint32_t HAL_RCC_GetSysClockFreq(void); 4322 uint32_t HAL_RCC_GetHCLKFreq(void); 4323 uint32_t HAL_RCC_GetPCLK1Freq(void); 4324 uint32_t HAL_RCC_GetPCLK2Freq(void); 4325 uint32_t HAL_RCC_GetPCLK4Freq(void); 4326 uint32_t HAL_RCC_GetPCLK5Freq(void); 4327 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 4328 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct); 4329 /* CSS NMI IRQ handler */ 4330 void HAL_RCC_NMI_IRQHandler(void); 4331 /* User callback in non blocking mode (IT mode) */ 4332 void HAL_RCC_CSSCallback(void); 4333 4334 /** 4335 * @} 4336 */ 4337 4338 /** @addtogroup RCC_Exported_Functions_Group3 4339 * @{ 4340 */ 4341 /* Attributes management functions ********************************************/ 4342 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 4343 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 4344 4345 /** 4346 * @} 4347 */ 4348 4349 /** 4350 * @} 4351 */ 4352 4353 /* Private types -------------------------------------------------------------*/ 4354 /* Private variables ---------------------------------------------------------*/ 4355 /* Private constants ---------------------------------------------------------*/ 4356 /** @defgroup RCC_Private_Constants RCC Private Constants 4357 * @{ 4358 */ 4359 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 4360 #define RCC_PLL_TIMEOUT_VALUE 1U /* 1 ms */ 4361 4362 /* Defines used for Flags */ 4363 #define RCC_SR_REG_INDEX 1U 4364 #define RCC_LSECFGR_REG_INDEX 2U 4365 #define RCC_HSECFGR_REG_INDEX 3U 4366 #define RCC_RSR_REG_INDEX 4U 4367 #define RCC_FLAG_POS_MASK 0x0000001FU 4368 4369 /* Defines RCC privilege/secure/public/lock attribute masks */ 4370 #define RCC_ATTR_PRIV_MASK (0x00000002U) /* RCC privilege mask */ 4371 #define RCC_ATTR_SEC_MASK (0x00000008U) /* RCC secure mask */ 4372 #define RCC_ATTR_PUB_MASK (0x00000020U) /* RCC public mask */ 4373 #define RCC_ATTR_LOCK_MASK (0x00000080U) /* RCC lock mask */ 4374 4375 /* Defines RCC item groups masks */ 4376 /* Item ID are masked with item group to get an unique ID 4377 31 24 16 8 0 4378 -------------------------------------------------------- 4379 | Item Group | Item | 4380 --------------------------------------------------------*/ 4381 #define RCC_ITEM_GROUP_POS 24UL 4382 #define RCC_ITEM_GROUP_MASK 0xFF000000UL 4383 #define RCC_ITEM_MASK 0x00FFFFFFUL 4384 #define RCC_ITEM_GROUP_OSC 0x01000000UL 4385 #define RCC_ITEM_GROUP_PLL 0x02000000UL 4386 #define RCC_ITEM_GROUP_IC 0x04000000UL 4387 #define RCC_ITEM_GROUP_SYSCFG 0x08000000UL 4388 #define RCC_ITEM_GROUP_BUS 0x10000000UL 4389 #define RCC_ITEM_GROUP_MEM 0x20000000UL 4390 4391 #define RCC_ITEM_GROUP_OSC_MASK 0x0000001FUL 4392 #define RCC_ITEM_GROUP_PLL_MASK 0x0000000FUL 4393 #define RCC_ITEM_GROUP_IC_MASK 0x000FFFFFUL 4394 #define RCC_ITEM_GROUP_SYSCFG_MASK 0x0000003FUL 4395 #define RCC_ITEM_GROUP_BUS_MASK 0x00003FFFUL 4396 #define RCC_ITEM_GROUP_MEM_MASK 0x00000FFFUL 4397 4398 /** 4399 * @} 4400 */ 4401 4402 /* Private macros ------------------------------------------------------------*/ 4403 /** @addtogroup RCC_Private_Macros 4404 * @{ 4405 */ 4406 4407 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 4408 * @{ 4409 */ 4410 4411 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4412 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4413 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4414 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 4415 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4416 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 4417 4418 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4419 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) 4420 4421 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4422 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) 4423 4424 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4425 4426 #define IS_RCC_HSI_DIV(__HSI__) (((__HSI__) == RCC_HSI_DIV1) || ((__HSI__) == RCC_HSI_DIV2) || \ 4427 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_DIV8)) 4428 4429 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4430 4431 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 4432 4433 #define IS_RCC_MSI_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == RCC_MSI_FREQ_4MHZ) ||\ 4434 ((__FREQUENCY__) == RCC_MSI_FREQ_16MHZ)) 4435 4436 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || \ 4437 ((__PLL__) == RCC_PLL_OFF) || \ 4438 ((__PLL__) == RCC_PLL_ON) || \ 4439 ((__PLL__) == RCC_PLL_BYPASS)) 4440 4441 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 4442 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 4443 ((__SOURCE__) == RCC_PLLSOURCE_HSE) || \ 4444 ((__SOURCE__) == RCC_PLLSOURCE_PIN)) 4445 4446 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) 4447 4448 #define IS_RCC_PLLN_VALUE(__VALUE__) ((10U <= (__VALUE__)) && ((__VALUE__) <= 2500U)) 4449 4450 #define IS_RCC_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 7U)) 4451 4452 #define IS_RCC_PLLFRACN_VALUE(__VALUE__) ((__VALUE__) <= (RCC_PLL1CFGR2_PLL1DIVNFRAC >> RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos)) 4453 4454 #define IS_RCC_CLOCKTYPE(__CLK__) ((__CLK__) <= 0x7FU) 4455 4456 #define IS_RCC_CPUCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_CPUCLKSOURCE_HSI) || \ 4457 ((__SOURCE__) == RCC_CPUCLKSOURCE_MSI) || \ 4458 ((__SOURCE__) == RCC_CPUCLKSOURCE_HSE) || \ 4459 ((__SOURCE__) == RCC_CPUCLKSOURCE_IC1)) 4460 4461 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4462 ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 4463 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4464 ((__SOURCE__) == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) 4465 4466 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_HCLK_DIV1) || ((__HCLK__) == RCC_HCLK_DIV2) || \ 4467 ((__HCLK__) == RCC_HCLK_DIV4) || ((__HCLK__) == RCC_HCLK_DIV8) || \ 4468 ((__HCLK__) == RCC_HCLK_DIV16) || ((__HCLK__) == RCC_HCLK_DIV32) || \ 4469 ((__HCLK__) == RCC_HCLK_DIV64) || ((__HCLK__) == RCC_HCLK_DIV128)) 4470 4471 #define IS_RCC_PCLK1(__PCLK1__) (((__PCLK1__) == RCC_APB1_DIV1) || ((__PCLK1__) == RCC_APB1_DIV2) || \ 4472 ((__PCLK1__) == RCC_APB1_DIV4) || ((__PCLK1__) == RCC_APB1_DIV8) || \ 4473 ((__PCLK1__) == RCC_APB1_DIV16) || ((__PCLK1__) == RCC_APB1_DIV32) || \ 4474 ((__PCLK1__) == RCC_APB1_DIV64) || ((__PCLK1__) == RCC_APB1_DIV128)) 4475 4476 #define IS_RCC_PCLK2(__PCLK2__) (((__PCLK2__) == RCC_APB2_DIV1) || ((__PCLK2__) == RCC_APB2_DIV2) || \ 4477 ((__PCLK2__) == RCC_APB2_DIV4) || ((__PCLK2__) == RCC_APB2_DIV8) || \ 4478 ((__PCLK2__) == RCC_APB2_DIV16) || ((__PCLK2__) == RCC_APB2_DIV32) || \ 4479 ((__PCLK2__) == RCC_APB2_DIV64) || ((__PCLK2__) == RCC_APB2_DIV128)) 4480 4481 #define IS_RCC_PCLK4(__PCLK4__) (((__PCLK4__) == RCC_APB4_DIV1) || ((__PCLK4__) == RCC_APB4_DIV2) || \ 4482 ((__PCLK4__) == RCC_APB4_DIV4) || ((__PCLK4__) == RCC_APB4_DIV8) || \ 4483 ((__PCLK4__) == RCC_APB4_DIV16) || ((__PCLK4__) == RCC_APB4_DIV32) || \ 4484 ((__PCLK4__) == RCC_APB4_DIV64) || ((__PCLK4__) == RCC_APB4_DIV128)) 4485 4486 #define IS_RCC_PCLK5(__PCLK5__) (((__PCLK5__) == RCC_APB5_DIV1) || ((__PCLK5__) == RCC_APB5_DIV2) || \ 4487 ((__PCLK5__) == RCC_APB5_DIV4) || ((__PCLK5__) == RCC_APB5_DIV8) || \ 4488 ((__PCLK5__) == RCC_APB5_DIV16) || ((__PCLK5__) == RCC_APB5_DIV32) || \ 4489 ((__PCLK5__) == RCC_APB5_DIV64) || ((__PCLK5__) == RCC_APB5_DIV128)) 4490 4491 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 4492 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV1) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ 4493 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ 4494 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ 4495 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ 4496 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ 4497 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ 4498 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ 4499 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ 4500 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ 4501 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ 4502 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ 4503 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ 4504 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ 4505 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ 4506 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ 4507 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32) || \ 4508 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV33) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV34) || \ 4509 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV35) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV36) || \ 4510 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV37) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV38) || \ 4511 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV39) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV40) || \ 4512 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV41) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV42) || \ 4513 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV43) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV44) || \ 4514 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV45) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV46) || \ 4515 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV47) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV48) || \ 4516 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV49) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV50) || \ 4517 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV51) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV52) || \ 4518 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV53) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV54) || \ 4519 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV55) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV56) || \ 4520 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV57) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV58) || \ 4521 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV59) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV60) || \ 4522 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV61) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV62) || \ 4523 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV63) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV64)) 4524 4525 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2)) 4526 4527 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 4528 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 4529 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_IC5) || \ 4530 ((__SOURCE__) == RCC_MCO1SOURCE_IC10) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSA)) 4531 4532 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_LSI) || ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ 4533 ((__SOURCE__) == RCC_MCO2SOURCE_MSI) || ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 4534 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || ((__SOURCE__) == RCC_MCO2SOURCE_IC15) || \ 4535 ((__SOURCE__) == RCC_MCO2SOURCE_IC20) || ((__SOURCE__) == RCC_MCO2SOURCE_SYSB)) 4536 4537 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 4538 ((__DIV__) == RCC_MCODIV_3) || ((__DIV__) == RCC_MCODIV_4) || \ 4539 ((__DIV__) == RCC_MCODIV_5) || ((__DIV__) == RCC_MCODIV_6) || \ 4540 ((__DIV__) == RCC_MCODIV_7) || ((__DIV__) == RCC_MCODIV_8) || \ 4541 ((__DIV__) == RCC_MCODIV_9) || ((__DIV__) == RCC_MCODIV_10) || \ 4542 ((__DIV__) == RCC_MCODIV_11) || ((__DIV__) == RCC_MCODIV_12) || \ 4543 ((__DIV__) == RCC_MCODIV_13) || ((__DIV__) == RCC_MCODIV_14) || \ 4544 ((__DIV__) == RCC_MCODIV_15) || ((__DIV__) == RCC_MCODIV_16)) 4545 4546 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) 4547 4548 #define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 4549 4550 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 4551 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4552 4553 #define IS_RCC_ICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ICCLKSOURCE_PLL1) || \ 4554 ((__SOURCE__) == RCC_ICCLKSOURCE_PLL2) || \ 4555 ((__SOURCE__) == RCC_ICCLKSOURCE_PLL3) || \ 4556 ((__SOURCE__) == RCC_ICCLKSOURCE_PLL4)) 4557 4558 #define IS_RCC_ICCLKDIVIDER(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 256U)) 4559 4560 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ITEM_ALL) != 0U) && (((ITEM) & ~RCC_ITEM_ALL) == 0U)) 4561 4562 #define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_ITEM_LSI) || \ 4563 ((ITEM) == RCC_ITEM_LSE) || \ 4564 ((ITEM) == RCC_ITEM_MSI) || \ 4565 ((ITEM) == RCC_ITEM_HSI) || \ 4566 ((ITEM) == RCC_ITEM_HSE) || \ 4567 ((ITEM) == RCC_ITEM_PLL1) || \ 4568 ((ITEM) == RCC_ITEM_PLL2) || \ 4569 ((ITEM) == RCC_ITEM_PLL3) || \ 4570 ((ITEM) == RCC_ITEM_PLL4) || \ 4571 ((ITEM) == RCC_ITEM_IC1) || \ 4572 ((ITEM) == RCC_ITEM_IC2) || \ 4573 ((ITEM) == RCC_ITEM_IC3) || \ 4574 ((ITEM) == RCC_ITEM_IC4) || \ 4575 ((ITEM) == RCC_ITEM_IC5) || \ 4576 ((ITEM) == RCC_ITEM_IC6) || \ 4577 ((ITEM) == RCC_ITEM_IC7) || \ 4578 ((ITEM) == RCC_ITEM_IC8) || \ 4579 ((ITEM) == RCC_ITEM_IC9) || \ 4580 ((ITEM) == RCC_ITEM_IC10) || \ 4581 ((ITEM) == RCC_ITEM_IC11) || \ 4582 ((ITEM) == RCC_ITEM_IC12) || \ 4583 ((ITEM) == RCC_ITEM_IC13) || \ 4584 ((ITEM) == RCC_ITEM_IC14) || \ 4585 ((ITEM) == RCC_ITEM_IC15) || \ 4586 ((ITEM) == RCC_ITEM_IC16) || \ 4587 ((ITEM) == RCC_ITEM_IC17) || \ 4588 ((ITEM) == RCC_ITEM_IC18) || \ 4589 ((ITEM) == RCC_ITEM_IC19) || \ 4590 ((ITEM) == RCC_ITEM_IC20) || \ 4591 ((ITEM) == RCC_ITEM_MOD) || \ 4592 ((ITEM) == RCC_ITEM_SYS) || \ 4593 ((ITEM) == RCC_ITEM_BUS) || \ 4594 ((ITEM) == RCC_ITEM_PER) || \ 4595 ((ITEM) == RCC_ITEM_INT) || \ 4596 ((ITEM) == RCC_ITEM_RST) || \ 4597 ((ITEM) == RCC_ITEM_ACLKN) || \ 4598 ((ITEM) == RCC_ITEM_ACLKNC) || \ 4599 ((ITEM) == RCC_ITEM_AHBM) || \ 4600 ((ITEM) == RCC_ITEM_AHB1) || \ 4601 ((ITEM) == RCC_ITEM_AHB2) || \ 4602 ((ITEM) == RCC_ITEM_AHB3) || \ 4603 ((ITEM) == RCC_ITEM_AHB4) || \ 4604 ((ITEM) == RCC_ITEM_AHB5) || \ 4605 ((ITEM) == RCC_ITEM_APB1) || \ 4606 ((ITEM) == RCC_ITEM_APB2) || \ 4607 ((ITEM) == RCC_ITEM_APB3) || \ 4608 ((ITEM) == RCC_ITEM_APB4) || \ 4609 ((ITEM) == RCC_ITEM_APB5) || \ 4610 ((ITEM) == RCC_ITEM_NOC) || \ 4611 ((ITEM) == RCC_ITEM_AXISRAM3) || \ 4612 ((ITEM) == RCC_ITEM_AXISRAM4) || \ 4613 ((ITEM) == RCC_ITEM_AXISRAM5) || \ 4614 ((ITEM) == RCC_ITEM_AXISRAM6) || \ 4615 ((ITEM) == RCC_ITEM_AHBSRAM1) || \ 4616 ((ITEM) == RCC_ITEM_AHBSRAM2) || \ 4617 ((ITEM) == RCC_ITEM_BKPSRAM) || \ 4618 ((ITEM) == RCC_ITEM_AXISRAM1) || \ 4619 ((ITEM) == RCC_ITEM_AXISRAM2) || \ 4620 ((ITEM) == RCC_ITEM_FLEXRAM) || \ 4621 ((ITEM) == RCC_ITEM_CACHEAXIRAM) || \ 4622 ((ITEM) == RCC_ITEM_VENCRAM)) 4623 4624 4625 #if defined (CPU_IN_SECURE_STATE) 4626 #define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_SEC) == RCC_ATTR_SEC) || \ 4627 (((ATTRIBUTE) & RCC_ATTR_NSEC) == RCC_ATTR_NSEC) || \ 4628 (((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) || \ 4629 (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV) || \ 4630 (((ATTRIBUTE) & RCC_ATTR_PUB) == RCC_ATTR_PUB) || \ 4631 (((ATTRIBUTE) & RCC_ATTR_NPUB) == RCC_ATTR_NPUB) || \ 4632 (((ATTRIBUTE) & RCC_ATTR_LOCK) == RCC_ATTR_LOCK)) && \ 4633 (((ATTRIBUTE) & ~(RCC_ATTR_SEC|RCC_ATTR_NSEC|RCC_ATTR_PRIV|RCC_ATTR_NPRIV|\ 4634 RCC_ATTR_PUB|RCC_ATTR_NPUB|RCC_ATTR_LOCK)) == 0U)) 4635 #else 4636 #define IS_RCC_ATTRIBUTES(ATTRIBUTE) (((((ATTRIBUTE) & RCC_ATTR_PRIV) == RCC_ATTR_PRIV) || \ 4637 (((ATTRIBUTE) & RCC_ATTR_NPRIV) == RCC_ATTR_NPRIV)) && \ 4638 (((ATTRIBUTE) & ~(RCC_ATTR_PRIV|RCC_ATTR_NPRIV)) == 0U)) 4639 4640 #endif /* CPU_IN_SECURE_STATE */ 4641 4642 4643 /** 4644 * @} 4645 */ 4646 4647 /** 4648 * @} 4649 */ 4650 4651 /** 4652 * @} 4653 */ 4654 4655 /** 4656 * @} 4657 */ 4658 #ifdef __cplusplus 4659 } 4660 #endif 4661 4662 #endif /* STM32N6xx_HAL_RCC_H */ 4663
