1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 * 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7RSxx_HAL_RCC_H 22 #define STM32H7RSxx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7rsxx_hal_def.h" 30 #include "stm32h7rsxx_ll_rcc.h" 31 32 /** @addtogroup STM32H7RSxx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup RCC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup RCC_Exported_Types RCC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief RCC PLL configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PLLState; /*!< The new state of the PLL. 52 This parameter can be a value of @ref RCC_PLL_Config */ 53 54 uint32_t PLLSource; /*!< PLL entry clock source. 55 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 56 57 uint32_t PLLM; /*!< Division factor for PLL VCO input clock. 58 This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ 59 60 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. 61 This parameter must be a number between Min_Data = 8 and Max_Data = 420 */ 62 63 uint32_t PLLP; /*!< Division factor for system clock. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 65 Odd division factors (except for 1) are not allowed */ 66 67 uint32_t PLLQ; /*!< Division factor for peripheral clocks. 68 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 69 70 uint32_t PLLR; /*!< Division factor for peripheral clocks. 71 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 72 73 uint32_t PLLS; /*!< Division factor for peripheral clocks. 74 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 75 76 uint32_t PLLT; /*!< Division factor for peripheral clocks. 77 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 78 79 uint32_t PLLFractional; /*!< Fractional Part of the Multiplication Factor for PLL VCO. 80 This parameter must be a number between 0 and 8191 */ 81 82 } RCC_PLLInitTypeDef; 83 84 /** 85 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 86 */ 87 typedef struct 88 { 89 uint32_t OscillatorType; /*!< The oscillators to be configured. 90 This parameter can be a value of @ref RCC_Oscillator_Type */ 91 92 uint32_t HSEState; /*!< The new state of the HSE. 93 This parameter can be a value of @ref RCC_HSE_Config */ 94 95 uint32_t LSEState; /*!< The new state of the LSE. 96 This parameter can be a value of @ref RCC_LSE_Config */ 97 98 uint32_t HSIState; /*!< The new state of the HSI. 99 This parameter can be a value of @ref RCC_HSI_Config */ 100 101 uint32_t HSIDiv; /*!< The division factor of the HSI. 102 This parameter can be a value of @ref RCC_HSI_Divider */ 103 104 uint32_t HSICalibrationValue; /*!< The calibration trimming value. 105 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 106 107 uint32_t LSIState; /*!< The new state of the LSI. 108 This parameter can be a value of @ref RCC_LSI_Config */ 109 110 uint32_t HSI48State; /*!< The new state of the HSI48. 111 This parameter can be a value of @ref RCC_HSI48_Config */ 112 113 uint32_t CSIState; /*!< The new state of the CSI. 114 This parameter can be a value of @ref RCC_CSI_Config */ 115 116 RCC_PLLInitTypeDef PLL1; /*!< Main PLL1 structure parameters */ 117 118 RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ 119 120 RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ 121 122 } RCC_OscInitTypeDef; 123 124 /** 125 * @brief RCC System, AHB and APB busses clock configuration structure definition 126 */ 127 typedef struct 128 { 129 uint32_t ClockType; /*!< The clock to be configured. 130 This parameter can be a value of @ref RCC_System_Clock_Type */ 131 132 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 133 This parameter can be a value of @ref RCC_System_Clock_Source */ 134 135 uint32_t SYSCLKDivider; /*!< The system clock divider for CPU clock and all bus matrix clocks. 136 This parameter can be a value of @ref RCC_System_Clock_Divider */ 137 138 uint32_t AHBCLKDivider; /*!< The AHB/AXI clock divider for HCLK. 139 This clock is derived from the system clock divided by the system clock divider. 140 This parameter can be a value of @ref RCC_HCLK_Clock_Source */ 141 142 uint32_t APB1CLKDivider; /*!< The APB1 clock divider for PCLK1. 143 This clock is derived from the AHB clock (HCLK). 144 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 145 146 uint32_t APB2CLKDivider; /*!< The APB2 clock divider for PCLK2. 147 This clock is derived from the AHB clock (HCLK). 148 This parameter can be a value of @ref RCC_APB2_Clock_Source */ 149 150 uint32_t APB4CLKDivider; /*!< The APB4 clock divider for PCLK4. 151 This clock is derived from the AHB clock (HCLK). 152 This parameter can be a value of @ref RCC_APB4_Clock_Source */ 153 154 uint32_t APB5CLKDivider; /*!< The APB5 clock divider for PCLK5. 155 This clock is derived from the AHB clock (HCLK). 156 This parameter can be a value of @ref RCC_APB5_Clock_Source */ 157 158 } RCC_ClkInitTypeDef; 159 160 /** 161 * @} 162 */ 163 164 /* Exported constants --------------------------------------------------------*/ 165 166 /** @defgroup RCC_Exported_Constants RCC Exported Constants 167 * @{ 168 */ 169 170 /** @defgroup RCC_Oscillator_Type Oscillator Type 171 * @{ 172 */ 173 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 174 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE selected */ 175 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI selected */ 176 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE selected */ 177 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI selected */ 178 #define RCC_OSCILLATORTYPE_CSI 0x00000010U /*!< CSI selected */ 179 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 selected */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup RCC_HSE_Config HSE Config 185 * @{ 186 */ 187 #define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ 188 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 189 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass analog clock activation */ 190 #define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< HSE bypass digital clock activation */ 191 /** 192 * @} 193 */ 194 195 /** @defgroup RCC_LSE_Config LSE Config 196 * @{ 197 */ 198 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 199 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 200 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< LSE bypass analog clock activation */ 201 #define RCC_LSE_BYPASS_DIGITAL (RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< LSE bypass digital clock activation */ 202 /** 203 * @} 204 */ 205 206 /** @defgroup RCC_HSI_Config HSI Config 207 * @{ 208 */ 209 #define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ 210 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation with divider 1 = 64MHz */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup RCC_HSI_Calibration_Default HSI Calibration default 216 * @{ 217 */ 218 #define RCC_HSICALIBRATION_DEFAULT 0x40U /*!< Default HSI calibration trimming value */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup RCC_HSI_Divider HSI Divider 224 * @{ 225 */ 226 #define RCC_HSI_DIV1 0U /*!< HSI clock activation with divider 1 = 64MHz */ 227 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock activation with divider 2 = 32MHz */ 228 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock activation with divider 4 = 16MHz */ 229 #define RCC_HSI_DIV8 RCC_CR_HSIDIV /*!< HSI clock activation with divider 8 = 8MHz */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup RCC_HSI48_Config HSI48 Config 235 * @{ 236 */ 237 #define RCC_HSI48_OFF 0U /*!< HSI48 clock deactivation */ 238 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup RCC_LSI_Config LSI Config 244 * @{ 245 */ 246 #define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ 247 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 248 /** 249 * @} 250 */ 251 252 /** @defgroup RCC_CSI_Config CSI Config 253 * @{ 254 */ 255 #define RCC_CSI_OFF 0U /*!< CSI clock deactivation */ 256 #define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup RCC_CSI_Calibration_Default CSI Calibration default 262 * @{ 263 */ 264 #define RCC_CSICALIBRATION_DEFAULT 0x20U /*!< Default CSI calibration trimming value */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_PLL_Config PLL Config 270 * @{ 271 */ 272 #define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ 273 #define RCC_PLL_OFF 1U /*!< PLL deactivation */ 274 #define RCC_PLL_ON 2U /*!< PLL activation */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 280 * @{ 281 */ 282 #define RCC_PLLSOURCE_HSI 0U /*!< HSI clock selected as PLL entry clock source */ 283 #define RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_0 /*!< CSI clock selected as PLL entry clock source */ 284 #define RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_1 /*!< HSE clock selected as PLL entry clock source */ 285 #define RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC /*!< No clock selected as PLL entry clock source */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 291 * @{ 292 */ 293 #define RCC_PLL_PCLK RCC_PLLCFGR_PLL1PEN /*!< PLL DIVP divider output enable */ 294 #define RCC_PLL_QCLK RCC_PLLCFGR_PLL1QEN /*!< PLL DIVQ divider output enable */ 295 #define RCC_PLL_RCLK RCC_PLLCFGR_PLL1REN /*!< PLL DIVR divider output enable */ 296 #define RCC_PLL_SCLK RCC_PLLCFGR_PLL1SEN /*!< PLL DIVS divider output enable */ 297 #define RCC_PLL_TCLK 0x00000200U /*!< PLL DIVT divider output enable, hardcoded because no definition in CMSIS */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup RCC_PLL_VCI_Range PLL VCI Range 303 * @{ 304 */ 305 #define RCC_PLL_VCOINPUT_RANGE0 0U /*!< Clock range frequency for PLL between 1 and 2 MHz (reset) */ 306 #define RCC_PLL_VCOINPUT_RANGE1 RCC_PLLCFGR_PLL1RGE_0 /*!< Clock range frequency for PLL between 2 and 4 MHz */ 307 #define RCC_PLL_VCOINPUT_RANGE2 RCC_PLLCFGR_PLL1RGE_1 /*!< Clock range frequency for PLL between 4 and 8 MHz */ 308 #define RCC_PLL_VCOINPUT_RANGE3 RCC_PLLCFGR_PLL1RGE /*!< Clock range frequency for PLL between 8 and 16 MHz */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup RCC_PLL_VCO_Range PLL VCO Range 314 * @{ 315 */ 316 #define RCC_PLL_VCO_HIGH 0U /*!< Wide PLL VCO output range between 400 and 1600 MHz (reset) */ 317 #define RCC_PLL_VCO_LOW RCC_PLLCFGR_PLL1VCOSEL /*!< Low PLL VCO output range between 150 and 420 MHz */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup RCC_System_Clock_Type System Clock Type 323 * @{ 324 */ 325 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 326 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 327 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 328 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 329 #define RCC_CLOCKTYPE_PCLK4 0x00000010U /*!< PCLK4 to configure */ 330 #define RCC_CLOCKTYPE_PCLK5 0x00000020U /*!< PCLK5 to configure */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_System_Clock_Source System Clock Source 336 * @{ 337 */ 338 #define RCC_SYSCLKSOURCE_HSI 0U /*!< HSI selection as system clock */ 339 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_0 /*!< CSI selection as system clock */ 340 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ 341 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL1 selection as system clock */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 347 * @{ 348 */ 349 #define RCC_SYSCLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */ 350 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_0 /*!< CSI used as system clock */ 351 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ 352 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL1 used as system clock */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_System_Clock_Divider System Clock Divider 358 * @{ 359 */ 360 #define RCC_SYSCLK_DIV1 0U /*!< SYSCLK not divided */ 361 #define RCC_SYSCLK_DIV2 RCC_CDCFGR_CPRE_3 /*!< SYSCLK divided by 2 */ 362 #define RCC_SYSCLK_DIV4 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 4 */ 363 #define RCC_SYSCLK_DIV8 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1) /*!< SYSCLK divided by 8 */ 364 #define RCC_SYSCLK_DIV16 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 16 */ 365 #define RCC_SYSCLK_DIV64 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2) /*!< SYSCLK divided by 64 */ 366 #define RCC_SYSCLK_DIV128 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 128 */ 367 #define RCC_SYSCLK_DIV256 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1) /*!< SYSCLK divided by 256 */ 368 #define RCC_SYSCLK_DIV512 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0) /*!< SYSCLK divided by 512 */ 369 /** 370 * @} 371 */ 372 373 374 /** @defgroup RCC_HCLK_Clock_Source HCLK Clock Source 375 * @{ 376 */ 377 #define RCC_HCLK_DIV1 0U /*!< HCLK not divided */ 378 #define RCC_HCLK_DIV2 RCC_BMCFGR_BMPRE_3 /*!< HCLK divided by 2 */ 379 #define RCC_HCLK_DIV4 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 4 */ 380 #define RCC_HCLK_DIV8 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1) /*!< HCLK divided by 8 */ 381 #define RCC_HCLK_DIV16 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 16 */ 382 #define RCC_HCLK_DIV64 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2) /*!< HCLK divided by 64 */ 383 #define RCC_HCLK_DIV128 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 128 */ 384 #define RCC_HCLK_DIV256 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1) /*!< HCLK divided by 256 */ 385 #define RCC_HCLK_DIV512 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0) /*!< HCLK divided by 512 */ 386 /** 387 * @} 388 */ 389 390 /** @defgroup RCC_APB1_Clock_Source APB1 Clock Source 391 * @{ 392 */ 393 #define RCC_APB1_DIV1 0U /*!< APB1 not divided */ 394 #define RCC_APB1_DIV2 RCC_APBCFGR_PPRE1_2 /*!< APB1 divided by 2 */ 395 #define RCC_APB1_DIV4 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_0) /*!< APB1 divided by 4 */ 396 #define RCC_APB1_DIV8 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_1) /*!< APB1 divided by 8 */ 397 #define RCC_APB1_DIV16 RCC_APBCFGR_PPRE1 /*!< APB1 divided by 16 */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup RCC_APB2_Clock_Source APB2 Clock Source 403 * @{ 404 */ 405 #define RCC_APB2_DIV1 0U /*!< APB2 not divided */ 406 #define RCC_APB2_DIV2 RCC_APBCFGR_PPRE2_2 /*!< APB2 divided by 2 */ 407 #define RCC_APB2_DIV4 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_0) /*!< APB2 divided by 4 */ 408 #define RCC_APB2_DIV8 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_1) /*!< APB2 divided by 8 */ 409 #define RCC_APB2_DIV16 RCC_APBCFGR_PPRE2 /*!< APB2 divided by 16 */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup RCC_APB4_Clock_Source APB4 Clock Source 415 * @{ 416 */ 417 #define RCC_APB4_DIV1 0U /*!< APB4 not divided */ 418 #define RCC_APB4_DIV2 RCC_APBCFGR_PPRE4_2 /*!< APB4 divided by 2 */ 419 #define RCC_APB4_DIV4 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_0) /*!< APB4 divided by 4 */ 420 #define RCC_APB4_DIV8 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_1) /*!< APB4 divided by 8 */ 421 #define RCC_APB4_DIV16 RCC_APBCFGR_PPRE4 /*!< APB4 divided by 16 */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup RCC_APB5_Clock_Source APB5 Clock Source 427 * @{ 428 */ 429 #define RCC_APB5_DIV1 0U /*!< APB5 not divided */ 430 #define RCC_APB5_DIV2 RCC_APBCFGR_PPRE5_2 /*!< APB5 divided by 2 */ 431 #define RCC_APB5_DIV4 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_0) /*!< APB5 divided by 4 */ 432 #define RCC_APB5_DIV8 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_1) /*!< APB5 divided by 8 */ 433 #define RCC_APB5_DIV16 RCC_APBCFGR_PPRE5 /*!< APB5 divided by 16 */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 439 * @{ 440 */ 441 #define RCC_RTCCLKSOURCE_DISABLE 0U /*!< RTC clock is disabled */ 442 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 443 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 444 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((0x02U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 2 used as RTC clock */ 445 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((0x03U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 3 used as RTC clock */ 446 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x04U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ 447 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((0x05U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 5 used as RTC clock */ 448 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((0x06U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 6 used as RTC clock */ 449 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((0x07U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 7 used as RTC clock */ 450 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((0x08U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 8 used as RTC clock */ 451 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x09U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ 452 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((0x0AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 10 used as RTC clock */ 453 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((0x0BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 11 used as RTC clock */ 454 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((0x0CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 12 used as RTC clock */ 455 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((0x0DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 13 used as RTC clock */ 456 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((0x0EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 14 used as RTC clock */ 457 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((0x0FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 15 used as RTC clock */ 458 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x10U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ 459 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((0x11U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 17 used as RTC clock */ 460 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((0x12U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 18 used as RTC clock */ 461 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((0x13U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 19 used as RTC clock */ 462 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((0x14U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 20 used as RTC clock */ 463 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((0x15U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 21 used as RTC clock */ 464 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((0x16U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 22 used as RTC clock */ 465 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((0x17U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 23 used as RTC clock */ 466 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((0x18U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 24 used as RTC clock */ 467 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x19U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ 468 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((0x1AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 26 used as RTC clock */ 469 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((0x1BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 27 used as RTC clock */ 470 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((0x1CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 28 used as RTC clock */ 471 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((0x1DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 29 used as RTC clock */ 472 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((0x1EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 30 used as RTC clock */ 473 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((0x1FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 31 used as RTC clock */ 474 #define RCC_RTCCLKSOURCE_HSE_DIV32 ((0x20U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 475 #define RCC_RTCCLKSOURCE_HSE_DIV33 ((0x21U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 33 used as RTC clock */ 476 #define RCC_RTCCLKSOURCE_HSE_DIV34 ((0x22U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 34 used as RTC clock */ 477 #define RCC_RTCCLKSOURCE_HSE_DIV35 ((0x23U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 35 used as RTC clock */ 478 #define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x24U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ 479 #define RCC_RTCCLKSOURCE_HSE_DIV37 ((0x25U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 37 used as RTC clock */ 480 #define RCC_RTCCLKSOURCE_HSE_DIV38 ((0x26U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 38 used as RTC clock */ 481 #define RCC_RTCCLKSOURCE_HSE_DIV39 ((0x27U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 39 used as RTC clock */ 482 #define RCC_RTCCLKSOURCE_HSE_DIV40 ((0x28U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 40 used as RTC clock */ 483 #define RCC_RTCCLKSOURCE_HSE_DIV41 ((0x29U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 41 used as RTC clock */ 484 #define RCC_RTCCLKSOURCE_HSE_DIV42 ((0x2AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 42 used as RTC clock */ 485 #define RCC_RTCCLKSOURCE_HSE_DIV43 ((0x2BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 43 used as RTC clock */ 486 #define RCC_RTCCLKSOURCE_HSE_DIV44 ((0x2CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 44 used as RTC clock */ 487 #define RCC_RTCCLKSOURCE_HSE_DIV45 ((0x2DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 45 used as RTC clock */ 488 #define RCC_RTCCLKSOURCE_HSE_DIV46 ((0x2EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 46 used as RTC clock */ 489 #define RCC_RTCCLKSOURCE_HSE_DIV47 ((0x2FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 47 used as RTC clock */ 490 #define RCC_RTCCLKSOURCE_HSE_DIV48 ((0x30U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 48 used as RTC clock */ 491 #define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x31U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ 492 #define RCC_RTCCLKSOURCE_HSE_DIV50 ((0x32U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 50 used as RTC clock */ 493 #define RCC_RTCCLKSOURCE_HSE_DIV51 ((0x33U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 51 used as RTC clock */ 494 #define RCC_RTCCLKSOURCE_HSE_DIV52 ((0x34U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 52 used as RTC clock */ 495 #define RCC_RTCCLKSOURCE_HSE_DIV53 ((0x35U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 53 used as RTC clock */ 496 #define RCC_RTCCLKSOURCE_HSE_DIV54 ((0x36U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 54 used as RTC clock */ 497 #define RCC_RTCCLKSOURCE_HSE_DIV55 ((0x37U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 55 used as RTC clock */ 498 #define RCC_RTCCLKSOURCE_HSE_DIV56 ((0x38U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 56 used as RTC clock */ 499 #define RCC_RTCCLKSOURCE_HSE_DIV57 ((0x39U << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 57 used as RTC clock */ 500 #define RCC_RTCCLKSOURCE_HSE_DIV58 ((0x3AU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 58 used as RTC clock */ 501 #define RCC_RTCCLKSOURCE_HSE_DIV59 ((0x3BU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 59 used as RTC clock */ 502 #define RCC_RTCCLKSOURCE_HSE_DIV60 ((0x3CU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 60 used as RTC clock */ 503 #define RCC_RTCCLKSOURCE_HSE_DIV61 ((0x3DU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 61 used as RTC clock */ 504 #define RCC_RTCCLKSOURCE_HSE_DIV62 ((0x3EU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 62 used as RTC clock */ 505 #define RCC_RTCCLKSOURCE_HSE_DIV63 ((0x3FU << 12U) | RCC_BDCR_RTCSEL) /*!< HSE oscillator clock divided by 63 used as RTC clock */ 506 /** 507 * @} 508 */ 509 510 /** @defgroup RCC_MCOx_Index MCOx Index 511 * @{ 512 */ 513 514 /* @cond */ 515 /* 32 28 20 16 0 516 -------------------------------- 517 | MCO | GPIO | GPIO | GPIO | 518 | Index | AF | Port | Pin | 519 -------------------------------*/ 520 521 #define RCC_MCO_GPIOPORT_POS 16U 522 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 523 #define RCC_MCO_GPIOAF_POS 20U 524 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 525 #define RCC_MCO_INDEX_POS 28U 526 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 527 528 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 529 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ 530 /* @endcond */ 531 532 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ 533 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 534 #define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ 535 536 #define RCC_MCO2_PC9 (RCC_MCO2_INDEX |\ 537 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOC) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) 538 #define RCC_MCO2 RCC_MCO2_PC9 /*!< Alias for compatibility */ 539 540 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 541 /** 542 * @} 543 */ 544 545 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 546 * @{ 547 */ 548 #define RCC_MCO1SOURCE_HSI 0U /*!< HSI clock selected as MCO1 source (reset) */ 549 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1SEL_0 /*!< LSE clock selected as MCO1 source */ 550 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1SEL_1 /*!< HSE clock selected as MCO1 source */ 551 #define RCC_MCO1SOURCE_PLL1Q (RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0) /*!< PLL1Q clock selected as MCO1 source */ 552 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1SEL_2 /*!< HSI48 clock selected as MCO1 source */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 558 * @{ 559 */ 560 #define RCC_MCO2SOURCE_SYSCLK 0U /*!< System clock selected as MCO2 source (reset) */ 561 #define RCC_MCO2SOURCE_PLL2P RCC_CFGR_MCO2SEL_0 /*!< PLL2P clock selected as MCO2 source */ 562 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_1 /*!< HSE clock selected as MCO2 source */ 563 #define RCC_MCO2SOURCE_PLL1P (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< PLL1P clock selected as MCO2 source */ 564 #define RCC_MCO2SOURCE_CSI RCC_CFGR_MCO2SEL_2 /*!< CSI clock selected as MCO2 source */ 565 #define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< LSI clock selected as MCO2 source */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 571 * @{ 572 */ 573 #define RCC_MCODIV_NONE 0U /*!< No MCO prescaler (reset) */ 574 #define RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0 /*!< MCO divided by 1 */ 575 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1 /*!< MCO divided by 2 */ 576 #define RCC_MCODIV_3 (RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 3 */ 577 #define RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2 /*!< MCO divided by 4 */ 578 #define RCC_MCODIV_5 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 5 */ 579 #define RCC_MCODIV_6 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 6 */ 580 #define RCC_MCODIV_7 (RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 7 */ 581 #define RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3 /*!< MCO divided by 8 */ 582 #define RCC_MCODIV_9 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 9 */ 583 #define RCC_MCODIV_10 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 10 */ 584 #define RCC_MCODIV_11 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 11 */ 585 #define RCC_MCODIV_12 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2) /*!< MCO divided by 12 */ 586 #define RCC_MCODIV_13 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_0) /*!< MCO divided by 13 */ 587 #define RCC_MCODIV_14 (RCC_CFGR_MCO1PRE_3 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_1) /*!< MCO divided by 14 */ 588 #define RCC_MCODIV_15 RCC_CFGR_MCO1PRE /*!< MCO divided by 15 */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup RCC_Interrupt Interrupt 594 * @{ 595 */ 596 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt */ 597 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt */ 598 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt */ 599 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt */ 600 #define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt */ 601 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt */ 602 #define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt */ 603 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt */ 604 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt */ 605 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt */ 606 #define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt (flag only) */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup RCC_Flag Flag 612 * Elements values convention: XXXYYYYYb 613 * - YYYYY : Flag position in the register 614 * - XXX : Register index 615 * - 001: CR register 616 * - 010: BDCR register 617 * - 011: CSR register 618 * - 100: RSR register 619 * @{ 620 */ 621 #define RCC_FLAG_HSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 622 #define RCC_FLAG_HSIDIV ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos) /*!< HSIDIV Ready flag */ 623 #define RCC_FLAG_CSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos) /*!< CSI Ready flag */ 624 #define RCC_FLAG_HSI48RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 625 #define RCC_FLAG_HSERDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 626 #define RCC_FLAG_PLL1RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos) /*!< PLL1 Ready flag */ 627 #define RCC_FLAG_PLL2RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos) /*!< PLL2 Ready flag */ 628 #define RCC_FLAG_PLL3RDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos) /*!< PLL3 Ready flag */ 629 630 /* Flags in the BDCR register */ 631 #define RCC_FLAG_LSERDY ((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 632 #define RCC_FLAG_LSECSSD ((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 633 634 /* Flags in the CSR register */ 635 #define RCC_FLAG_LSIRDY ((RCC_CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 636 637 /* Flags in the RSR register */ 638 #define RCC_FLAG_BORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos) /*!< BOR reset flag */ 639 #define RCC_FLAG_PINRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos) /*!< PIN reset flag */ 640 #define RCC_FLAG_PORRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PORRSTF_Pos) /*!< Power-on reset flag */ 641 #define RCC_FLAG_SFTRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos) /*!< Software Reset flag */ 642 #define RCC_FLAG_IWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 643 #define RCC_FLAG_WWDGRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 644 #define RCC_FLAG_LPWRRST ((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 650 * @{ 651 */ 652 #define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ 653 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 654 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 655 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup RCC_Reset_Flag Reset Flag 661 * @{ 662 */ 663 #define RCC_RESET_FLAG_OBL RCC_RSR_OBLRSTF /*!< Option Byte Loader reset flag */ 664 #define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ 665 #define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 666 #define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ 667 #define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 668 #define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ 669 #define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ 670 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 671 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 672 RCC_RESET_FLAG_LPWR) 673 /** 674 * @} 675 */ 676 677 /** @defgroup RCC_Stop_WakeUpClock Stop WakeUp Clock 678 * @{ 679 */ 680 #define RCC_STOP_WAKEUPCLOCK_HSI 0U /*!< HSI selected as wake up system clock from system Stop (default after reset) */ 681 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK /*!< CSI selected as wake up system clock from system Stop */ 682 /** 683 * @} 684 */ 685 686 /** @defgroup RCC_Stop_KernelWakeUpClock Stop Kernel WakeUp Clock 687 * @{ 688 */ 689 #define RCC_STOP_KERWAKEUPCLOCK_HSI 0U /*!< HSI selected as wake up kernel clock from system Stop (default after reset) */ 690 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK /*!< CSI selected as wake up kernel clock from system Stop */ 691 /** 692 * @} 693 */ 694 695 /** 696 * @} 697 */ 698 699 /* Exported macros -----------------------------------------------------------*/ 700 701 /** @defgroup RCC_Exported_Macros RCC Exported Macros 702 * @{ 703 */ 704 705 /** @defgroup RCC_AXI_Clock_Gating_Enable_Disable AXI Interconnect, Master and Slave Clock Gating Enable Disable 706 * @brief Enable or disable the clock gating. 707 * @note The dynamic power consumption can be optimized by enabling the functional clock gating. 708 * After reset, the clock gating is enabled (except for JTAG if a JTAG connection has been detected). 709 * @{ 710 */ 711 712 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICKG) 713 714 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCKG) 715 716 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMCCKG) 717 718 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA1CKG) 719 720 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCKG) 721 722 #define __HAL_RCC_AXI_MASTER_GPU2D_0_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS0CKG) 723 724 #define __HAL_RCC_AXI_MASTER_GPU2D_1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS1CKG) 725 726 #define __HAL_RCC_AXI_MASTER_GPU2D_CACHE_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DCKG) 727 728 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIPPCKG) 729 730 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2DCKG) 731 732 #define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_LTDCCKG) 733 734 #define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUMCKG) 735 736 #define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUSCKG) 737 738 #define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBSCKG) 739 740 #define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FMCCKG) 741 742 #define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI1CKG) 743 744 #define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI2CKG) 745 746 #define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM0CKG) 747 748 #define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM1CKG) 749 750 #define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM2CKG) 751 752 #define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM3CKG) 753 754 #define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_FLIFTCKG) 755 756 #define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_EXTICKG) 757 758 #define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_ENABLE() CLEAR_BIT(RCC->CKGDISR, RCC_CKGDISR_JTAGCKG) 759 760 761 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICKG) 762 763 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCKG) 764 765 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMCCKG) 766 767 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA1CKG) 768 769 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCKG) 770 771 #define __HAL_RCC_AXI_MASTER_GPU_0_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS0CKG) 772 773 #define __HAL_RCC_AXI_MASTER_GPU_1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DS1CKG) 774 775 #define __HAL_RCC_AXI_MASTER_GPU_CACHE_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2DCKG) 776 777 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIPPCKG) 778 779 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2DCKG) 780 781 #define __HAL_RCC_AXI_MASTER_LTDC_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_LTDCCKG) 782 783 #define __HAL_RCC_AXI_MASTER_GFXMMU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUMCKG) 784 785 #define __HAL_RCC_AXI_SLAVE_GFXMMU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GFXMMUSCKG) 786 787 #define __HAL_RCC_AXI_SLAVE_AHB_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBSCKG) 788 789 #define __HAL_RCC_AXI_SLAVE_FMC_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FMCCKG) 790 791 #define __HAL_RCC_AXI_SLAVE_XSPI1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI1CKG) 792 793 #define __HAL_RCC_AXI_SLAVE_XSPI2_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_XSPI2CKG) 794 795 #define __HAL_RCC_AXI_SLAVE_SRAM0_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM0CKG) 796 797 #define __HAL_RCC_AXI_SLAVE_SRAM1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM1CKG) 798 799 #define __HAL_RCC_AXI_SLAVE_SRAM2_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM2CKG) 800 801 #define __HAL_RCC_AXI_SLAVE_SRAM3_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXISRAM3CKG) 802 803 #define __HAL_RCC_AXI_SLAVE_FLASH_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_FLIFTCKG) 804 805 #define __HAL_RCC_AXI_SLAVE_EXTI_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_EXTICKG) 806 807 #define __HAL_RCC_AXI_SLAVE_JTAG_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_JTAGCKG) 808 809 /** 810 * @} 811 */ 812 813 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 814 * @brief Enable or disable the AHB1 peripheral clock. 815 * @note After reset, the peripheral clock (used for registers read/write access) 816 * is disabled and the application software has to enable this clock before 817 * using it. 818 * @{ 819 */ 820 821 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 822 __IO uint32_t tmpreg; \ 823 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN);\ 824 /* Delay after an RCC peripheral clock enabling */ \ 825 tmpreg = READ_REG(RCC->AHB1ENR);\ 826 UNUSED(tmpreg); \ 827 } while(0) 828 829 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 830 __IO uint32_t tmpreg; \ 831 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ 832 /* Delay after an RCC peripheral clock enabling */ \ 833 tmpreg = READ_REG(RCC->AHB1ENR);\ 834 UNUSED(tmpreg); \ 835 } while(0) 836 837 #if defined(ETH) 838 #define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ 839 __IO uint32_t tmpreg; \ 840 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ 841 /* Delay after an RCC peripheral clock enabling */ \ 842 tmpreg = READ_REG(RCC->AHB1ENR);\ 843 UNUSED(tmpreg); \ 844 } while(0) 845 846 #define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ 847 __IO uint32_t tmpreg; \ 848 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ 849 /* Delay after an RCC peripheral clock enabling */ \ 850 tmpreg = READ_REG(RCC->AHB1ENR);\ 851 UNUSED(tmpreg); \ 852 } while(0) 853 854 #define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ 855 __IO uint32_t tmpreg; \ 856 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ 857 /* Delay after an RCC peripheral clock enabling */ \ 858 tmpreg = READ_REG(RCC->AHB1ENR);\ 859 UNUSED(tmpreg); \ 860 } while(0) 861 #endif /* ETH */ 862 863 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 864 __IO uint32_t tmpreg; \ 865 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ 866 /* Delay after an RCC peripheral clock enabling */ \ 867 tmpreg = READ_REG(RCC->AHB1ENR);\ 868 UNUSED(tmpreg); \ 869 } while(0) 870 871 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 872 __IO uint32_t tmpreg; \ 873 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN);\ 874 /* Delay after an RCC peripheral clock enabling */ \ 875 tmpreg = READ_REG(RCC->AHB1ENR);\ 876 UNUSED(tmpreg); \ 877 } while(0) 878 879 #define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ 880 __IO uint32_t tmpreg; \ 881 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN);\ 882 /* Delay after an RCC peripheral clock enabling */ \ 883 tmpreg = READ_REG(RCC->AHB1ENR);\ 884 UNUSED(tmpreg); \ 885 } while(0) 886 887 #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ 888 __IO uint32_t tmpreg; \ 889 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN);\ 890 /* Delay after an RCC peripheral clock enabling */ \ 891 tmpreg = READ_REG(RCC->AHB1ENR);\ 892 UNUSED(tmpreg); \ 893 } while(0) 894 895 896 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 897 898 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN) 899 900 #if defined(ETH) 901 #define __HAL_RCC_ETH1MAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN) 902 903 #define __HAL_RCC_ETH1TX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN) 904 905 #define __HAL_RCC_ETH1RX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN) 906 #endif /* ETH */ 907 908 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN) 909 910 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN) 911 912 #define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN) 913 914 #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN) 915 916 /** 917 * @} 918 */ 919 920 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 921 * @brief Enable or disable the AHB2 peripheral clock. 922 * @note After reset, the peripheral clock (used for registers read/write access) 923 * is disabled and the application software has to enable this clock before 924 * using it. 925 * @{ 926 */ 927 928 #define __HAL_RCC_PSSI_CLK_ENABLE() do { \ 929 __IO uint32_t tmpreg; \ 930 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN);\ 931 /* Delay after an RCC peripheral clock enabling */ \ 932 tmpreg = READ_REG(RCC->AHB2ENR);\ 933 UNUSED(tmpreg); \ 934 } while(0) 935 936 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 937 __IO uint32_t tmpreg; \ 938 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ 939 /* Delay after an RCC peripheral clock enabling */ \ 940 tmpreg = READ_REG(RCC->AHB2ENR);\ 941 UNUSED(tmpreg); \ 942 } while(0) 943 944 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 945 __IO uint32_t tmpreg; \ 946 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ 947 /* Delay after an RCC peripheral clock enabling */ \ 948 tmpreg = READ_REG(RCC->AHB2ENR);\ 949 UNUSED(tmpreg); \ 950 } while(0) 951 952 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 953 __IO uint32_t tmpreg; \ 954 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN);\ 955 /* Delay after an RCC peripheral clock enabling */ \ 956 tmpreg = READ_REG(RCC->AHB2ENR);\ 957 UNUSED(tmpreg); \ 958 } while(0) 959 960 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 961 __IO uint32_t tmpreg; \ 962 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN);\ 963 /* Delay after an RCC peripheral clock enabling */ \ 964 tmpreg = READ_REG(RCC->AHB2ENR);\ 965 UNUSED(tmpreg); \ 966 } while(0) 967 968 #define __HAL_RCC_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) 969 970 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) 971 972 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) 973 974 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) 975 976 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) 977 978 /** 979 * @} 980 */ 981 982 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 983 * @brief Enable or disable the AHB3 peripheral clock. 984 * @note After reset, the peripheral clock (used for registers read/write access) 985 * is disabled and the application software has to enable this clock before 986 * using it. 987 * @{ 988 */ 989 990 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 991 __IO uint32_t tmpreg; \ 992 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN);\ 993 /* Delay after an RCC peripheral clock enabling */ \ 994 tmpreg = READ_REG(RCC->AHB3ENR);\ 995 UNUSED(tmpreg); \ 996 } while(0) 997 998 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 999 __IO uint32_t tmpreg; \ 1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN);\ 1001 /* Delay after an RCC peripheral clock enabling */ \ 1002 tmpreg = READ_REG(RCC->AHB3ENR);\ 1003 UNUSED(tmpreg); \ 1004 } while(0) 1005 1006 #if defined(CRYP) 1007 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ 1008 __IO uint32_t tmpreg; \ 1009 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN);\ 1010 /* Delay after an RCC peripheral clock enabling */ \ 1011 tmpreg = READ_REG(RCC->AHB3ENR);\ 1012 UNUSED(tmpreg); \ 1013 } while(0) 1014 #endif /* CRYP */ 1015 1016 #if defined(SAES) 1017 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1018 __IO uint32_t tmpreg; \ 1019 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN);\ 1020 /* Delay after an RCC peripheral clock enabling */ \ 1021 tmpreg = READ_REG(RCC->AHB3ENR);\ 1022 UNUSED(tmpreg); \ 1023 } while(0) 1024 #endif /* SAES */ 1025 1026 #if defined(PKA) 1027 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1028 __IO uint32_t tmpreg; \ 1029 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN);\ 1030 /* Delay after an RCC peripheral clock enabling */ \ 1031 tmpreg = READ_REG(RCC->AHB3ENR);\ 1032 UNUSED(tmpreg); \ 1033 } while(0) 1034 #endif /* PKA */ 1035 1036 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN) 1037 1038 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN) 1039 1040 #if defined(CRYP) 1041 #define __HAL_RCC_CRYP_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN) 1042 #endif /* CRYP */ 1043 1044 #if defined(SAES) 1045 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN) 1046 #endif /* SAES */ 1047 1048 #if defined(PKA) 1049 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN) 1050 #endif /* PKA */ 1051 1052 /** 1053 * @} 1054 */ 1055 1056 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable 1057 * @brief Enable or disable the AHB4 peripheral clock. 1058 * @note After reset, the peripheral clock (used for registers read/write access) 1059 * is disabled and the application software has to enable this clock before 1060 * using it. 1061 * @{ 1062 */ 1063 1064 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 1065 __IO uint32_t tmpreg; \ 1066 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ 1067 /* Delay after an RCC peripheral clock enabling */ \ 1068 tmpreg = READ_REG(RCC->AHB4ENR);\ 1069 UNUSED(tmpreg); \ 1070 } while(0) 1071 1072 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 1073 __IO uint32_t tmpreg; \ 1074 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ 1075 /* Delay after an RCC peripheral clock enabling */ \ 1076 tmpreg = READ_REG(RCC->AHB4ENR);\ 1077 UNUSED(tmpreg); \ 1078 } while(0) 1079 1080 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 1081 __IO uint32_t tmpreg; \ 1082 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ 1083 /* Delay after an RCC peripheral clock enabling */ \ 1084 tmpreg = READ_REG(RCC->AHB4ENR);\ 1085 UNUSED(tmpreg); \ 1086 } while(0) 1087 1088 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 1089 __IO uint32_t tmpreg; \ 1090 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ 1091 /* Delay after an RCC peripheral clock enabling */ \ 1092 tmpreg = READ_REG(RCC->AHB4ENR);\ 1093 UNUSED(tmpreg); \ 1094 } while(0) 1095 1096 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1097 __IO uint32_t tmpreg; \ 1098 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ 1099 /* Delay after an RCC peripheral clock enabling */ \ 1100 tmpreg = READ_REG(RCC->AHB4ENR);\ 1101 UNUSED(tmpreg); \ 1102 } while(0) 1103 1104 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1105 __IO uint32_t tmpreg; \ 1106 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ 1107 /* Delay after an RCC peripheral clock enabling */ \ 1108 tmpreg = READ_REG(RCC->AHB4ENR);\ 1109 UNUSED(tmpreg); \ 1110 } while(0) 1111 1112 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1113 __IO uint32_t tmpreg; \ 1114 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ 1115 /* Delay after an RCC peripheral clock enabling */ \ 1116 tmpreg = READ_REG(RCC->AHB4ENR);\ 1117 UNUSED(tmpreg); \ 1118 } while(0) 1119 1120 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 1121 __IO uint32_t tmpreg; \ 1122 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ 1123 /* Delay after an RCC peripheral clock enabling */ \ 1124 tmpreg = READ_REG(RCC->AHB4ENR);\ 1125 UNUSED(tmpreg); \ 1126 } while(0) 1127 1128 #define __HAL_RCC_GPIOM_CLK_ENABLE() do { \ 1129 __IO uint32_t tmpreg; \ 1130 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN);\ 1131 /* Delay after an RCC peripheral clock enabling */ \ 1132 tmpreg = READ_REG(RCC->AHB4ENR);\ 1133 UNUSED(tmpreg); \ 1134 } while(0) 1135 1136 #define __HAL_RCC_GPION_CLK_ENABLE() do { \ 1137 __IO uint32_t tmpreg; \ 1138 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN);\ 1139 /* Delay after an RCC peripheral clock enabling */ \ 1140 tmpreg = READ_REG(RCC->AHB4ENR);\ 1141 UNUSED(tmpreg); \ 1142 } while(0) 1143 1144 #define __HAL_RCC_GPIOO_CLK_ENABLE() do { \ 1145 __IO uint32_t tmpreg; \ 1146 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN);\ 1147 /* Delay after an RCC peripheral clock enabling */ \ 1148 tmpreg = READ_REG(RCC->AHB4ENR);\ 1149 UNUSED(tmpreg); \ 1150 } while(0) 1151 1152 #define __HAL_RCC_GPIOP_CLK_ENABLE() do { \ 1153 __IO uint32_t tmpreg; \ 1154 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN);\ 1155 /* Delay after an RCC peripheral clock enabling */ \ 1156 tmpreg = READ_REG(RCC->AHB4ENR);\ 1157 UNUSED(tmpreg); \ 1158 } while(0) 1159 1160 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 1161 __IO uint32_t tmpreg; \ 1162 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ 1163 /* Delay after an RCC peripheral clock enabling */ \ 1164 tmpreg = READ_REG(RCC->AHB4ENR);\ 1165 UNUSED(tmpreg); \ 1166 } while(0) 1167 1168 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 1169 __IO uint32_t tmpreg; \ 1170 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ 1171 /* Delay after an RCC peripheral clock enabling */ \ 1172 tmpreg = READ_REG(RCC->AHB4ENR);\ 1173 UNUSED(tmpreg); \ 1174 } while(0) 1175 1176 1177 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) 1178 1179 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) 1180 1181 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) 1182 1183 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) 1184 1185 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) 1186 1187 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) 1188 1189 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) 1190 1191 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) 1192 1193 #define __HAL_RCC_GPIOM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) 1194 1195 #define __HAL_RCC_GPION_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) 1196 1197 #define __HAL_RCC_GPIOO_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) 1198 1199 #define __HAL_RCC_GPIOP_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) 1200 1201 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) 1202 1203 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) 1204 1205 /** 1206 * @} 1207 */ 1208 1209 /** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable AHB5 Peripheral Clock Enable Disable 1210 * @brief Enable or disable the AHB5 peripheral clock. 1211 * @note After reset, the peripheral clock (used for registers read/write access) 1212 * is disabled and the application software has to enable this clock before 1213 * using it. 1214 * @{ 1215 */ 1216 1217 #define __HAL_RCC_HPDMA1_CLK_ENABLE() do { \ 1218 __IO uint32_t tmpreg; \ 1219 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN);\ 1220 /* Delay after an RCC peripheral clock enabling */ \ 1221 tmpreg = READ_REG(RCC->AHB5ENR);\ 1222 UNUSED(tmpreg); \ 1223 } while(0) 1224 1225 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 1226 __IO uint32_t tmpreg; \ 1227 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN);\ 1228 /* Delay after an RCC peripheral clock enabling */ \ 1229 tmpreg = READ_REG(RCC->AHB5ENR);\ 1230 UNUSED(tmpreg); \ 1231 } while(0) 1232 1233 #if defined(JPEG) 1234 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ 1235 __IO uint32_t tmpreg; \ 1236 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN);\ 1237 /* Delay after an RCC peripheral clock enabling */ \ 1238 tmpreg = READ_REG(RCC->AHB5ENR);\ 1239 UNUSED(tmpreg); \ 1240 } while(0) 1241 #endif /* JPEG */ 1242 1243 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1244 __IO uint32_t tmpreg; \ 1245 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN);\ 1246 /* Delay after an RCC peripheral clock enabling */ \ 1247 tmpreg = READ_REG(RCC->AHB5ENR);\ 1248 UNUSED(tmpreg); \ 1249 } while(0) 1250 1251 #define __HAL_RCC_XSPI1_CLK_ENABLE() do { \ 1252 __IO uint32_t tmpreg; \ 1253 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN);\ 1254 /* Delay after an RCC peripheral clock enabling */ \ 1255 tmpreg = READ_REG(RCC->AHB5ENR);\ 1256 UNUSED(tmpreg); \ 1257 } while(0) 1258 1259 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1260 __IO uint32_t tmpreg; \ 1261 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN);\ 1262 /* Delay after an RCC peripheral clock enabling */ \ 1263 tmpreg = READ_REG(RCC->AHB5ENR);\ 1264 UNUSED(tmpreg); \ 1265 } while(0) 1266 1267 #define __HAL_RCC_XSPI2_CLK_ENABLE() do { \ 1268 __IO uint32_t tmpreg; \ 1269 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN);\ 1270 /* Delay after an RCC peripheral clock enabling */ \ 1271 tmpreg = READ_REG(RCC->AHB5ENR);\ 1272 UNUSED(tmpreg); \ 1273 } while(0) 1274 1275 #define __HAL_RCC_XSPIM_CLK_ENABLE() do { \ 1276 __IO uint32_t tmpreg; \ 1277 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN);\ 1278 /* Delay after an RCC peripheral clock enabling */ \ 1279 tmpreg = READ_REG(RCC->AHB5ENR);\ 1280 UNUSED(tmpreg); \ 1281 } while(0) 1282 1283 #if defined(GFXMMU) 1284 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 1285 __IO uint32_t tmpreg; \ 1286 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN);\ 1287 /* Delay after an RCC peripheral clock enabling */ \ 1288 tmpreg = READ_REG(RCC->AHB5ENR);\ 1289 UNUSED(tmpreg); \ 1290 } while(0) 1291 #endif /* GFXMMU */ 1292 1293 #if defined(GPU2D) 1294 #define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ 1295 __IO uint32_t tmpreg; \ 1296 SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN);\ 1297 /* Delay after an RCC peripheral clock enabling */ \ 1298 tmpreg = READ_REG(RCC->AHB5ENR);\ 1299 UNUSED(tmpreg); \ 1300 } while(0) 1301 #endif /* GPU2D */ 1302 1303 #define __HAL_RCC_HPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) 1304 1305 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) 1306 1307 #if defined(JPEG) 1308 #define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) 1309 #endif /* JPEG */ 1310 1311 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) 1312 1313 #define __HAL_RCC_XSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) 1314 1315 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) 1316 1317 #define __HAL_RCC_XSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) 1318 1319 #define __HAL_RCC_XSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) 1320 1321 #if defined(GFXMMU) 1322 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) 1323 #endif /* GFXMMU */ 1324 1325 #if defined(GPU2D) 1326 #define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) 1327 #endif /* GPU2D */ 1328 1329 /** 1330 * @} 1331 */ 1332 1333 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1334 * @brief Enable or disable the APB1 peripheral clock. 1335 * @note After reset, the peripheral clock (used for registers read/write access) 1336 * is disabled and the application software has to enable this clock before 1337 * using it. 1338 * @{ 1339 */ 1340 1341 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1342 __IO uint32_t tmpreg; \ 1343 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);\ 1344 /* Delay after an RCC peripheral clock enabling */ \ 1345 tmpreg = READ_REG(RCC->APB1ENR1);\ 1346 UNUSED(tmpreg); \ 1347 } while(0) 1348 1349 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1350 __IO uint32_t tmpreg; \ 1351 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN);\ 1352 /* Delay after an RCC peripheral clock enabling */ \ 1353 tmpreg = READ_REG(RCC->APB1ENR1);\ 1354 UNUSED(tmpreg); \ 1355 } while(0) 1356 1357 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1358 __IO uint32_t tmpreg; \ 1359 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN);\ 1360 /* Delay after an RCC peripheral clock enabling */ \ 1361 tmpreg = READ_REG(RCC->APB1ENR1);\ 1362 UNUSED(tmpreg); \ 1363 } while(0) 1364 1365 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1366 __IO uint32_t tmpreg; \ 1367 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN);\ 1368 /* Delay after an RCC peripheral clock enabling */ \ 1369 tmpreg = READ_REG(RCC->APB1ENR1);\ 1370 UNUSED(tmpreg); \ 1371 } while(0) 1372 1373 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1374 __IO uint32_t tmpreg; \ 1375 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN);\ 1376 /* Delay after an RCC peripheral clock enabling */ \ 1377 tmpreg = READ_REG(RCC->APB1ENR1);\ 1378 UNUSED(tmpreg); \ 1379 } while(0) 1380 1381 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1382 __IO uint32_t tmpreg; \ 1383 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN);\ 1384 /* Delay after an RCC peripheral clock enabling */ \ 1385 tmpreg = READ_REG(RCC->APB1ENR1);\ 1386 UNUSED(tmpreg); \ 1387 } while(0) 1388 1389 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1390 __IO uint32_t tmpreg; \ 1391 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN);\ 1392 /* Delay after an RCC peripheral clock enabling */ \ 1393 tmpreg = READ_REG(RCC->APB1ENR1);\ 1394 UNUSED(tmpreg); \ 1395 } while(0) 1396 1397 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1398 __IO uint32_t tmpreg; \ 1399 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN);\ 1400 /* Delay after an RCC peripheral clock enabling */ \ 1401 tmpreg = READ_REG(RCC->APB1ENR1);\ 1402 UNUSED(tmpreg); \ 1403 } while(0) 1404 1405 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1406 __IO uint32_t tmpreg; \ 1407 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN);\ 1408 /* Delay after an RCC peripheral clock enabling */ \ 1409 tmpreg = READ_REG(RCC->APB1ENR1);\ 1410 UNUSED(tmpreg); \ 1411 } while(0) 1412 1413 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1414 __IO uint32_t tmpreg; \ 1415 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN);\ 1416 /* Delay after an RCC peripheral clock enabling */ \ 1417 tmpreg = READ_REG(RCC->APB1ENR1);\ 1418 UNUSED(tmpreg); \ 1419 } while(0) 1420 1421 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1422 __IO uint32_t tmpreg; \ 1423 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN);\ 1424 /* Delay after an RCC peripheral clock enabling */ \ 1425 tmpreg = READ_REG(RCC->APB1ENR1);\ 1426 UNUSED(tmpreg); \ 1427 } while(0) 1428 1429 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1430 __IO uint32_t tmpreg; \ 1431 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN);\ 1432 /* Delay after an RCC peripheral clock enabling */ \ 1433 tmpreg = READ_REG(RCC->APB1ENR1);\ 1434 UNUSED(tmpreg); \ 1435 } while(0) 1436 1437 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1438 __IO uint32_t tmpreg; \ 1439 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN);\ 1440 /* Delay after an RCC peripheral clock enabling */ \ 1441 tmpreg = READ_REG(RCC->APB1ENR1);\ 1442 UNUSED(tmpreg); \ 1443 } while(0) 1444 1445 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ 1446 __IO uint32_t tmpreg; \ 1447 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN);\ 1448 /* Delay after an RCC peripheral clock enabling */ \ 1449 tmpreg = READ_REG(RCC->APB1ENR1);\ 1450 UNUSED(tmpreg); \ 1451 } while(0) 1452 1453 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1454 __IO uint32_t tmpreg; \ 1455 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN);\ 1456 /* Delay after an RCC peripheral clock enabling */ \ 1457 tmpreg = READ_REG(RCC->APB1ENR1);\ 1458 UNUSED(tmpreg); \ 1459 } while(0) 1460 1461 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1462 __IO uint32_t tmpreg; \ 1463 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN);\ 1464 /* Delay after an RCC peripheral clock enabling */ \ 1465 tmpreg = READ_REG(RCC->APB1ENR1);\ 1466 UNUSED(tmpreg); \ 1467 } while(0) 1468 1469 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1470 __IO uint32_t tmpreg; \ 1471 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN);\ 1472 /* Delay after an RCC peripheral clock enabling */ \ 1473 tmpreg = READ_REG(RCC->APB1ENR1);\ 1474 UNUSED(tmpreg); \ 1475 } while(0) 1476 1477 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1478 __IO uint32_t tmpreg; \ 1479 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN);\ 1480 /* Delay after an RCC peripheral clock enabling */ \ 1481 tmpreg = READ_REG(RCC->APB1ENR1);\ 1482 UNUSED(tmpreg); \ 1483 } while(0) 1484 1485 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1486 __IO uint32_t tmpreg; \ 1487 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\ 1488 /* Delay after an RCC peripheral clock enabling */ \ 1489 tmpreg = READ_REG(RCC->APB1ENR1);\ 1490 UNUSED(tmpreg); \ 1491 } while(0) 1492 1493 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1494 __IO uint32_t tmpreg; \ 1495 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN);\ 1496 /* Delay after an RCC peripheral clock enabling */ \ 1497 tmpreg = READ_REG(RCC->APB1ENR1);\ 1498 UNUSED(tmpreg); \ 1499 } while(0) 1500 1501 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1502 __IO uint32_t tmpreg; \ 1503 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN);\ 1504 /* Delay after an RCC peripheral clock enabling */ \ 1505 tmpreg = READ_REG(RCC->APB1ENR1);\ 1506 UNUSED(tmpreg); \ 1507 } while(0) 1508 1509 #define __HAL_RCC_I3C1_CLK_ENABLE() do { \ 1510 __IO uint32_t tmpreg; \ 1511 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\ 1512 /* Delay after an RCC peripheral clock enabling */ \ 1513 tmpreg = READ_REG(RCC->APB1ENR1);\ 1514 UNUSED(tmpreg); \ 1515 } while(0) 1516 1517 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1518 __IO uint32_t tmpreg; \ 1519 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN);\ 1520 /* Delay after an RCC peripheral clock enabling */ \ 1521 tmpreg = READ_REG(RCC->APB1ENR1);\ 1522 UNUSED(tmpreg); \ 1523 } while(0) 1524 1525 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1526 __IO uint32_t tmpreg; \ 1527 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN);\ 1528 /* Delay after an RCC peripheral clock enabling */ \ 1529 tmpreg = READ_REG(RCC->APB1ENR1);\ 1530 UNUSED(tmpreg); \ 1531 } while(0) 1532 1533 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1534 __IO uint32_t tmpreg; \ 1535 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN);\ 1536 /* Delay after an RCC peripheral clock enabling */ \ 1537 tmpreg = READ_REG(RCC->APB1ENR1);\ 1538 UNUSED(tmpreg); \ 1539 } while(0) 1540 1541 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1542 __IO uint32_t tmpreg; \ 1543 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN);\ 1544 /* Delay after an RCC peripheral clock enabling */ \ 1545 tmpreg = READ_REG(RCC->APB1ENR1);\ 1546 UNUSED(tmpreg); \ 1547 } while(0) 1548 1549 #define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ 1550 __IO uint32_t tmpreg; \ 1551 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN);\ 1552 /* Delay after an RCC peripheral clock enabling */ \ 1553 tmpreg = READ_REG(RCC->APB1ENR1);\ 1554 UNUSED(tmpreg); \ 1555 } while(0) 1556 1557 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 1558 __IO uint32_t tmpreg; \ 1559 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN);\ 1560 /* Delay after an RCC peripheral clock enabling */ \ 1561 tmpreg = READ_REG(RCC->APB1ENR1);\ 1562 UNUSED(tmpreg); \ 1563 } while(0) 1564 1565 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1566 __IO uint32_t tmpreg; \ 1567 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN);\ 1568 /* Delay after an RCC peripheral clock enabling */ \ 1569 tmpreg = READ_REG(RCC->APB1ENR1);\ 1570 UNUSED(tmpreg); \ 1571 } while(0) 1572 1573 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1574 1575 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1576 1577 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1578 1579 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1580 1581 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1582 1583 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1584 1585 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) 1586 1587 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) 1588 1589 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) 1590 1591 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1592 1593 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1594 1595 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1596 1597 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) 1598 1599 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1600 1601 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1602 1603 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1604 1605 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1606 1607 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) 1608 1609 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1610 1611 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1612 1613 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) 1614 1615 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) 1616 1617 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) 1618 1619 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) 1620 1621 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) 1622 1623 #define __HAL_RCC_MDIOS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) 1624 1625 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN) 1626 1627 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1628 1629 /** 1630 * @} 1631 */ 1632 1633 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1634 * @brief Enable or disable the APB2 peripheral clock. 1635 * @note After reset, the peripheral clock (used for registers read/write access) 1636 * is disabled and the application software has to enable this clock before 1637 * using it. 1638 * @{ 1639 */ 1640 1641 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1642 __IO uint32_t tmpreg; \ 1643 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 1644 /* Delay after an RCC peripheral clock enabling */ \ 1645 tmpreg = READ_REG(RCC->APB2ENR);\ 1646 UNUSED(tmpreg); \ 1647 } while(0) 1648 1649 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1650 __IO uint32_t tmpreg; \ 1651 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 1652 /* Delay after an RCC peripheral clock enabling */ \ 1653 tmpreg = READ_REG(RCC->APB2ENR);\ 1654 UNUSED(tmpreg); \ 1655 } while(0) 1656 1657 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1658 __IO uint32_t tmpreg; \ 1659 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 1660 /* Delay after an RCC peripheral clock enabling */ \ 1661 tmpreg = READ_REG(RCC->APB2ENR);\ 1662 UNUSED(tmpreg); \ 1663 } while(0) 1664 1665 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1666 __IO uint32_t tmpreg; \ 1667 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ 1668 /* Delay after an RCC peripheral clock enabling */ \ 1669 tmpreg = READ_REG(RCC->APB2ENR);\ 1670 UNUSED(tmpreg); \ 1671 } while(0) 1672 1673 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1674 __IO uint32_t tmpreg; \ 1675 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1676 /* Delay after an RCC peripheral clock enabling */ \ 1677 tmpreg = READ_REG(RCC->APB2ENR);\ 1678 UNUSED(tmpreg); \ 1679 } while(0) 1680 1681 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1682 __IO uint32_t tmpreg; \ 1683 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 1684 /* Delay after an RCC peripheral clock enabling */ \ 1685 tmpreg = READ_REG(RCC->APB2ENR);\ 1686 UNUSED(tmpreg); \ 1687 } while(0) 1688 1689 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1690 __IO uint32_t tmpreg; \ 1691 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 1692 /* Delay after an RCC peripheral clock enabling */ \ 1693 tmpreg = READ_REG(RCC->APB2ENR);\ 1694 UNUSED(tmpreg); \ 1695 } while(0) 1696 1697 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 1698 __IO uint32_t tmpreg; \ 1699 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1700 /* Delay after an RCC peripheral clock enabling */ \ 1701 tmpreg = READ_REG(RCC->APB2ENR);\ 1702 UNUSED(tmpreg); \ 1703 } while(0) 1704 1705 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1706 __IO uint32_t tmpreg; \ 1707 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ 1708 /* Delay after an RCC peripheral clock enabling */ \ 1709 tmpreg = READ_REG(RCC->APB2ENR);\ 1710 UNUSED(tmpreg); \ 1711 } while(0) 1712 1713 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1714 __IO uint32_t tmpreg; \ 1715 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ 1716 /* Delay after an RCC peripheral clock enabling */ \ 1717 tmpreg = READ_REG(RCC->APB2ENR);\ 1718 UNUSED(tmpreg); \ 1719 } while(0) 1720 1721 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1722 __IO uint32_t tmpreg; \ 1723 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ 1724 /* Delay after an RCC peripheral clock enabling */ \ 1725 tmpreg = READ_REG(RCC->APB2ENR);\ 1726 UNUSED(tmpreg); \ 1727 } while(0) 1728 1729 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1730 1731 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1732 1733 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1734 1735 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) 1736 1737 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1738 1739 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1740 1741 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1742 1743 #define __HAL_RCC_TIM9_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN) 1744 1745 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) 1746 1747 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1748 1749 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1750 1751 /** 1752 * @} 1753 */ 1754 1755 /** @defgroup RCC_APB4_Peripheral_Clock_Enable_Disable APB4 Peripheral Clock Enable Disable 1756 * @brief Enable or disable the APB4 peripheral clock. 1757 * @note After reset, the peripheral clock (used for registers read/write access) 1758 * is disabled and the application software has to enable this clock before 1759 * using it. 1760 * @{ 1761 */ 1762 1763 #define __HAL_RCC_SBS_CLK_ENABLE() do { \ 1764 __IO uint32_t tmpreg; \ 1765 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN);\ 1766 /* Delay after an RCC peripheral clock enabling */ \ 1767 tmpreg = READ_REG(RCC->APB4ENR);\ 1768 UNUSED(tmpreg); \ 1769 } while(0) 1770 1771 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1772 __IO uint32_t tmpreg; \ 1773 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ 1774 /* Delay after an RCC peripheral clock enabling */ \ 1775 tmpreg = READ_REG(RCC->APB4ENR);\ 1776 UNUSED(tmpreg); \ 1777 } while(0) 1778 1779 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1780 __IO uint32_t tmpreg; \ 1781 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ 1782 /* Delay after an RCC peripheral clock enabling */ \ 1783 tmpreg = READ_REG(RCC->APB4ENR);\ 1784 UNUSED(tmpreg); \ 1785 } while(0) 1786 1787 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1788 __IO uint32_t tmpreg; \ 1789 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ 1790 /* Delay after an RCC peripheral clock enabling */ \ 1791 tmpreg = READ_REG(RCC->APB4ENR);\ 1792 UNUSED(tmpreg); \ 1793 } while(0) 1794 1795 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1796 __IO uint32_t tmpreg; \ 1797 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ 1798 /* Delay after an RCC peripheral clock enabling */ \ 1799 tmpreg = READ_REG(RCC->APB4ENR);\ 1800 UNUSED(tmpreg); \ 1801 } while(0) 1802 1803 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1804 __IO uint32_t tmpreg; \ 1805 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ 1806 /* Delay after an RCC peripheral clock enabling */ \ 1807 tmpreg = READ_REG(RCC->APB4ENR);\ 1808 UNUSED(tmpreg); \ 1809 } while(0) 1810 1811 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 1812 __IO uint32_t tmpreg; \ 1813 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ 1814 /* Delay after an RCC peripheral clock enabling */ \ 1815 tmpreg = READ_REG(RCC->APB4ENR);\ 1816 UNUSED(tmpreg); \ 1817 } while(0) 1818 1819 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1820 __IO uint32_t tmpreg; \ 1821 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ 1822 /* Delay after an RCC peripheral clock enabling */ \ 1823 tmpreg = READ_REG(RCC->APB4ENR);\ 1824 UNUSED(tmpreg); \ 1825 } while(0) 1826 1827 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1828 __IO uint32_t tmpreg; \ 1829 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ 1830 /* Delay after an RCC peripheral clock enabling */ \ 1831 tmpreg = READ_REG(RCC->APB4ENR);\ 1832 UNUSED(tmpreg); \ 1833 } while(0) 1834 1835 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1836 __IO uint32_t tmpreg; \ 1837 SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ 1838 /* Delay after an RCC peripheral clock enabling */ \ 1839 tmpreg = READ_REG(RCC->APB4ENR);\ 1840 UNUSED(tmpreg); \ 1841 } while(0) 1842 1843 #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) 1844 1845 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) 1846 1847 #define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) 1848 1849 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) 1850 1851 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) 1852 1853 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) 1854 1855 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) 1856 1857 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) 1858 1859 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) 1860 1861 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) 1862 1863 /** 1864 * @} 1865 */ 1866 1867 /** @defgroup RCC_APB5_Peripheral_Clock_Enable_Disable APB5 Peripheral Clock Enable Disable 1868 * @brief Enable or disable the APB5 peripheral clock. 1869 * @note After reset, the peripheral clock (used for registers read/write access) 1870 * is disabled and the application software has to enable this clock before 1871 * using it. 1872 * @{ 1873 */ 1874 1875 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1876 __IO uint32_t tmpreg; \ 1877 SET_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN);\ 1878 /* Delay after an RCC peripheral clock enabling */ \ 1879 tmpreg = READ_REG(RCC->APB5ENR);\ 1880 UNUSED(tmpreg); \ 1881 } while(0) 1882 1883 #define __HAL_RCC_DCMIPP_CLK_ENABLE() do { \ 1884 __IO uint32_t tmpreg; \ 1885 SET_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN);\ 1886 /* Delay after an RCC peripheral clock enabling */ \ 1887 tmpreg = READ_REG(RCC->APB5ENR);\ 1888 UNUSED(tmpreg); \ 1889 } while(0) 1890 1891 #define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ 1892 __IO uint32_t tmpreg; \ 1893 SET_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN);\ 1894 /* Delay after an RCC peripheral clock enabling */ \ 1895 tmpreg = READ_REG(RCC->APB5ENR);\ 1896 UNUSED(tmpreg); \ 1897 } while(0) 1898 1899 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN) 1900 1901 #define __HAL_RCC_DCMIPP_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN) 1902 1903 #define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN) 1904 1905 /** 1906 * @} 1907 */ 1908 1909 /** @defgroup RCC_AHB1_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1910 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1911 * @note After reset, the peripheral clock (used for registers read/write access) 1912 * is disabled and the application software has to enable this clock before 1913 * using it. 1914 * @{ 1915 */ 1916 1917 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1918 1919 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN) != 0U) 1920 1921 #if defined(ETH) 1922 #define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN) != 0U) 1923 1924 #define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN) != 0U) 1925 1926 #define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN) != 0U) 1927 #endif /* ETH */ 1928 1929 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN) != 0U) 1930 1931 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGFSEN) != 0U) 1932 1933 #define __HAL_RCC_USBPHYC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USBPHYCEN) != 0U) 1934 1935 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADF1EN) != 0U) 1936 1937 /** 1938 * @} 1939 */ 1940 1941 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1942 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1943 * @note After reset, the peripheral clock (used for registers read/write access) 1944 * is disabled and the application software has to enable this clock before 1945 * using it. 1946 * @{ 1947 */ 1948 1949 #define __HAL_RCC_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PSSIEN) != 0U) 1950 1951 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN) != 0U) 1952 1953 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN) != 0U) 1954 1955 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM1EN) != 0U) 1956 1957 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) 1958 1959 /** 1960 * @} 1961 */ 1962 1963 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1964 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1965 * @note After reset, the peripheral clock (used for registers read/write access) 1966 * is disabled and the application software has to enable this clock before 1967 * using it. 1968 * @{ 1969 */ 1970 1971 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_RNGEN) != 0U) 1972 1973 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_HASHEN) != 0U) 1974 1975 #if defined(CRYP) 1976 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_CRYPEN) != 0U) 1977 #endif /* CRYP */ 1978 1979 #if defined(SAES) 1980 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SAESEN) != 0U) 1981 #endif /* SAES */ 1982 1983 #if defined(PKA) 1984 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PKAEN) != 0U) 1985 #endif /* PKA */ 1986 1987 /** 1988 * @} 1989 */ 1990 1991 /** @defgroup RCC_AHB4_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status 1992 * @brief Check whether the AHB4 peripheral clock is enabled or not. 1993 * @note After reset, the peripheral clock (used for registers read/write access) 1994 * is disabled and the application software has to enable this clock before 1995 * using it. 1996 * @{ 1997 */ 1998 1999 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) != 0U) 2000 2001 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) != 0U) 2002 2003 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) != 0U) 2004 2005 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) != 0U) 2006 2007 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) != 0U) 2008 2009 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) != 0U) 2010 2011 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) != 0U) 2012 2013 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) != 0U) 2014 2015 #define __HAL_RCC_GPIOM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) != 0U) 2016 2017 #define __HAL_RCC_GPION_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) != 0U) 2018 2019 #define __HAL_RCC_GPIOO_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) != 0U) 2020 2021 #define __HAL_RCC_GPIOP_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) != 0U) 2022 2023 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) != 0U) 2024 2025 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) != 0U) 2026 2027 /** 2028 * @} 2029 */ 2030 2031 /** @defgroup RCC_AHB5_Clock_Enable_Disable_Status AHB5 Peripheral Clock Enabled or Disabled Status 2032 * @brief Check whether the AHB5 peripheral clock is enabled or not. 2033 * @note After reset, the peripheral clock (used for registers read/write access) 2034 * is disabled and the application software has to enable this clock before 2035 * using it. 2036 * @{ 2037 */ 2038 2039 #define __HAL_RCC_HPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_HPDMA1EN) != 0U) 2040 2041 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_DMA2DEN) != 0U) 2042 2043 #if defined(JPEG) 2044 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_JPEGEN) != 0U) 2045 #endif /* JPEG */ 2046 2047 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_FMCEN) != 0U) 2048 2049 #define __HAL_RCC_XSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI1EN) != 0U) 2050 2051 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_SDMMC1EN) != 0U) 2052 2053 #define __HAL_RCC_XSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPI2EN) != 0U) 2054 2055 #define __HAL_RCC_XSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_XSPIMEN) != 0U) 2056 2057 #if defined(GFXMMU) 2058 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GFXMMUEN) != 0U) 2059 #endif /* GFXMMU */ 2060 2061 #if defined(GPU2D) 2062 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_GPU2DEN) != 0U) 2063 #endif /* GPU2D */ 2064 2065 /** 2066 * @} 2067 */ 2068 2069 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2070 * @brief Check whether the APB1 peripheral clock is enabled or not. 2071 * @note After reset, the peripheral clock (used for registers read/write access) 2072 * is disabled and the application software has to enable this clock before 2073 * using it. 2074 * @{ 2075 */ 2076 2077 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 2078 2079 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 2080 2081 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 2082 2083 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 2084 2085 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 2086 2087 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 2088 2089 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) != 0U) 2090 2091 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) != 0U) 2092 2093 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) != 0U) 2094 2095 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 2096 2097 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 2098 2099 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 2100 2101 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 2102 2103 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) != 0U) 2104 2105 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 2106 2107 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 2108 2109 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 2110 2111 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 2112 2113 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U) 2114 2115 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 2116 2117 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 2118 2119 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U) 2120 2121 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) != 0U) 2122 2123 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) != 0U) 2124 2125 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) != 0U) 2126 2127 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_CRSEN) != 0U) 2128 2129 #define __HAL_RCC_MDIOS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_MDIOSEN) != 0U) 2130 2131 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCANEN) != 0U) 2132 2133 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 2134 2135 /** 2136 * @} 2137 */ 2138 2139 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2140 * @brief Check whether the APB2 peripheral clock is enabled or not. 2141 * @note After reset, the peripheral clock (used for registers read/write access) 2142 * is disabled and the application software has to enable this clock before 2143 * using it. 2144 * @{ 2145 */ 2146 2147 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2148 2149 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2150 2151 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2152 2153 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) 2154 2155 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2156 2157 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2158 2159 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2160 2161 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN) != 0U) 2162 2163 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) != 0U) 2164 2165 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2166 2167 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2168 2169 /** 2170 * @} 2171 */ 2172 2173 /** @defgroup RCC_APB4_Clock_Enable_Disable_Status APB4 Peripheral Clock Enabled or Disabled Status 2174 * @brief Check whether the APB4 peripheral clock is enabled or not. 2175 * @note After reset, the peripheral clock (used for registers read/write access) 2176 * is disabled and the application software has to enable this clock before 2177 * using it. 2178 * @{ 2179 */ 2180 2181 #define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) != 0U) 2182 2183 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) != 0U) 2184 2185 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) != 0U) 2186 2187 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) != 0U) 2188 2189 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) != 0U) 2190 2191 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) != 0U) 2192 2193 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) != 0U) 2194 2195 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) != 0U) 2196 2197 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) != 0U) 2198 2199 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) != 0U) 2200 2201 /** 2202 * @} 2203 */ 2204 2205 /** @defgroup RCC_APB5_Clock_Enable_Disable_Status APB5 Peripheral Clock Enabled or Disabled Status 2206 * @brief Check whether the APB5 peripheral clock is enabled or not. 2207 * @note After reset, the peripheral clock (used for registers read/write access) 2208 * is disabled and the application software has to enable this clock before 2209 * using it. 2210 * @{ 2211 */ 2212 2213 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_LTDCEN) != 0U) 2214 2215 #define __HAL_RCC_DCMIPP_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_DCMIPPEN) != 0U) 2216 2217 #define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB5ENR, RCC_APB5ENR_GFXTIMEN) != 0U) 2218 2219 /** 2220 * @} 2221 */ 2222 2223 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2224 * @brief Force or release AHB1 peripheral reset. 2225 * @{ 2226 */ 2227 2228 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x8E008030UL) 2229 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0UL) 2230 2231 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2232 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2233 2234 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST) 2235 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADC12RST) 2236 2237 #if defined(ETH) 2238 #define __HAL_RCC_ETH1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST) 2239 #define __HAL_RCC_ETH1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETH1RST) 2240 #endif /* ETH */ 2241 2242 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST) 2243 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGHSRST) 2244 2245 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST) 2246 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_OTGFSRST) 2247 2248 #define __HAL_RCC_USBPHYC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST) 2249 #define __HAL_RCC_USBPHYC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_USBPHYCRST) 2250 2251 #define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST) 2252 #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ADF1RST) 2253 2254 /** 2255 * @} 2256 */ 2257 2258 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2259 * @brief Force or release AHB2 peripheral reset. 2260 * @{ 2261 */ 2262 2263 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00004202UL) 2264 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0UL) 2265 2266 #define __HAL_RCC_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST) 2267 #define __HAL_RCC_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PSSIRST) 2268 2269 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2270 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC2RST) 2271 2272 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST) 2273 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_CORDICRST) 2274 2275 /** 2276 * @} 2277 */ 2278 2279 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2280 * @brief Force or release AHB3 peripheral reset. 2281 * @{ 2282 */ 2283 2284 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000057UL) 2285 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0UL) 2286 2287 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST) 2288 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_RNGRST) 2289 2290 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST) 2291 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_HASHRST) 2292 2293 #if defined(CRYP) 2294 #define __HAL_RCC_CRYP_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST) 2295 #define __HAL_RCC_CRYP_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_CRYPRST) 2296 #endif /* CRYP */ 2297 2298 #if defined(SAES) 2299 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST) 2300 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_SAESRST) 2301 #endif /* SAES */ 2302 2303 #if defined(PKA) 2304 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST) 2305 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_PKARST) 2306 #endif /* PKA */ 2307 2308 /** 2309 * @} 2310 */ 2311 2312 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 2313 * @brief Force or release AHB4 peripheral reset. 2314 * @{ 2315 */ 2316 2317 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x0008B0FFUL) 2318 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0UL) 2319 2320 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST) 2321 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOARST) 2322 2323 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST) 2324 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOBRST) 2325 2326 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST) 2327 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOCRST) 2328 2329 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST) 2330 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIODRST) 2331 2332 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST) 2333 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOERST) 2334 2335 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST) 2336 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOFRST) 2337 2338 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST) 2339 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOGRST) 2340 2341 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST) 2342 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOHRST) 2343 2344 #define __HAL_RCC_GPIOM_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST) 2345 #define __HAL_RCC_GPIOM_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOMRST) 2346 2347 #define __HAL_RCC_GPION_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST) 2348 #define __HAL_RCC_GPION_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIONRST) 2349 2350 #define __HAL_RCC_GPIOO_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST) 2351 #define __HAL_RCC_GPIOO_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOORST) 2352 2353 #define __HAL_RCC_GPIOP_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST) 2354 #define __HAL_RCC_GPIOP_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_GPIOPRST) 2355 2356 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST) 2357 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_CRCRST) 2358 2359 /** 2360 * @} 2361 */ 2362 2363 /** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset 2364 * @brief Force or release AHB5 peripheral reset. 2365 * @{ 2366 */ 2367 2368 #define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x0018513BUL) 2369 #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0UL) 2370 2371 #define __HAL_RCC_HPDMA1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST) 2372 #define __HAL_RCC_HPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST) 2373 2374 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST) 2375 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST) 2376 2377 #if defined(JPEG) 2378 #define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST) 2379 #define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST) 2380 #endif /* JPEG */ 2381 2382 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST) 2383 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST) 2384 2385 #define __HAL_RCC_XSPI1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST) 2386 #define __HAL_RCC_XSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST) 2387 2388 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST) 2389 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST) 2390 2391 #define __HAL_RCC_XSPI2_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST) 2392 #define __HAL_RCC_XSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST) 2393 2394 #define __HAL_RCC_XSPIM_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST) 2395 #define __HAL_RCC_XSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST) 2396 2397 #if defined(GFXMMU) 2398 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST) 2399 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST) 2400 #endif /* GFXMMU */ 2401 2402 #if defined(GPU2D) 2403 #define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST) 2404 #define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST) 2405 #endif /* GPU2D */ 2406 2407 /** 2408 * @} 2409 */ 2410 2411 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2412 * @brief Force or release APB1 peripheral reset. 2413 * @{ 2414 */ 2415 2416 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2417 WRITE_REG(RCC->APB1RSTR1, 0xC8FFC3FFUL); \ 2418 WRITE_REG(RCC->APB1RSTR2, 0x08000122UL); \ 2419 } while(0) 2420 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2421 WRITE_REG(RCC->APB1RSTR1, 0UL); \ 2422 WRITE_REG(RCC->APB1RSTR2, 0UL); \ 2423 } while(0) 2424 2425 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2426 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2427 2428 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2429 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2430 2431 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2432 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2433 2434 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2435 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2436 2437 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2438 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2439 2440 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2441 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2442 2443 #define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST) 2444 #define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM12RST) 2445 2446 #define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST) 2447 #define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM13RST) 2448 2449 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST) 2450 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM14RST) 2451 2452 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2453 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 2454 2455 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2456 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2457 2458 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2459 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 2460 2461 #define __HAL_RCC_SPDIFRX_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST) 2462 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPDIFRXRST) 2463 2464 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2465 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2466 2467 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2468 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2469 2470 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2471 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2472 2473 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2474 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2475 2476 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) 2477 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) 2478 2479 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2480 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2481 2482 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2483 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 2484 2485 #define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) 2486 #define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1_I3C1RST) 2487 2488 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST) 2489 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CECRST) 2490 2491 #define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST) 2492 #define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART7RST) 2493 2494 #define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST) 2495 #define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART8RST) 2496 2497 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST) 2498 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_CRSRST) 2499 2500 #define __HAL_RCC_MDIOS_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST) 2501 #define __HAL_RCC_MDIOS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_MDIOSRST) 2502 2503 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST) 2504 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCANRST) 2505 2506 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2507 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2508 2509 /** 2510 * @} 2511 */ 2512 2513 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 2514 * @brief Force or release APB2 peripheral reset. 2515 * @{ 2516 */ 2517 2518 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xC8FFC3FFUL) 2519 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0UL) 2520 2521 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2522 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 2523 2524 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2525 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 2526 2527 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2528 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 2529 2530 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 2531 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 2532 2533 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2534 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 2535 2536 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2537 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 2538 2539 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2540 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 2541 2542 #define __HAL_RCC_TIM9_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST) 2543 #define __HAL_RCC_TIM9_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM9RST) 2544 2545 #define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST) 2546 #define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI5RST) 2547 2548 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2549 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 2550 2551 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2552 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 2553 2554 /** 2555 * @} 2556 */ 2557 2558 /** @defgroup RCC_APB4_Force_Release_Reset APB4 Peripheral Force Release Reset 2559 * @brief Force or release APB4 peripheral reset. 2560 * @{ 2561 */ 2562 2563 #define __HAL_RCC_APB4_FORCE_RESET() WRITE_REG(RCC->APB4RSTR, 0x04009E2AUL) 2564 #define __HAL_RCC_APB4_RELEASE_RESET() WRITE_REG(RCC->APB4RSTR, 0UL) 2565 2566 #define __HAL_RCC_SBS_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST) 2567 #define __HAL_RCC_SBS_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SBSRST) 2568 2569 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST) 2570 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPUART1RST) 2571 2572 #define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST) 2573 #define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_SPI6RST) 2574 2575 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST) 2576 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM2RST) 2577 2578 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST) 2579 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM3RST) 2580 2581 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST) 2582 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM4RST) 2583 2584 #define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST) 2585 #define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_LPTIM5RST) 2586 2587 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST) 2588 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_VREFRST) 2589 2590 #define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST) 2591 #define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB4RSTR, RCC_APB4RSTR_DTSRST) 2592 2593 /** 2594 * @} 2595 */ 2596 2597 /** @defgroup RCC_APB5_Force_Release_Reset APB5 Peripheral Force Release Reset 2598 * @brief Force or release APB5 peripheral reset. 2599 * @{ 2600 */ 2601 2602 #define __HAL_RCC_APB5_FORCE_RESET() WRITE_REG(RCC->APB5RSTR, 0x00000016UL) 2603 #define __HAL_RCC_APB5_RELEASE_RESET() WRITE_REG(RCC->APB5RSTR, 0UL) 2604 2605 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST) 2606 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_LTDCRST) 2607 2608 #define __HAL_RCC_DCMIPP_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST) 2609 #define __HAL_RCC_DCMIPP_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_DCMIPPRST) 2610 2611 #define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST) 2612 #define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB5RSTR, RCC_APB5RSTR_GFXTIMRST) 2613 2614 /** 2615 * @} 2616 */ 2617 2618 2619 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2620 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2621 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2622 * power consumption. 2623 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2624 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2625 * @{ 2626 */ 2627 2628 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 2629 2630 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) 2631 #if defined(ETH) 2632 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) 2633 2634 #define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) 2635 2636 #define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) 2637 #endif /* ETH */ 2638 2639 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) 2640 2641 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) 2642 2643 #define __HAL_RCC_USBPHYC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) 2644 2645 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) 2646 2647 2648 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 2649 2650 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) 2651 2652 #if defined(ETH) 2653 #define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) 2654 2655 #define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) 2656 2657 #define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) 2658 #endif /* ETH */ 2659 2660 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) 2661 2662 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) 2663 2664 #define __HAL_RCC_USBPHYC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) 2665 2666 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) 2667 2668 /** 2669 * @} 2670 */ 2671 2672 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2673 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2675 * power consumption. 2676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2677 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2678 * @{ 2679 */ 2680 2681 #define __HAL_RCC_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) 2682 2683 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) 2684 2685 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) 2686 2687 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) 2688 2689 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 2690 2691 2692 #define __HAL_RCC_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) 2693 2694 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) 2695 2696 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) 2697 2698 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) 2699 2700 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 2701 2702 /** 2703 * @} 2704 */ 2705 2706 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2707 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2708 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2709 * power consumption. 2710 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2711 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2712 * @{ 2713 */ 2714 2715 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) 2716 2717 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) 2718 2719 #if defined(CRYP) 2720 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) 2721 #endif /* CRYP */ 2722 2723 #if defined(SAES) 2724 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) 2725 #endif /* SAES */ 2726 2727 #if defined(PKA) 2728 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) 2729 #endif /* PKA */ 2730 2731 2732 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) 2733 2734 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) 2735 2736 #if defined(CRYP) 2737 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) 2738 #endif /* CRYP */ 2739 2740 #if defined(SAES) 2741 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) 2742 #endif /* SAES */ 2743 2744 #if defined(PKA) 2745 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) 2746 #endif /* PKA */ 2747 2748 /** 2749 * @} 2750 */ 2751 2752 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable 2753 * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 2754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2755 * power consumption. 2756 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2757 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2758 * @{ 2759 */ 2760 2761 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) 2762 2763 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) 2764 2765 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) 2766 2767 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) 2768 2769 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) 2770 2771 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) 2772 2773 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) 2774 2775 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) 2776 2777 #define __HAL_RCC_GPIOM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) 2778 2779 #define __HAL_RCC_GPION_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) 2780 2781 #define __HAL_RCC_GPIOO_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) 2782 2783 #define __HAL_RCC_GPIOP_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) 2784 2785 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) 2786 2787 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) 2788 2789 2790 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) 2791 2792 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) 2793 2794 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) 2795 2796 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) 2797 2798 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) 2799 2800 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) 2801 2802 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) 2803 2804 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) 2805 2806 #define __HAL_RCC_GPIOM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) 2807 2808 #define __HAL_RCC_GPION_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) 2809 2810 #define __HAL_RCC_GPIOO_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) 2811 2812 #define __HAL_RCC_GPIOP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) 2813 2814 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) 2815 2816 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) 2817 2818 /** 2819 * @} 2820 */ 2821 2822 /** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5 Peripheral Clock Sleep Enable Disable 2823 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2824 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2825 * power consumption. 2826 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2827 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2828 * @{ 2829 */ 2830 2831 #define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) 2832 2833 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) 2834 2835 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) 2836 2837 #if defined(JPEG) 2838 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) 2839 #endif /* JPEG */ 2840 2841 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) 2842 2843 #define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) 2844 2845 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) 2846 2847 #define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) 2848 2849 #define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) 2850 2851 #if defined(GFXMMU) 2852 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) 2853 #endif /* GFXMMU */ 2854 2855 #if defined(GPU2D) 2856 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) 2857 #endif /* GPU2D */ 2858 2859 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) 2860 2861 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) 2862 2863 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) 2864 2865 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) 2866 2867 2868 #define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) 2869 2870 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) 2871 2872 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) 2873 2874 #if defined(JPEG) 2875 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) 2876 #endif /* JPEG */ 2877 2878 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) 2879 2880 #define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) 2881 2882 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) 2883 2884 #define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) 2885 2886 #define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) 2887 2888 #if defined(GFXMMU) 2889 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) 2890 #endif /* GFXMMU */ 2891 2892 #if defined(GPU2D) 2893 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) 2894 #endif /* GPU2D */ 2895 2896 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) 2897 2898 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) 2899 2900 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) 2901 2902 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) 2903 2904 /** 2905 * @} 2906 */ 2907 2908 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2909 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2910 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2911 * power consumption. 2912 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2913 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2914 * @{ 2915 */ 2916 2917 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) 2918 2919 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) 2920 2921 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) 2922 2923 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) 2924 2925 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) 2926 2927 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) 2928 2929 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) 2930 2931 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) 2932 2933 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) 2934 2935 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) 2936 2937 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) 2938 2939 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) 2940 2941 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) 2942 2943 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) 2944 2945 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) 2946 2947 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) 2948 2949 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) 2950 2951 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) 2952 2953 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) 2954 2955 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) 2956 2957 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) 2958 2959 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) 2960 2961 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) 2962 2963 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) 2964 2965 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) 2966 2967 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) 2968 2969 #define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) 2970 2971 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) 2972 2973 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) 2974 2975 2976 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) 2977 2978 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) 2979 2980 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) 2981 2982 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) 2983 2984 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) 2985 2986 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) 2987 2988 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) 2989 2990 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) 2991 2992 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) 2993 2994 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) 2995 2996 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) 2997 2998 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) 2999 3000 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) 3001 3002 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) 3003 3004 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) 3005 3006 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) 3007 3008 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) 3009 3010 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) 3011 3012 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) 3013 3014 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) 3015 3016 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) 3017 3018 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) 3019 3020 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) 3021 3022 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) 3023 3024 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) 3025 3026 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) 3027 3028 #define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) 3029 3030 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) 3031 3032 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) 3033 3034 /** 3035 * @} 3036 */ 3037 3038 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3039 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3040 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3041 * power consumption. 3042 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3043 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3044 * @{ 3045 */ 3046 3047 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3048 3049 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3050 3051 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3052 3053 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3054 3055 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3056 3057 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3058 3059 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3060 3061 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) 3062 3063 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) 3064 3065 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3066 3067 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3068 3069 3070 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3071 3072 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3073 3074 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3075 3076 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3077 3078 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3079 3080 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3081 3082 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3083 3084 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) 3085 3086 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) 3087 3088 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3089 3090 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3091 3092 /** 3093 * @} 3094 */ 3095 3096 /** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable APB4 Peripheral Clock Sleep Enable Disable 3097 * @brief Enable or disable the APB4 peripheral clock during Low Power (Sleep) mode. 3098 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3099 * power consumption. 3100 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3101 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3102 * @{ 3103 */ 3104 3105 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) 3106 3107 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) 3108 3109 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) 3110 3111 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) 3112 3113 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) 3114 3115 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) 3116 3117 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) 3118 3119 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) 3120 3121 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) 3122 3123 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) 3124 3125 3126 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) 3127 3128 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) 3129 3130 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) 3131 3132 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) 3133 3134 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) 3135 3136 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) 3137 3138 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) 3139 3140 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) 3141 3142 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) 3143 3144 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) 3145 3146 /** 3147 * @} 3148 */ 3149 3150 /** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable APB5 Peripheral Clock Sleep Enable Disable 3151 * @brief Enable or disable the APB5 peripheral clock during Low Power (Sleep) mode. 3152 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3153 * power consumption. 3154 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3155 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3156 * @{ 3157 */ 3158 3159 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) 3160 3161 #define __HAL_RCC_DCMIPP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) 3162 3163 #define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) 3164 3165 3166 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) 3167 3168 #define __HAL_RCC_DCMIPP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) 3169 3170 #define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) 3171 3172 /** 3173 * @} 3174 */ 3175 3176 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 3177 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3178 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3179 * power consumption. 3180 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3181 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3182 * @{ 3183 */ 3184 3185 #define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) != 0U) 3186 3187 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADC12LPEN) != 0U) 3188 #if defined(ETH) 3189 #define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN) != 0U) 3190 3191 #define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN) != 0U) 3192 3193 #define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN) != 0U) 3194 #endif /* ETH */ 3195 3196 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGHSLPEN) != 0U) 3197 3198 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_OTGFSLPEN) != 0U) 3199 3200 #define __HAL_RCC_USBPHYC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USBPHYCLPEN) != 0U) 3201 3202 #define __HAL_RCC_ADF1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ADF1LPEN) != 0U) 3203 /** 3204 * @} 3205 */ 3206 3207 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 3208 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3209 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3210 * power consumption. 3211 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3212 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3213 * @{ 3214 */ 3215 3216 #define __HAL_RCC_PSSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PSSILPEN) != 0U) 3217 3218 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN) != 0U) 3219 3220 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_CORDICLPEN) != 0U) 3221 3222 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM1LPEN) != 0U) 3223 3224 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) != 0U) 3225 3226 /** 3227 * @} 3228 */ 3229 3230 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 3231 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 3232 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3233 * power consumption. 3234 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3235 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3236 * @{ 3237 */ 3238 3239 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_RNGLPEN) != 0U) 3240 3241 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_HASHLPEN) != 0U) 3242 3243 #if defined(CRYP) 3244 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_CRYPLPEN) != 0U) 3245 #endif /* CRYP */ 3246 3247 #if defined(SAES) 3248 #define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_SAESLPEN) != 0U) 3249 #endif /* SAES */ 3250 3251 #if defined(PKA) 3252 #define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3LPENR, RCC_AHB3LPENR_PKALPEN) != 0U) 3253 #endif /* PKA */ 3254 3255 /** 3256 * @} 3257 */ 3258 3259 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable_Status AHB4 Peripheral Clock Sleep Enabled or Disabled Status 3260 * @brief Check whether the AHB4 peripheral clock during Low Power (Sleep) mode is enabled or not. 3261 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3262 * power consumption. 3263 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3264 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3265 * @{ 3266 */ 3267 3268 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOALPEN) != 0U) 3269 3270 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOBLPEN) != 0U) 3271 3272 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOCLPEN) != 0U) 3273 3274 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIODLPEN) != 0U) 3275 3276 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOELPEN) != 0U) 3277 3278 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOFLPEN) != 0U) 3279 3280 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOGLPEN) != 0U) 3281 3282 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOHLPEN) != 0U) 3283 3284 #define __HAL_RCC_GPIOM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOMLPEN) != 0U) 3285 3286 #define __HAL_RCC_GPION_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIONLPEN) != 0U) 3287 3288 #define __HAL_RCC_GPIOO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOOLPEN) != 0U) 3289 3290 #define __HAL_RCC_GPIOP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_GPIOPLPEN) != 0U) 3291 3292 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_CRCLPEN) != 0U) 3293 3294 #define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_BKPRAMLPEN) != 0U) 3295 3296 /** 3297 * @} 3298 */ 3299 3300 /** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable_Status AHB5 Peripheral Clock Sleep Enabled or Disabled Status 3301 * @brief Check whether the AHB5 peripheral clock during Low Power (Sleep) mode is enabled or not. 3302 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3303 * power consumption. 3304 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3305 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3306 * @{ 3307 */ 3308 3309 #define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN) != 0U) 3310 3311 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN) != 0U) 3312 3313 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN) != 0U) 3314 3315 #if defined(JPEG) 3316 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) != 0U) 3317 #endif /* JPEG */ 3318 3319 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) != 0U) 3320 3321 #define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN) != 0U) 3322 3323 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN) != 0U) 3324 3325 #define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN) != 0U) 3326 3327 #define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) != 0U) 3328 3329 #if defined(GFXMMU) 3330 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN) != 0U) 3331 #endif /* GFXMMU */ 3332 3333 #if defined(GPU2D) 3334 #define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN) != 0U) 3335 #endif /* GPU2D */ 3336 3337 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN) != 0U) 3338 3339 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN) != 0U) 3340 3341 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) != 0U) 3342 3343 #define __HAL_RCC_AXISRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN) != 0U) 3344 3345 /** 3346 * @} 3347 */ 3348 3349 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 3350 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 3351 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3352 * power consumption. 3353 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3354 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3355 * @{ 3356 */ 3357 3358 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM2LPEN) != 0U) 3359 3360 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM3LPEN) != 0U) 3361 3362 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM4LPEN) != 0U) 3363 3364 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM5LPEN) != 0U) 3365 3366 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM6LPEN) != 0U) 3367 3368 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM7LPEN) != 0U) 3369 3370 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM12LPEN) != 0U) 3371 3372 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM13LPEN) != 0U) 3373 3374 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_TIM14LPEN) != 0U) 3375 3376 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_LPTIM1LPEN) != 0U) 3377 3378 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_WWDGLPEN) != 0U) 3379 3380 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI2LPEN) != 0U) 3381 3382 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPI3LPEN) != 0U) 3383 3384 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_SPDIFRXLPEN) != 0U) 3385 3386 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART2LPEN) != 0U) 3387 3388 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_USART3LPEN) != 0U) 3389 3390 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART4LPEN) != 0U) 3391 3392 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART5LPEN) != 0U) 3393 3394 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) != 0U) 3395 3396 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C2LPEN) != 0U) 3397 3398 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C3LPEN) != 0U) 3399 3400 #define __HAL_RCC_I3C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_I2C1_I3C1LPEN) != 0U) 3401 3402 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_CECLPEN) != 0U) 3403 3404 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART7LPEN) != 0U) 3405 3406 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR1, RCC_APB1LPENR1_UART8LPEN) != 0U) 3407 3408 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_CRSLPEN) != 0U) 3409 3410 #define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_MDIOSLPEN) != 0U) 3411 3412 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_FDCANLPEN) != 0U) 3413 3414 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1LPENR2, RCC_APB1LPENR2_UCPD1LPEN) != 0U) 3415 3416 /** 3417 * @} 3418 */ 3419 3420 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 3421 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 3422 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3423 * power consumption. 3424 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3425 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3426 * @{ 3427 */ 3428 3429 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) != 0U) 3430 3431 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) != 0U) 3432 3433 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) != 0U) 3434 3435 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) != 0U) 3436 3437 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) != 0U) 3438 3439 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) != 0U) 3440 3441 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) != 0U) 3442 3443 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM9LPEN) != 0U) 3444 3445 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN) != 0U) 3446 3447 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) != 0U) 3448 3449 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) != 0U) 3450 3451 /** 3452 * @} 3453 */ 3454 3455 /** @defgroup RCC_APB4_Clock_Sleep_Enable_Disable_Status APB4 Peripheral Clock Sleep Enabled or Disabled Status 3456 * @brief Check whether the APB4 peripheral clock during Low Power (Sleep) mode is enabled or not. 3457 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3458 * power consumption. 3459 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3460 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3461 * @{ 3462 */ 3463 3464 #define __HAL_RCC_SBS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SBSLPEN) != 0U) 3465 3466 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPUART1LPEN) != 0U) 3467 3468 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN) != 0U) 3469 3470 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM2LPEN) != 0U) 3471 3472 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM3LPEN) != 0U) 3473 3474 #define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM4LPEN) != 0U) 3475 3476 #define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_LPTIM5LPEN) != 0U) 3477 3478 #define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_VREFLPEN) != 0U) 3479 3480 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_RTCAPBLPEN) != 0U) 3481 3482 #define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB4LPENR, RCC_APB4LPENR_DTSLPEN) != 0U) 3483 3484 /** 3485 * @} 3486 */ 3487 3488 /** @defgroup RCC_APB5_Clock_Sleep_Enable_Disable_Status APB5 Peripheral Clock Sleep Enabled or Disabled Status 3489 * @brief Check whether the APB5 peripheral clock during Low Power (Sleep) mode is enabled or not. 3490 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 3491 * power consumption. 3492 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3493 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3494 * @{ 3495 */ 3496 3497 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_LTDCLPEN) != 0U) 3498 3499 #define __HAL_RCC_DCMIPP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_DCMIPPLPEN) != 0U) 3500 3501 #define __HAL_RCC_GFXTIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB5LPENR, RCC_APB5LPENR_GFXTIMLPEN) != 0U) 3502 3503 /** 3504 * @} 3505 */ 3506 3507 /** @defgroup RCC_Osc_config Oscillators configuration 3508 * @{ 3509 */ 3510 3511 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). 3512 * @note After enabling the HSI, the application software should wait on 3513 * HSIRDY and HSIDIVF flags to be set indicating that the HSI clock is 3514 * stable and the divider ready and that HSI clock can be used to clock 3515 * the PLL and/or system clock. 3516 * @note HSI can not be stopped if it is used directly or through the PLL 3517 * as system clock. In this case, you have to select another source 3518 * of the system clock then stop the HSI. 3519 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3520 * @param __STATE__ specifies the new state of the HSI. 3521 * This parameter can be one of the following values: 3522 * @arg @ref RCC_HSI_OFF turn OFF the HSI oscillator 3523 * @arg @ref RCC_HSI_ON turn ON the HSI oscillator (divide it by 1 (default after reset)) 3524 * @arg @ref RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 3525 * @arg @ref RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 3526 * @arg @ref RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 3527 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3528 * clock cycles. 3529 */ 3530 #define __HAL_RCC_HSI_CONFIG(__STATE__) \ 3531 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) 3532 3533 /** @brief Macro to get the HSI divider. 3534 * @retval The HSI divider. The returned value can be one 3535 * of the following: 3536 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) 3537 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 3538 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 3539 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 3540 */ 3541 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 3542 3543 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 3544 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3545 * It is used (enabled by hardware) as system clock source after start-up 3546 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3547 * of the HSE used directly or indirectly as system clock (if the Clock 3548 * Security System CSS is enabled). 3549 * @note HSI can not be stopped if it is used as system clock source. In this case, 3550 * you have to select another source of the system clock then stop the HSI. 3551 * @note After enabling the HSI, the application software should wait on HSIRDY 3552 * flag to be set indicating that HSI clock is stable and can be used as 3553 * system clock source. 3554 * This parameter can be: ENABLE or DISABLE. 3555 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3556 * clock cycles. 3557 */ 3558 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3559 3560 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3561 3562 /** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. 3563 * @note The calibration is used to compensate for the variations in voltage 3564 * and temperature that influence the frequency of the internal HSI RC. 3565 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 3566 * (default is RCC_HSICALIBRATION_DEFAULT). 3567 * This parameter must be a number between 0 and 0x7F. 3568 * @retval None 3569 */ 3570 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3571 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos); 3572 3573 /** 3574 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3575 * in STOP mode to be quickly available as kernel clock for some peripherals. 3576 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3577 * speed because of the HSI start-up time. 3578 * @note The enable of this function has not effect on the HSION bit. 3579 * This parameter can be: ENABLE or DISABLE. 3580 * @retval None 3581 */ 3582 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3583 3584 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3585 3586 /** 3587 * @brief Macros to enable or disable the Internal oscillator (CSI). 3588 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 3589 * It is used (enabled by hardware) as system clock source after 3590 * start-up from Reset, wakeup from STOP and STANDBY mode, or in case 3591 * of failure of the HSE used directly or indirectly as system clock 3592 * (if the Clock Security System CSS is enabled). 3593 * @note CSI can not be stopped if it is used as system clock source. 3594 * In this case, you have to select another source of the system 3595 * clock then stop the CSI. 3596 * @note After enabling the CSI, the application software should wait on 3597 * CSIRDY flag to be set indicating that CSI clock is stable and can 3598 * be used as system clock source. 3599 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 3600 * clock cycles. 3601 */ 3602 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 3603 3604 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 3605 3606 /** @brief Macro to adjust the Internal oscillator (CSI) calibration value. 3607 * @note The calibration is used to compensate for the variations in voltage 3608 * and temperature that influence the frequency of the internal CSI RC. 3609 * @param __CSICALIBRATIONVALUE__ specifies the calibration trimming value 3610 * (default is RCC_CSICALIBRATION_DEFAULT). 3611 * This parameter must be a number between 0 and 0x3F. 3612 * @retval None 3613 */ 3614 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICALIBRATIONVALUE__) \ 3615 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICALIBRATIONVALUE__) << RCC_CSICFGR_CSITRIM_Pos); 3616 3617 /** 3618 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 3619 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 3620 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 3621 * speed because of the CSI start-up time. 3622 * @note The enable of this function has not effect on the CSION bit. 3623 * This parameter can be: ENABLE or DISABLE. 3624 * @retval None 3625 */ 3626 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 3627 3628 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 3629 3630 /** 3631 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). 3632 * @note After enabling the HSI48, the application software should wait on 3633 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can 3634 * be used to clock the USB. 3635 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 3636 */ 3637 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); 3638 3639 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); 3640 3641 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 3642 * @note After enabling the LSI, the application software should wait on 3643 * LSIRDY flag to be set indicating that LSI clock is stable and can 3644 * be used to clock the IWDG and/or the RTC. 3645 * @note LSI can not be disabled if the IWDG is running. 3646 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 3647 * clock cycles. 3648 */ 3649 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 3650 3651 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 3652 3653 /** 3654 * @brief Macro to configure the External High Speed oscillator (__HSE__). 3655 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 3656 * software should wait on HSERDY flag to be set indicating that HSE clock 3657 * is stable and can be used to clock the PLL and/or system clock. 3658 * @note HSE state can not be changed if it is used directly or through the 3659 * PLL as system clock. In this case, you have to select another source 3660 * of the system clock then change the HSE state (ex. disable it). 3661 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 3662 * @note This function reset the CSSON bit, so if the clock security system(CSS) 3663 * was previously enabled you have to enable it again after calling this 3664 * function. 3665 * @param __STATE__ specifies the new state of the HSE. 3666 * This parameter can be one of the following values: 3667 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 3668 * 6 HSE oscillator clock cycles. 3669 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator. 3670 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock (analog). 3671 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with external digital clock. 3672 */ 3673 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 3674 do { \ 3675 if ((__STATE__) == RCC_HSE_ON) \ 3676 { \ 3677 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3678 } \ 3679 else if ((__STATE__) == RCC_HSE_OFF) \ 3680 { \ 3681 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 3682 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3683 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3684 } \ 3685 else if ((__STATE__) == RCC_HSE_BYPASS) \ 3686 { \ 3687 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3688 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3689 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3690 } \ 3691 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 3692 { \ 3693 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3694 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3695 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 3696 } \ 3697 else \ 3698 { \ 3699 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 3700 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 3701 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 3702 } \ 3703 } while(0) 3704 3705 /** 3706 * @brief Macro to configure the External Low Speed oscillator (LSE). 3707 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 3708 * User should request a transition to LSE Off first and then LSE On or LSE Bypass. 3709 * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). 3710 A duty cycle close to 50% is recommended. 3711 * @note As the LSE is in the Backup domain and write access is denied to 3712 * this domain after reset, you have to enable write access using 3713 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3714 * (to be done once after reset). 3715 * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL), the application 3716 * software should wait on LSERDY flag to be set indicating that LSE clock 3717 * is stable and can be used to clock the RTC. 3718 * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) 3719 * @param __STATE__ specifies the new state of the LSE. 3720 * This parameter can be one of the following values: 3721 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 3722 * 6 LSE oscillator clock cycles. 3723 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 3724 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock (analog). 3725 * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. 3726 */ 3727 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 3728 do { \ 3729 if((__STATE__) == RCC_LSE_ON) \ 3730 { \ 3731 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3732 } \ 3733 else if((__STATE__) == RCC_LSE_OFF) \ 3734 { \ 3735 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3736 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 3737 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3738 } \ 3739 else if((__STATE__) == RCC_LSE_BYPASS) \ 3740 { \ 3741 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3742 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 3743 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3744 } \ 3745 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 3746 { \ 3747 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3748 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 3749 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3750 } \ 3751 else \ 3752 { \ 3753 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 3754 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 3755 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 3756 } \ 3757 } while(0) 3758 3759 /** 3760 * @} 3761 */ 3762 3763 /** @defgroup RCC_RTC_Clock_config RCC_RTC_Clock_config 3764 * @{ 3765 */ 3766 3767 /** @brief Macros to enable or disable the the RTC clock. 3768 * @note These macros must be used only after the RTC clock source was selected. 3769 */ 3770 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3771 3772 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3773 3774 /** @brief Macros to configure the RTC clock (RTCCLK). 3775 * @note As the RTC clock configuration bits are in the Backup domain and write 3776 * access is denied to this domain after reset, you have to enable write 3777 * access using the Power Backup Access macro before to configure 3778 * the RTC clock source (to be done once after reset). 3779 * @note Once the RTC clock is configured it cannot be changed unless the 3780 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() and 3781 * __HAL_RCC_BACKUPRESET_RELEASE() macros, or by a Power On Reset (POR). 3782 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 3783 * This parameter can be one of the following values: 3784 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3785 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3786 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divide by 2 selected as RTC clock up to 3787 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV63 for HSE divide by 63 3788 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 3789 * work in STOP and STANDBY modes, and can be used as wakeup source. 3790 * However, when the HSE clock is used as RTC clock source, the RTC 3791 * cannot be used in STOP and STANDBY modes. 3792 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 3793 * RTC clock source). 3794 */ 3795 #define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) \ 3796 ((((__RTC_CLKSOURCE__) & (0x3FU << 12U)) != 0U) ? \ 3797 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTC_CLKSOURCE__) & (~RCC_BDCR_RTCSEL)) >> 4U)) : \ 3798 CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)) 3799 3800 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 3801 do { \ 3802 __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ 3803 SET_BIT(RCC->BDCR, ((__RTC_CLKSOURCE__) & RCC_BDCR_RTCSEL)); \ 3804 } while(0) 3805 3806 #define __HAL_RCC_GET_RTC_SOURCE() \ 3807 ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 3808 ((READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) << 4U) | RCC_BDCR_RTCSEL) : READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 3809 3810 /** @brief Macros to force or release the Vswitch backup domain reset. 3811 * @note This function resets the RTC peripheral (including the backup registers) 3812 * and the RTC clock source selection in RCC_BDCR register. 3813 * @note The BKPSRAM is not affected by this reset. 3814 */ 3815 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3816 3817 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 3818 3819 /** 3820 * @} 3821 */ 3822 3823 /** @defgroup RCC_PLL_Clocks_config PLL Clocks configuration 3824 * @{ 3825 */ 3826 3827 /** @brief Macro to configure the PLLs clock source. 3828 * @note This function must be used only when all PLLs are disabled. 3829 * @param __PLLSOURCE__ specifies the PLLs entry clock source. 3830 * This parameter can be one of the following values: 3831 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3832 * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator clock selected as PLL clock entry 3833 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3834 * @arg @ref RCC_PLLSOURCE_NONE No oscillator clock selected as PLL clock entry (consumption gain) 3835 */ 3836 #define __HAL_RCC_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 3837 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) 3838 3839 /** @brief Macro to get the oscillator used as PLL clock source. 3840 * @retval The oscillator used as PLL clock source. 3841 * The returned value can be one of the following values: 3842 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3843 * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator is used as PLL clock source. 3844 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3845 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 3846 */ 3847 #define __HAL_RCC_GET_PLL_OSCSOURCE() \ 3848 READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC) 3849 3850 /** @brief Macros to enable or disable the PLL1. 3851 * @note After enabling the main PLL, the application software should wait on 3852 * PLL1RDY flag to be set indicating that PLL1 clock is stable and can 3853 * be used as system clock source. 3854 * @note The main PLL can not be disabled if it is used as system clock source 3855 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3856 */ 3857 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 3858 3859 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 3860 3861 /** 3862 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK, PLL_S_CLK, PLL_T_CLK) 3863 * @note PLL_P_CLK cannot be stopped if used as System Clock 3864 * @param __PLL_CLOCKOUT__ specifies the PLL clock to be output 3865 * This parameter can be one or a combination of the following values: 3866 * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz 3867 * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz 3868 * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz 3869 * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz 3870 * 3871 * @retval None 3872 */ 3873 #define __HAL_RCC_PLL1CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) 3874 3875 #define __HAL_RCC_PLL1CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) 3876 3877 /** 3878 * @brief Macro to get the PLL1 clock output enable status. 3879 * @param __PLL_CLOCKOUT__ specifies the PLL1 clock to be output. 3880 * This parameter can be one of the following values: 3881 * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz 3882 * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz 3883 * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz 3884 * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz 3885 * @retval SET / RESET 3886 */ 3887 #define __HAL_RCC_GET_PLL1CLKOUT_CONFIG(__PLL_CLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLL_CLOCKOUT__)) 3888 3889 /** 3890 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 3891 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 3892 * @retval None 3893 */ 3894 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 3895 3896 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) 3897 3898 /** 3899 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3900 * @note This function must be used only when the main PLL is disabled. 3901 * 3902 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3903 * This parameter can be one of the following values: 3904 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3905 * @arg @ref RCC_PLLSOURCE_CSI CSI oscillator clock selected as PLL clock entry 3906 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3907 * @arg @ref RCC_PLLSOURCE_NONE No oscillator clock selected as PLL clock entry (consumption gain) 3908 * @note This clock source is common for PLL1, PLL2 and PLL3. It cannot be 3909 * change on any PLL if another PLL is already enabled. 3910 * 3911 * @param __PLL1M__ specifies the division factor for PLL VCO input clock 3912 * This parameter must be a number between 1 and 63. 3913 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3914 * frequency ranges from 1 to 16 MHz. 3915 * 3916 * @param __PLL1N__ specifies the multiplication factor for PLL VCO output clock 3917 * This parameter must be a number between 8 and 420. 3918 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3919 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 3920 * between 128 and 560 MHZ (when in wide VCO range) 3921 * 3922 * @param __PLL1P__ specifies the division factor for system clock. 3923 * This parameter must be a number between 1 and 128 (where odd numbers are not allowed) 3924 * 3925 * @param __PLL1Q__ specifies the division factor for peripheral kernel clocks 3926 * This parameter must be a number between 1 and 128 3927 * 3928 * @param __PLL1R__ specifies the division factor for peripheral kernel clocks 3929 * This parameter must be a number between 1 and 128 3930 * 3931 * @param __PLL1S__ specifies the division factor for peripheral kernel clocks 3932 * This parameter must be a number between 1 and 8 3933 * 3934 * 3935 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, 3936 * DIVR, DIVS or DIVT) is not used, application shall clear the enable bit (PLL1yEN) 3937 * and assign lowest possible value to __PLL1P__, __PLL1Q__, __PLL1R__, __PLL1S__ 3938 * or __PLL1T__ parameters. 3939 * @retval None 3940 */ 3941 3942 #define __HAL_RCC_PLL1_CONFIG(__PLLSOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__, __PLL1S__) \ 3943 do { \ 3944 MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__PLLSOURCE__) | ( (__PLL1M__) << RCC_PLLCKSELR_DIVM1_Pos))); \ 3945 WRITE_REG(RCC->PLL1DIVR1, ((((__PLL1N__) - 1U) & RCC_PLL1DIVR1_DIVN) | \ 3946 ((((__PLL1P__) - 1U) << RCC_PLL1DIVR1_DIVP_Pos) & RCC_PLL1DIVR1_DIVP) | \ 3947 ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR1_DIVQ_Pos) & RCC_PLL1DIVR1_DIVQ) | \ 3948 ((((__PLL1R__) - 1U) << RCC_PLL1DIVR1_DIVR_Pos) & RCC_PLL1DIVR1_DIVR))); \ 3949 MODIFY_REG(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS, \ 3950 (((__PLL1S__) - 1U) & RCC_PLL1DIVR2_DIVS)); \ 3951 } while(0) 3952 3953 /** 3954 * @brief Macro to configures the PLL1 clock Fractional Part Of The Multiplication Factor 3955 * 3956 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 3957 * 3958 * @param __PLL1FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO. 3959 * It should be a value between 0 and 8191 3960 * @note Warning: The software has to set correctly these bits to insure that the VCO 3961 * output frequency is between its valid frequency range, which is: 3962 * 128 to 560 MHz if PLL1VCOSEL = 0 3963 * 150 to 420 MHz if PLL1VCOSEL = 1. 3964 * 3965 * @retval None 3966 */ 3967 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) \ 3968 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN, (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_FRACN_Pos) 3969 3970 /** @brief Macro to select the PLL1 reference frequency range. 3971 * @param __PLL_VCOINPUT_RANGE__ specifies the PLL1 input frequency range 3972 * This parameter can be one of the following values: 3973 * @arg @ref RCC_PLL_VCOINPUT_RANGE0 Range frequency is between 1 and 2 MHz 3974 * @arg @ref RCC_PLL_VCOINPUT_RANGE1 Range frequency is between 2 and 4 MHz 3975 * @arg @ref RCC_PLL_VCOINPUT_RANGE2 Range frequency is between 4 and 8 MHz 3976 * @arg @ref RCC_PLL_VCOINPUT_RANGE3 Range frequency is between 8 and 16 MHz 3977 * 3978 * @retval None 3979 */ 3980 #define __HAL_RCC_PLL1_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ 3981 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__PLL_VCOINPUT_RANGE__)) 3982 3983 /** @brief Macro to select the PLL1 reference frequency range. 3984 * @param __PLLVCORANGE__ specifies the PLL1 input frequency range 3985 * This parameter can be one of the following values: 3986 * @arg @ref RCC_PLL_VCO_HIGH Range frequency is between 128 to 560 MHz 3987 * @arg @ref RCC_PLL_VCO_LOW Range frequency is between 150 and 420 MHz 3988 * @retval None 3989 */ 3990 #define __HAL_RCC_PLL1_VCORANGE(__PLLVCORANGE__) \ 3991 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__PLLVCORANGE__)) 3992 3993 /** @brief Macros to enable or disable PLL2. 3994 * @note After enabling PLL2, the application software should wait on 3995 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 3996 * be used as kernel clock source. 3997 * @note PLL2 is disabled by hardware when entering Stop and Standby modes. 3998 */ 3999 #define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) 4000 #define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) 4001 4002 /** 4003 * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK, PLL2_S_CLK, PLL2_T_CLK) 4004 * @param __PLL_CLOCKOUT__ Specifies the PLL2 clock(s) to be output 4005 * This parameter can be one or a combination of the following values: 4006 * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz 4007 * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz 4008 * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz 4009 * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz 4010 * @arg @ref RCC_PLL_TCLK This clock is used to generate peripherals clock up to 500MHz 4011 * @retval None 4012 */ 4013 #define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) 4014 4015 #define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) 4016 4017 /** 4018 * @brief Macro to get the PLL2 clock output enable status. 4019 * @param __PLL_CLOCKOUT__ specifies the PLL2 clock to be output. 4020 * This parameter can be one of the following values: 4021 * @arg @ref RCC_PLL_PCLK This clock is used to generate system clock up to 500MHz 4022 * @arg @ref RCC_PLL_QCLK This clock is used to generate peripherals clock up to 500MHz 4023 * @arg @ref RCC_PLL_RCLK This clock is used to generate peripherals clock up to 500MHz 4024 * @arg @ref RCC_PLL_SCLK This clock is used to generate peripherals clock up to 500MHz 4025 * @arg @ref RCC_PLL_TCLK This clock is used to generate peripherals clock up to 500MHz 4026 * @retval SET / RESET 4027 */ 4028 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL_CLOCKOUT__) (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) \ 4029 >> (RCC_PLLCFGR_PLL2PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)) 4030 4031 /** 4032 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO 4033 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 4034 * @retval None 4035 */ 4036 #define __HAL_RCC_PLL2_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 4037 4038 #define __HAL_RCC_PLL2_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) 4039 4040 /** 4041 * @brief Macro to configures the PLL2 multiplication and division factors. 4042 * @note This function must be used only when PLL2 is disabled. 4043 * 4044 * @param __PLLSOURCE__ specifies the PLL2 clock source 4045 * This parameter must be a value of @ref RCC_PLL_Clock_Source 4046 * @note PLL2 clock source is addressing a common clock source for all PLLs. 4047 * 4048 * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock 4049 * This parameter must be a number between 1 and 63. 4050 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4051 * frequency ranges from 1 to 16 MHz. 4052 * 4053 * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock 4054 * This parameter must be a number between 4 and 512 or between 8 and 420(*). 4055 * @note You have to set the PLL2N parameter correctly to ensure that the VCO 4056 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 4057 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 4058 * 4059 * @param __PLL2P__ specifies the division factor for peripheral kernel clocks 4060 * This parameter must be a number between 1 and 128. 4061 * 4062 * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks 4063 * This parameter must be a number between 1 and 128. 4064 * 4065 * @param __PLL2R__ specifies the division factor for peripheral kernel clocks 4066 * This parameter must be a number between 1 and 128. 4067 * 4068 * @param __PLL2S__ specifies the division factor for peripheral kernel clocks 4069 * This parameter must be a number between 1 and 8. 4070 * 4071 * @param __PLL2T__ specifies the division factor for peripheral kernel clocks 4072 * This parameter must be a number between 1 and 8. 4073 * 4074 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, 4075 * DIVR, DIVS and DIVT) is not used, application shall clear the enable bit (PLL2yEN) 4076 * and assign lowest possible value to __PLL2P__, __PLL2Q__, __PLL2R__, __PLL2S__ 4077 * or __PLL2T__ parameters. 4078 * @retval None 4079 */ 4080 4081 #define __HAL_RCC_PLL2_CONFIG(__PLLSOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__, __PLL2S__, __PLL2T__) \ 4082 do{ \ 4083 MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM2 | RCC_PLLCKSELR_PLLSRC), \ 4084 (((__PLL2M__) << RCC_PLLCKSELR_DIVM2_Pos) | (__PLLSOURCE__))); \ 4085 WRITE_REG(RCC->PLL2DIVR1, ((((__PLL2N__) - 1U) & RCC_PLL2DIVR1_DIVN) | \ 4086 ((((__PLL2P__) - 1U) << RCC_PLL2DIVR1_DIVP_Pos) & RCC_PLL2DIVR1_DIVP) | \ 4087 ((((__PLL2Q__) - 1U) << RCC_PLL2DIVR1_DIVQ_Pos) & RCC_PLL2DIVR1_DIVQ) | \ 4088 ((((__PLL2R__) - 1U) << RCC_PLL2DIVR1_DIVR_Pos) & RCC_PLL2DIVR1_DIVR))); \ 4089 MODIFY_REG(RCC->PLL2DIVR2, (RCC_PLL2DIVR2_DIVS | RCC_PLL2DIVR2_DIVT) , \ 4090 ((((__PLL2S__) - 1U) & RCC_PLL2DIVR2_DIVS) | \ 4091 ((((__PLL2T__) - 1U) << RCC_PLL2DIVR2_DIVT_Pos) & RCC_PLL2DIVR2_DIVT))); \ 4092 } while(0) 4093 4094 /** 4095 * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor 4096 * 4097 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO 4098 * 4099 * @param __PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO 4100 * It should be a value between 0 and 8191 4101 * @note Warning: the software has to set correctly these bits to insure that the VCO 4102 * output frequency is between its valid frequency range, which is: 4103 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 4104 * 150 to 420 MHz if PLL2VCOSEL = 1. 4105 * 4106 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 4107 * 4108 * @retval None 4109 */ 4110 #define __HAL_RCC_PLL2_FRACN_CONFIG(__PLL2FRACN__) \ 4111 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN,((uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_FRACN_Pos)) 4112 4113 /** @brief Macro to select the PLL2 reference frequency range. 4114 * @param __PLL_VCOINPUT_RANGE__ specifies the PLL2 input frequency range 4115 * This parameter can be one of the following values: 4116 * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 1 and 2 MHz 4117 * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 2 and 4 MHz 4118 * @arg RCC_PLL_VCOINPUT_RANGE2: Range frequency is between 4 and 8 MHz 4119 * @arg RCC_PLL_VCOINPUT_RANGE3: Range frequency is between 8 and 16 MHz 4120 * @retval None 4121 */ 4122 #define __HAL_RCC_PLL2_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ 4123 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL2RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos))) 4124 4125 4126 /** @brief Macro to select the PLL2 reference frequency range. 4127 * @param __PLLVCORANGE__ Specifies the PLL2 input frequency range 4128 * This parameter can be one of the following values: 4129 * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 4130 * @arg RCC_PLL_VCO_LOW: Range frequency is between 150 and 420 MHz 4131 * 4132 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 4133 * 4134 * @retval None 4135 */ 4136 #define __HAL_RCC_PLL2_VCORANGE(__PLLVCORANGE__) \ 4137 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL2VCOSEL_Pos - RCC_PLLCFGR_PLL1VCOSEL_Pos))) 4138 4139 /** @brief Macros to enable or disable the main PLL3. 4140 * @note After enabling PLL3, the application software should wait on 4141 * PLL3RDY flag to be set indicating that PLL3 clock is stable and can 4142 * be used as kernel clock source. 4143 * @note PLL3 is disabled by hardware when entering Stop and Standby modes. 4144 */ 4145 #define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) 4146 #define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) 4147 4148 /** 4149 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO 4150 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 4151 * @retval None 4152 */ 4153 #define __HAL_RCC_PLL3_FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 4154 4155 #define __HAL_RCC_PLL3_FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) 4156 4157 /** 4158 * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK, PLL3_S_CLK, PLL3_T_CLK) 4159 * @param __PLL_CLOCKOUT__ Specifies the PLL3 clock(s) to be output 4160 * This parameter can be one or a combination of the following values: 4161 * @arg RCC_PLL_PCLK 4162 * @arg RCC_PLL_QCLK 4163 * @arg RCC_PLL_RCLK 4164 * @arg RCC_PLL_SCLK 4165 * @retval SET / RESET 4166 */ 4167 #define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL_CLOCKOUT__) SET_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) 4168 4169 #define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL_CLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) 4170 4171 /** 4172 * @brief Macro to get the PLL3 clock output enable status. 4173 * @param __PLL_CLOCKOUT__ specifies the PLL3 clock(s) to be output. 4174 * This parameter can be one of the following values: 4175 * @arg RCC_PLL_PCLK 4176 * @arg RCC_PLL_QCLK 4177 * @arg RCC_PLL_RCLK 4178 * @arg RCC_PLL_SCLK 4179 * @retval SET / RESET 4180 */ 4181 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL_CLOCKOUT__) (READ_BIT(RCC->PLLCFGR, ((__PLL_CLOCKOUT__) << (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos))) \ 4182 >> (RCC_PLLCFGR_PLL3PEN_Pos - RCC_PLLCFGR_PLL1PEN_Pos)) 4183 4184 /** 4185 * @brief Macro to configures the PLL3 multiplication and division factors. 4186 * @note This function must be used only when PLL3 is disabled. 4187 * 4188 * @param __PLLSOURCE__ specifies the PLL3 clock source 4189 * This parameter must be a value of @ref RCC_PLL_Clock_Source 4190 * @note PLL3 clock source is addressing a common clock source for all PLLs. 4191 * 4192 * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock 4193 * This parameter must be a number between 1 and 63. 4194 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4195 * frequency ranges from 1 to 16 MHz. 4196 * 4197 * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock 4198 * This parameter must be a number between 4 and 512. 4199 * @note You have to set the PLL3N parameter correctly to ensure that the VCO 4200 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 4201 * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) 4202 * 4203 * @param __PLL3P__ specifies the division factor for peripheral kernel clocks 4204 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 4205 * 4206 * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks 4207 * This parameter must be a number between 1 and 128 4208 * 4209 * @param __PLL3R__ specifies the division factor for peripheral kernel clocks 4210 * This parameter must be a number between 1 and 128 4211 * 4212 * @param __PLL3S__ specifies the division factor for peripheral kernel clocks 4213 * This parameter must be a number between 1 and 8. 4214 * 4215 * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ, 4216 * DIVR, DIVS and DIVT) is not used, application shall clear the enable bit (PLL3yEN) 4217 * and assign lowest possible value to __PLL3P__, __PLL3Q__, __PLL3R__, __PLL3S__ 4218 * or __PLL3T__ parameters. 4219 */ 4220 4221 #define __HAL_RCC_PLL3_CONFIG(__PLLSOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__, __PLL3S__) \ 4222 do{ \ 4223 MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM3 | RCC_PLLCKSELR_PLLSRC), \ 4224 (((__PLL3M__) << RCC_PLLCKSELR_DIVM3_Pos) | (__PLLSOURCE__))); \ 4225 WRITE_REG(RCC->PLL3DIVR1, ((((__PLL3N__) - 1U) & RCC_PLL3DIVR1_DIVN) | \ 4226 ((((__PLL3P__) - 1U) << RCC_PLL3DIVR1_DIVP_Pos) & RCC_PLL3DIVR1_DIVP) | \ 4227 ((((__PLL3Q__) - 1U) << RCC_PLL3DIVR1_DIVQ_Pos) & RCC_PLL3DIVR1_DIVQ) | \ 4228 ((((__PLL3R__) - 1U) << RCC_PLL3DIVR1_DIVR_Pos) & RCC_PLL3DIVR1_DIVR))); \ 4229 MODIFY_REG(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS, \ 4230 (((__PLL3S__) - 1U) & RCC_PLL3DIVR2_DIVS)); \ 4231 } while(0) 4232 4233 /** 4234 * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor 4235 * 4236 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO 4237 * 4238 * @param __PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO 4239 * It should be a value between 0 and 8191 4240 * @note Warning: the software has to set correctly these bits to insure that the VCO 4241 * output frequency is between its valid frequency range, which is: 4242 * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 4243 * 150 to 420 MHz if PLL3VCOSEL = 1. 4244 * 4245 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 4246 * 4247 * @retval None 4248 */ 4249 #define __HAL_RCC_PLL3_FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN, (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_FRACN_Pos) 4250 4251 /** @brief Macro to select the PLL3 reference frequency range. 4252 * @param __PLL_VCOINPUT_RANGE__ specifies the PLL1 input frequency range 4253 * This parameter can be one of the following values: 4254 * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 1 and 2 MHz 4255 * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 2 and 4 MHz 4256 * @arg RCC_PLL_VCOINPUT_RANGE2: Range frequency is between 4 and 8 MHz 4257 * @arg RCC_PLL_VCOINPUT_RANGE3: Range frequency is between 8 and 16 MHz 4258 * @retval None 4259 */ 4260 #define __HAL_RCC_PLL3_VCOINPUT_RANGE(__PLL_VCOINPUT_RANGE__) \ 4261 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, ((__PLL_VCOINPUT_RANGE__) << (RCC_PLLCFGR_PLL3RGE_Pos - RCC_PLLCFGR_PLL1RGE_Pos))) 4262 4263 /** @brief Macro to select the PLL3 reference frequency range. 4264 * @param __PLLVCORANGE__ specifies the PLL1 input frequency range 4265 * This parameter can be one of the following values: 4266 * @arg RCC_PLL_VCO_HIGH: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) 4267 * @arg RCC_PLL_VCO_HIGH: Range frequency is between 150 and 420 MHz 4268 * 4269 * (*) : For stm32h7a3xx and stm32h7b3xx family lines. 4270 * 4271 * @retval None 4272 */ 4273 #define __HAL_RCC_PLL3_VCORANGE(__PLLVCORANGE__) \ 4274 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, ((__PLLVCORANGE__) << (RCC_PLLCFGR_PLL3VCOSEL_Pos - RCC_PLLCFGR_PLL1VCOSEL_Pos))) 4275 4276 /** 4277 * @} 4278 */ 4279 4280 /** @defgroup RCC_sysclk_config System clock source configuration 4281 * @{ 4282 */ 4283 4284 /** 4285 * @brief Macro to configure the system clock source. 4286 * @param __SYSCLKSOURCE__ specifies the system clock source. 4287 * This parameter can be one of the following values: 4288 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 4289 * @arg @ref RCC_SYSCLKSOURCE_CSI CSI oscillator is used as system clock source. 4290 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 4291 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL1 output is used as system clock source. 4292 * @retval None 4293 */ 4294 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4295 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 4296 4297 /** @brief Macro to get the clock source used as system clock. 4298 * @retval The clock source used as system clock. 4299 * The returned value can be one of the following values: 4300 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 4301 * @arg @ref RCC_SYSCLKSOURCE_STATUS_CSI CSI used as system clock. 4302 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 4303 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL1 used as system clock. 4304 */ 4305 #define __HAL_RCC_GET_SYSCLK_SOURCE() \ 4306 READ_BIT(RCC->CFGR, RCC_CFGR_SWS) 4307 4308 /** 4309 * @} 4310 */ 4311 4312 /** @addtogroup RCC_Osc_config 4313 * @{ 4314 */ 4315 4316 /** 4317 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4318 * @note As the LSE is in the Backup domain and write access is denied to 4319 * this domain after reset, you have to enable write access using 4320 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4321 * (to be done once after reset). 4322 * @note This parameter cannot be updated while LSE is ON. 4323 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 4324 * This parameter can be one of the following values: 4325 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4326 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4327 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4328 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4329 * @retval None 4330 */ 4331 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4332 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); 4333 /** 4334 * @} 4335 */ 4336 4337 /** @defgroup RCC_wkup_config Wakeup from stop configuration 4338 * @{ 4339 */ 4340 4341 /** 4342 * @brief Macro to configure the wake up from stop clock. 4343 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop 4344 * This parameter can be one of the following values: 4345 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4346 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source 4347 * @retval None 4348 */ 4349 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4350 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 4351 4352 /** 4353 * @brief Macro to configure the Kernel wake up from stop clock. 4354 * @param __STOPKERWUCLK__ specifies the Kernel clock source used after wake up from stop 4355 * This parameter can be one of the following values: 4356 * @arg @ref RCC_STOP_KERWAKEUPCLOCK_HSI HSI selected as Kernel clock source 4357 * @arg @ref RCC_STOP_KERWAKEUPCLOCK_CSI CSI selected as Kernel clock source 4358 * @retval None 4359 */ 4360 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__STOPKERWUCLK__) \ 4361 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__STOPKERWUCLK__)) 4362 /** 4363 * @} 4364 */ 4365 4366 /** @defgroup RCC_MCOx_Clock_Config RCC MCOx Clock Config 4367 * @{ 4368 */ 4369 4370 /** @brief Macro to configure the MCO1 clock. 4371 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4372 * This parameter can be one of the following values: 4373 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO1 source 4374 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO1 source 4375 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO1 source 4376 * @arg @ref RCC_MCO1SOURCE_PLL1Q PLL1Q clock selected as MCO1 source 4377 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO1 source 4378 * @param __MCODIV__ specifies the MCO clock prescaler. 4379 * This parameter can be one of the following values: 4380 * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 4381 */ 4382 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4383 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4384 4385 /** @brief Macro to configure the MCO2 clock. 4386 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4387 * This parameter can be one of the following values: 4388 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock (SYSCLK) selected as MCO2 source 4389 * @arg @ref RCC_MCO2SOURCE_PLL2P PLL2P clock selected as MCO2 source 4390 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source 4391 * @arg @ref RCC_MCO2SOURCE_PLL1P PLL1P clock selected as MCO2 source 4392 * @arg @ref RCC_MCO2SOURCE_CSI CSI clock selected as MCO2 source 4393 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source 4394 * @param __MCODIV__ specifies the MCO clock prescaler. 4395 * This parameter can be one of the following values: 4396 * @arg @ref RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 4397 */ 4398 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4399 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7U))); 4400 4401 /** 4402 * @} 4403 */ 4404 4405 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4406 * @brief macros to manage the specified RCC Flags and interrupts. 4407 * @{ 4408 */ 4409 /** @brief Enable RCC interrupt. 4410 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. 4411 * This parameter can be any combination of the following values: 4412 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4413 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4414 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4415 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4416 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4417 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4418 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4419 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4420 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4421 * @arg @ref RCC_IT_LSECSS Clock security system interrupt 4422 */ 4423 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4424 4425 /** @brief Disable RCC interrupt. 4426 * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. 4427 * This parameter can be any combination of the following values: 4428 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4429 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4430 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4431 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4432 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4433 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4434 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4435 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4436 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4437 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4438 */ 4439 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4440 4441 /** @brief Clear the RCC's interrupt pending bits 4442 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4443 * This parameter can be any combination of the following values: 4444 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4445 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4446 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4447 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4448 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4449 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4450 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4451 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4452 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4453 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4454 * @arg @ref RCC_IT_HSECSS HSE clock security interrupt 4455 */ 4456 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4457 4458 /** @brief Check whether the RCC interrupt has occurred or not. 4459 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 4460 * This parameter can be one of the following values: 4461 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4462 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4463 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4464 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4465 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4466 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4467 * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt 4468 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4469 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4470 * @arg @ref RCC_IT_LSECSS LSE clock security system interrupt 4471 * @arg @ref RCC_IT_HSECSS HSE clock security interrupt 4472 * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). 4473 */ 4474 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 4475 4476 /** @brief Set RMVF bit to clear the reset flags. 4477 * The reset flags are: RCC_FLAG_BORRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, 4478 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4479 */ 4480 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->RSR, RCC_RSR_RMVF) 4481 4482 /** @brief Check whether the selected RCC flag is set or not. 4483 * @param __FLAG__ specifies the flag to check. 4484 * This parameter can be one of the following values: 4485 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4486 * @arg @ref RCC_FLAG_HSIDIV HSI divider ready 4487 * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready 4488 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4489 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4490 * @arg @ref RCC_FLAG_PLL1RDY PLL1 clock ready 4491 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4492 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready 4493 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4494 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4495 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4496 * @arg @ref RCC_FLAG_BORRST BOR reset 4497 * @arg @ref RCC_FLAG_PINRST Pin reset 4498 * @arg @ref RCC_FLAG_PORRST Power-on reset 4499 * @arg @ref RCC_FLAG_SFTRST Software reset 4500 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4501 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4502 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4503 * @retval The new state of __FLAG__ (TRUE or FALSE). 4504 */ 4505 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX) ? RCC->CR : \ 4506 ((((__FLAG__) >> 5U) == RCC_BDCR_REG_INDEX) ? RCC->BDCR : \ 4507 ((((__FLAG__) >> 5U) == RCC_CSR_REG_INDEX) ? RCC->CSR : \ 4508 ((((__FLAG__) >> 5U) == RCC_RSR_REG_INDEX) ? RCC->RSR : RCC->CIFR)))) & \ 4509 (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4510 4511 /** 4512 * @} 4513 */ 4514 4515 /** 4516 * @} 4517 */ 4518 4519 /* Include RCC HAL Extension module */ 4520 #include "stm32h7rsxx_hal_rcc_ex.h" 4521 4522 /* Exported functions --------------------------------------------------------*/ 4523 /** @addtogroup RCC_Exported_Functions 4524 * @{ 4525 */ 4526 4527 /** @addtogroup RCC_Exported_Functions_Group1 4528 * @{ 4529 */ 4530 /* Initialization and de-initialization functions ******************************/ 4531 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4532 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4533 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 4534 4535 /** 4536 * @} 4537 */ 4538 4539 /** @addtogroup RCC_Exported_Functions_Group2 4540 * @{ 4541 */ 4542 /* Peripheral Control functions ************************************************/ 4543 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4544 void HAL_RCC_EnableCSS(void); 4545 void HAL_RCC_DisableCSS(void); 4546 uint32_t HAL_RCC_GetSysClockFreq(void); 4547 uint32_t HAL_RCC_GetHCLKFreq(void); 4548 uint32_t HAL_RCC_GetPCLK1Freq(void); 4549 uint32_t HAL_RCC_GetPCLK2Freq(void); 4550 uint32_t HAL_RCC_GetPCLK4Freq(void); 4551 uint32_t HAL_RCC_GetPCLK5Freq(void); 4552 uint32_t HAL_RCC_GetPLL1PFreq(void); 4553 uint32_t HAL_RCC_GetPLL1QFreq(void); 4554 uint32_t HAL_RCC_GetPLL1RFreq(void); 4555 uint32_t HAL_RCC_GetPLL1SFreq(void); 4556 uint32_t HAL_RCC_GetPLL2PFreq(void); 4557 uint32_t HAL_RCC_GetPLL2QFreq(void); 4558 uint32_t HAL_RCC_GetPLL2RFreq(void); 4559 uint32_t HAL_RCC_GetPLL2SFreq(void); 4560 uint32_t HAL_RCC_GetPLL2TFreq(void); 4561 uint32_t HAL_RCC_GetPLL3PFreq(void); 4562 uint32_t HAL_RCC_GetPLL3QFreq(void); 4563 uint32_t HAL_RCC_GetPLL3RFreq(void); 4564 uint32_t HAL_RCC_GetPLL3SFreq(void); 4565 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 4566 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 4567 /* CSS NMI IRQ handler */ 4568 void HAL_RCC_NMI_IRQHandler(void); 4569 /* User callbacks in non blocking mode (IT mode) */ 4570 void HAL_RCC_HSECSSCallback(void); 4571 void HAL_RCC_LSECSSCallback(void); 4572 uint32_t HAL_RCC_GetResetSource(void); 4573 /** 4574 * @} 4575 */ 4576 4577 /** 4578 * @} 4579 */ 4580 4581 /* Private types -------------------------------------------------------------*/ 4582 /* Private variables ---------------------------------------------------------*/ 4583 /* Private constants ---------------------------------------------------------*/ 4584 /** @defgroup RCC_Private_Constants RCC Private Constants 4585 * @{ 4586 */ 4587 #define RCC_PLL_VCOINPUTFREQ_MAX 16000000U /* Maximum VCO input frequency is 16 MHz */ 4588 #define RCC_PLL_VCOINPUTFREQ_MIN 1000000U /* Minimum VCO input frequency is 1 MHz */ 4589 4590 #define RCC_PLL_TIMEOUT_VALUE (50U) /* 50 ms */ 4591 4592 /* Defines used for Flags */ 4593 #define RCC_CR_REG_INDEX 1U 4594 #define RCC_BDCR_REG_INDEX 2U 4595 #define RCC_CSR_REG_INDEX 3U 4596 #define RCC_RSR_REG_INDEX 4U 4597 4598 #define RCC_FLAG_MASK 0x0000001FU 4599 4600 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 4601 4602 /** 4603 * @} 4604 */ 4605 4606 /* Private macros ------------------------------------------------------------*/ 4607 /** @addtogroup RCC_Private_Macros 4608 * @{ 4609 */ 4610 4611 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters 4612 * @{ 4613 */ 4614 4615 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4616 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 4617 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 4618 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ 4619 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 4620 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ 4621 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) 4622 4623 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4624 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) 4625 4626 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4627 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) 4628 4629 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4630 4631 #define IS_RCC_HSIDIV(__HSIDIV__) (((__HSIDIV__) == RCC_HSI_DIV1) || ((__HSIDIV__) == RCC_HSI_DIV2) || \ 4632 ((__HSIDIV__) == RCC_HSI_DIV4) || ((__HSIDIV__) == RCC_HSI_DIV8)) 4633 4634 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4635 <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) 4636 4637 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4638 4639 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4640 4641 #define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) 4642 4643 #define IS_RCC_CSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4644 <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) 4645 4646 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 4647 ((__PLL__) == RCC_PLL_ON)) 4648 4649 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 4650 ((__SOURCE__) == RCC_PLLSOURCE_CSI) || \ 4651 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 4652 4653 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) 4654 4655 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U)) 4656 4657 #define IS_RCC_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) 4658 4659 #define IS_RCC_PLLQ_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) 4660 4661 #define IS_RCC_PLLR_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) 4662 4663 #define IS_RCC_PLLS_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 4664 4665 #define IS_RCC_PLLT_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 4666 4667 #define IS_RCC_PLL_VCOINPUTFREQ(__VALUE__) ((RCC_PLL_VCOINPUTFREQ_MIN <= (__VALUE__)) &&\ 4668 ((__VALUE__) <= RCC_PLL_VCOINPUTFREQ_MAX)) 4669 4670 #define IS_RCC_PLLFRACN_VALUE(__VALUE__) ((__VALUE__) <= 8191U) 4671 4672 #define IS_RCC_PLLCLOCKOUT_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_PCLK) || \ 4673 ((__VALUE__) == RCC_PLL_QCLK) || \ 4674 ((__VALUE__) == RCC_PLL_RCLK) || \ 4675 ((__VALUE__) == RCC_PLL_SCLK)) 4676 4677 #define IS_RCC_PLLRGE_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_VCOINPUT_RANGE0) || \ 4678 ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE1) || \ 4679 ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE2) || \ 4680 ((__VALUE__) == RCC_PLL_VCOINPUT_RANGE3)) 4681 4682 #define IS_RCC_PLLVCO_VALUE(__VALUE__) (((__VALUE__) == RCC_PLL_VCO_HIGH) || \ 4683 ((__VALUE__) == RCC_PLL_VCO_LOW)) 4684 4685 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 63U)) 4686 4687 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4688 ((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ 4689 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4690 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4691 4692 #define IS_RCC_SYSCLK(__SYSCLK__) (((__SYSCLK__) == RCC_SYSCLK_DIV1) || ((__SYSCLK__) == RCC_SYSCLK_DIV2) || \ 4693 ((__SYSCLK__) == RCC_SYSCLK_DIV4) || ((__SYSCLK__) == RCC_SYSCLK_DIV8) || \ 4694 ((__SYSCLK__) == RCC_SYSCLK_DIV16) || ((__SYSCLK__) == RCC_SYSCLK_DIV64) || \ 4695 ((__SYSCLK__) == RCC_SYSCLK_DIV128) || ((__SYSCLK__) == RCC_SYSCLK_DIV256) || \ 4696 ((__SYSCLK__) == RCC_SYSCLK_DIV512)) 4697 4698 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_HCLK_DIV1) || ((__HCLK__) == RCC_HCLK_DIV2) || \ 4699 ((__HCLK__) == RCC_HCLK_DIV4) || ((__HCLK__) == RCC_HCLK_DIV8) || \ 4700 ((__HCLK__) == RCC_HCLK_DIV16) || ((__HCLK__) == RCC_HCLK_DIV64) || \ 4701 ((__HCLK__) == RCC_HCLK_DIV128) || ((__HCLK__) == RCC_HCLK_DIV256) || \ 4702 ((__HCLK__) == RCC_HCLK_DIV512)) 4703 4704 #define IS_RCC_PCLK1(__PCLK1__) (((__PCLK1__) == RCC_APB1_DIV1) || ((__PCLK1__) == RCC_APB1_DIV2) || \ 4705 ((__PCLK1__) == RCC_APB1_DIV4) || ((__PCLK1__) == RCC_APB1_DIV8) || \ 4706 ((__PCLK1__) == RCC_APB1_DIV16)) 4707 4708 #define IS_RCC_PCLK2(__PCLK2__) (((__PCLK2__) == RCC_APB2_DIV1) || ((__PCLK2__) == RCC_APB2_DIV2) || \ 4709 ((__PCLK2__) == RCC_APB2_DIV4) || ((__PCLK2__) == RCC_APB2_DIV8) || \ 4710 ((__PCLK2__) == RCC_APB2_DIV16)) 4711 4712 #define IS_RCC_PCLK4(__PCLK4__) (((__PCLK4__) == RCC_APB4_DIV1) || ((__PCLK4__) == RCC_APB4_DIV2) || \ 4713 ((__PCLK4__) == RCC_APB4_DIV4) || ((__PCLK4__) == RCC_APB4_DIV8) || \ 4714 ((__PCLK4__) == RCC_APB4_DIV16)) 4715 4716 #define IS_RCC_PCLK5(__PCLK5__) (((__PCLK5__) == RCC_APB5_DIV1) || ((__PCLK5__) == RCC_APB5_DIV2) || \ 4717 ((__PCLK5__) == RCC_APB5_DIV4) || ((__PCLK5__) == RCC_APB5_DIV8) || \ 4718 ((__PCLK5__) == RCC_APB5_DIV16)) 4719 4720 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 4721 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 4722 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 4723 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 4724 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 4725 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 4726 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 4727 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 4728 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 4729 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 4730 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 4731 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 4732 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 4733 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 4734 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 4735 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 4736 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 4737 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 4738 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 4739 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 4740 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 4741 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 4742 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 4743 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 4744 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 4745 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 4746 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 4747 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 4748 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 4749 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 4750 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 4751 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ 4752 ((__SOURCE__) == RCC_RTCCLKSOURCE_DISABLE)) 4753 4754 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 4755 ((__MCOX__) == RCC_MCO2_PC9)) 4756 4757 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 4758 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL1Q) || \ 4759 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 4760 4761 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO2SOURCE_PLL2P) || \ 4762 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || ((__SOURCE__) == RCC_MCO2SOURCE_PLL1P) || \ 4763 ((__SOURCE__) == RCC_MCO2SOURCE_CSI) || ((__SOURCE__) == RCC_MCO2SOURCE_LSI)) 4764 4765 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_NONE) || ((__DIV__) == RCC_MCODIV_1) || \ 4766 ((__DIV__) == RCC_MCODIV_2) || ((__DIV__) == RCC_MCODIV_3) || \ 4767 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_5) || \ 4768 ((__DIV__) == RCC_MCODIV_6) || ((__DIV__) == RCC_MCODIV_7) || \ 4769 ((__DIV__) == RCC_MCODIV_8) || ((__DIV__) == RCC_MCODIV_9) || \ 4770 ((__DIV__) == RCC_MCODIV_10) || ((__DIV__) == RCC_MCODIV_11) || \ 4771 ((__DIV__) == RCC_MCODIV_12) || ((__DIV__) == RCC_MCODIV_13) || \ 4772 ((__DIV__) == RCC_MCODIV_14) || ((__DIV__) == RCC_MCODIV_15)) 4773 4774 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 4775 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 4776 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 4777 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 4778 4779 #define IS_RCC_FLAG(__FLAG__) (((__FLAG__) == RCC_FLAG_HSIRDY) || ((__FLAG__) == RCC_FLAG_HSIDIV ) || \ 4780 ((__FLAG__) == RCC_FLAG_CSIRDY) || ((__FLAG__) == RCC_FLAG_HSI48RDY) || \ 4781 ((__FLAG__) == RCC_FLAG_HSERDY) || ((__FLAG__) == RCC_FLAG_PLL1RDY) || \ 4782 ((__FLAG__) == RCC_FLAG_PLL2RDY) || ((__FLAG__) == RCC_FLAG_PLL3RDY) || \ 4783 ((__FLAG__) == RCC_FLAG_LSERDY) || ((__FLAG__) == RCC_FLAG_LSECSSD) || \ 4784 ((__FLAG__) == RCC_FLAG_LSIRDY) || ((__FLAG__) == RCC_FLAG_BORRST) || \ 4785 ((__FLAG__) == RCC_FLAG_PINRST) || ((__FLAG__) == RCC_FLAG_PORRST) || \ 4786 ((__FLAG__) == RCC_FLAG_SFTRST) || ((__FLAG__) == RCC_FLAG_IWDGRST) || \ 4787 ((__FLAG__) == RCC_FLAG_WWDGRST) || ((__FLAG__) == RCC_FLAG_LPWRRST)) 4788 4789 #define IS_RCC_HSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) 4790 4791 #define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x3FU) 4792 4793 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 4794 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4795 4796 #define IS_RCC_STOP_KERWAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 4797 ((__SOURCE__) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 4798 /** 4799 * @} 4800 */ 4801 4802 /** 4803 * @} 4804 */ 4805 4806 /** 4807 * @} 4808 */ 4809 4810 /** 4811 * @} 4812 */ 4813 4814 #ifdef __cplusplus 4815 } 4816 #endif 4817 4818 #endif /* STM32H7RSxx_HAL_RCC_H */ 4819
