1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_RCC_H 21 #define STM32U5xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< The new state of the PLL. 49 This parameter can be a value of @ref RCC_PLL_Config */ 50 51 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 55 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 56 57 uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. 58 This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ 59 60 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 61 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 62 63 uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. 64 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 65 66 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 67 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 68 69 uint32_t PLLR; /*!< PLLR: Division factor for system clock. 70 This parameter must be a number between Min_Data = 2 and Max_Data = 128 71 Only division by 1 and even division factors are allowed */ 72 73 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 74 This parameter must be a value of @ref RCC_PLL_VCI_Range */ 75 76 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 8191 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 99 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 100 on the other devices */ 101 102 uint32_t LSIState; /*!< The new state of the LSI. 103 This parameter can be a value of @ref RCC_LSI_Config */ 104 105 uint32_t LSIDiv; /*!< The division factor of the LSI. 106 This parameter can be a value of @ref RCC_LSI_Div */ 107 108 uint32_t MSIState; /*!< The new state of the MSI. 109 This parameter can be a value of @ref RCC_MSI_Config */ 110 111 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 113 114 uint32_t MSIClockRange; /*!< The MSI frequency range. 115 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 116 117 uint32_t MSIKClockRange; /*!< The MSIK frequency range. 118 This parameter can be a value of @ref RCC_MSIK_Clock_Range */ 119 120 uint32_t HSI48State; /*!< The new state of the HSI48. 121 This parameter can be a value of @ref RCC_HSI48_Config */ 122 123 uint32_t SHSIState; /*!< The new state of the SHSI. 124 This parameter can be a value of @ref RCC_SHSI_Config */ 125 126 uint32_t MSIKState; /*!< The new state of the MSIK. 127 This parameter can be a value of @ref RCC_MSIK_Config */ 128 129 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 130 131 } RCC_OscInitTypeDef; 132 133 /** 134 * @brief RCC System, AHB and APB busses clock configuration structure definition 135 */ 136 typedef struct 137 { 138 uint32_t ClockType; /*!< The clock to be configured. 139 This parameter can be a value of @ref RCC_System_Clock_Type */ 140 141 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 142 This parameter can be a value of @ref RCC_System_Clock_Source */ 143 144 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock 145 (SYSCLK). 146 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 147 148 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 149 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 150 151 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 152 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 153 154 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 155 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 156 } RCC_ClkInitTypeDef; 157 158 /** 159 * @} 160 */ 161 162 /* Exported constants --------------------------------------------------------*/ 163 /** @defgroup RCC_Exported_Constants RCC Exported Constants 164 * @{ 165 */ 166 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 167 #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 168 #define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 169 170 /* Defines used for Flags */ 171 #define CR_REG_INDEX (1U) 172 #define BDCR_REG_INDEX (2U) 173 #define CSR_REG_INDEX (3U) 174 #define CRRCR_REG_INDEX (4U) 175 176 #define RCC_FLAG_MASK (0x1FU) 177 /** 178 * @} 179 */ 180 181 /** @defgroup RCC_Reset_Flag Reset Flag 182 * @{ 183 */ 184 #define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ 185 #define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ 186 #define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 187 #define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ 188 #define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 189 #define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 190 #define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ 191 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ 192 RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ 193 RCC_RESET_FLAG_LPWR) 194 /** 195 * @} 196 */ 197 198 /** @defgroup RCC_Timeout_Value Timeout Values 199 * @{ 200 */ 201 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 202 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 203 /** 204 * @} 205 */ 206 207 /** @defgroup RCC_Oscillator_Type Oscillator Type 208 * @{ 209 */ 210 #define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ 211 #define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ 212 #define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ 213 #define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ 214 #define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ 215 #define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ 216 #define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ 217 #define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ 218 #define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ 219 /* Defines Oscillator Masks */ 220 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ 221 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ 222 RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_HSE_Config HSE Config 228 * @{ 229 */ 230 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 231 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 232 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ 233 #define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_LSE_Config LSE Config 239 * @{ 240 */ 241 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 242 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 243 #define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ 244 #define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 245 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_HSI_Config HSI Config 251 * @{ 252 */ 253 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 254 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 255 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup RCC_LSI_Config LSI Config 261 * @{ 262 */ 263 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 264 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_LSI_Div LSI Div 270 * @{ 271 */ 272 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 273 #define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ 274 /** 275 * @} 276 */ 277 278 /** @defgroup RCC_MSI_Config MSI Config 279 * @{ 280 */ 281 #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ 282 #define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ 283 284 #define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup RCC_HSI48_Config HSI48 Config 290 * @{ 291 */ 292 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ 293 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup RCC_MSIK_Config MSIK Config 299 * @{ 300 */ 301 #define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ 302 #define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup RCC_SHSI_Config SHSI Config 308 * @{ 309 */ 310 #define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ 311 #define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ 312 /** 313 * @} 314 */ 315 316 /** @defgroup RCC_PLL_Config RCC PLL Config 317 * @{ 318 */ 319 #define RCC_PLL_NONE 0x00000000U 320 #define RCC_PLL_OFF 0x00000001U 321 #define RCC_PLL_ON 0x00000002U 322 /** 323 * @} 324 */ 325 326 327 /** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output 328 * @{ 329 */ 330 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 331 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 332 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 333 334 /** 335 * @} 336 */ 337 338 /** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider 339 * @{ 340 */ 341 #define RCC_PLLMBOOST_DIV1 0x00000000U 342 #define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 343 #define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 344 #define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) 345 #define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 346 #define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) 347 #define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) 348 #define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) 349 #define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 350 /** 351 * @} 352 */ 353 354 /** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range 355 * @{ 356 */ 357 #define RCC_PLLVCIRANGE_0 0x00000000U 358 #define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) 359 /** 360 * @} 361 */ 362 363 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source 364 * @{ 365 */ 366 #define RCC_PLLSOURCE_NONE 0x00000000U 367 #define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 368 #define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 369 #define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 370 371 /** 372 * @} 373 */ 374 375 376 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 377 * @{ 378 */ 379 #define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ 380 #define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ 381 #define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ 382 #define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ 383 #define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ 384 #define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ 385 #define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ 386 #define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ 387 #define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ 388 #define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ 389 #define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ 390 #define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ 391 #define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ 392 #define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ 393 #define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ 394 #define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ 395 RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ 396 /** 397 * @} 398 */ 399 400 /** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range 401 * @{ 402 */ 403 #define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ 404 #define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ 405 #define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ 406 #define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ 407 #define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ 408 #define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ 409 #define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ 410 #define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ 411 #define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ 412 #define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ 413 #define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ 414 #define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ 415 #define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ 416 #define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ 417 #define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ 418 #define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ 419 RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ 420 /** 421 * @} 422 */ 423 424 /** @defgroup RCC_System_Clock_Type System Clock Type 425 * @{ 426 */ 427 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 428 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 429 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 430 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 431 #define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup RCC_System_Clock_Source System Clock Source 437 * @{ 438 */ 439 #define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ 440 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ 441 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 442 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 448 * @{ 449 */ 450 #define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ 451 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ 452 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 453 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 454 /** 455 * @} 456 */ 457 458 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 459 * @{ 460 */ 461 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 462 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 463 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 464 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 465 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 466 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 467 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 468 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 469 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 470 /** 471 * @} 472 */ 473 474 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 475 * @{ 476 */ 477 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 478 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 479 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 480 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 481 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 487 * @{ 488 */ 489 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ 490 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 491 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 492 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup RCC_MCO_Index MCO Index 498 * @{ 499 */ 500 #define RCC_MCO1 0x00000000U 501 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 502 /** 503 * @} 504 */ 505 506 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 507 * @{ 508 */ 509 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 510 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 511 #define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ 512 #define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ 513 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ 514 #define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ 515 #define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ 516 #define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ 517 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 518 #define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ 519 /** 520 * @} 521 */ 522 523 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 524 * @{ 525 */ 526 #define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ 527 #define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ 528 #define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ 529 #define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ 530 #define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup RCC_Interrupt Interrupts 536 * @{ 537 */ 538 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 539 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 540 #define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ 541 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 542 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 543 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 544 #define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 545 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 546 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 547 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 548 #define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ 549 #define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup RCC_Flag Flags 555 * Elements values convention: XXXYYYYYb 556 * - YYYYY : Flag position in the register 557 * - XXX : Register index 558 * - 001: CR register 559 * - 010: BDCR register 560 * - 011: CSR register 561 * - 100: CRRCR register 562 * @{ 563 */ 564 /* Flags in the CR register */ 565 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ 566 #define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ 567 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 568 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 569 #define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ 570 #define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 571 #define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 572 #define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ 573 #define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 574 575 /* Flags in the BDCR register */ 576 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 577 #define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ 578 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 579 #define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 580 /* Flags in the CSR register */ 581 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ 582 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ 583 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 584 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ 585 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 586 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 587 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 588 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 589 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 595 * @{ 596 */ 597 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 598 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 599 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 600 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 606 * @{ 607 */ 608 #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ 609 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ 610 /** 611 * @} 612 */ 613 614 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 615 * @{ 616 */ 617 #define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ 618 #define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ 619 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_items RCC items 625 * @brief RCC items to configure attributes on 626 * @{ 627 */ 628 #define RCC_HSI RCC_SECCFGR_HSISEC 629 #define RCC_HSE RCC_SECCFGR_HSESEC 630 #define RCC_MSI RCC_SECCFGR_MSISEC 631 #define RCC_LSI RCC_SECCFGR_LSISEC 632 #define RCC_LSE RCC_SECCFGR_LSESEC 633 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 634 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 635 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 636 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 637 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 638 #define RCC_ICLK RCC_SECCFGR_ICLKSEC 639 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 640 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 641 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 642 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 643 RCC_PLL3|RCC_ICLK|RCC_RMVF) 644 /** 645 * @} 646 */ 647 648 /** @defgroup RCC_attributes RCC attributes 649 * @brief RCC privilege/non-privilege and secure/non-secure attributes 650 * @{ 651 */ 652 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 653 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 654 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 655 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 656 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 657 #endif /* __ARM_FEATURE_CMSE */ 658 /** 659 * @} 660 */ 661 662 /* Exported macros -----------------------------------------------------------*/ 663 664 /** @defgroup RCC_Exported_Macros RCC Exported Macros 665 * @{ 666 */ 667 668 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 669 * @brief Enable or disable the AHB1 peripheral clock. 670 * @note After reset, the peripheral clock (used for registers read/write access) 671 * is disabled and the application software has to enable this clock before 672 * using it. 673 * @{ 674 */ 675 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 676 __IO uint32_t tmpreg; \ 677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 678 /* Delay after an RCC peripheral clock enabling */ \ 679 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 680 UNUSED(tmpreg); \ 681 } while(0) 682 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 683 __IO uint32_t tmpreg; \ 684 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 685 /* Delay after an RCC peripheral clock enabling */ \ 686 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 687 UNUSED(tmpreg); \ 688 } while(0) 689 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 690 __IO uint32_t tmpreg; \ 691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 692 /* Delay after an RCC peripheral clock enabling */ \ 693 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 694 UNUSED(tmpreg); \ 695 } while(0) 696 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 697 __IO uint32_t tmpreg; \ 698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 699 /* Delay after an RCC peripheral clock enabling */ \ 700 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 701 UNUSED(tmpreg); \ 702 } while(0) 703 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 704 __IO uint32_t tmpreg; \ 705 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 706 /* Delay after an RCC peripheral clock enabling */ \ 707 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 708 UNUSED(tmpreg); \ 709 } while(0) 710 711 #if defined(JPEG) 712 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \ 713 __IO uint32_t tmpreg; \ 714 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ 715 /* Delay after an RCC peripheral clock enabling */ \ 716 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ 717 UNUSED(tmpreg); \ 718 } while(0) 719 #endif /* JPEG */ 720 721 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 722 __IO uint32_t tmpreg; \ 723 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 724 /* Delay after an RCC peripheral clock enabling */ \ 725 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 726 UNUSED(tmpreg); \ 727 } while(0) 728 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 729 __IO uint32_t tmpreg; \ 730 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 731 /* Delay after an RCC peripheral clock enabling */ \ 732 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 733 UNUSED(tmpreg); \ 734 } while(0) 735 736 #define __HAL_RCC_MDF1_CLK_ENABLE() do { \ 737 __IO uint32_t tmpreg; \ 738 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 739 /* Delay after an RCC peripheral clock enabling */ \ 740 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 741 UNUSED(tmpreg); \ 742 } while(0) 743 744 #if defined(DMA2D) 745 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ 746 __IO uint32_t tmpreg; \ 747 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 748 /* Delay after an RCC peripheral clock enabling */ \ 749 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 750 UNUSED(tmpreg); \ 751 } while(0) 752 #endif /* DMA2D */ 753 754 #if defined(GFXMMU) 755 #define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ 756 __IO uint32_t tmpreg; \ 757 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 758 /* Delay after an RCC peripheral clock enabling */ \ 759 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 760 UNUSED(tmpreg); \ 761 } while(0) 762 #endif /* GFXMMU */ 763 764 #if defined(GPU2D) 765 #define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ 766 __IO uint32_t tmpreg; \ 767 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ 768 /* Delay after an RCC peripheral clock enabling */ \ 769 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ 770 UNUSED(tmpreg); \ 771 } while(0) 772 #endif /* GPU2D */ 773 774 #if defined(DCACHE2) 775 #define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ 776 __IO uint32_t tmpreg; \ 777 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ 778 /* Delay after an RCC peripheral clock enabling */ \ 779 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ 780 UNUSED(tmpreg); \ 781 } while(0) 782 #endif /* DCACHE2 */ 783 784 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 785 __IO uint32_t tmpreg; \ 786 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 787 /* Delay after an RCC peripheral clock enabling */ \ 788 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 789 UNUSED(tmpreg); \ 790 } while(0) 791 792 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ 793 __IO uint32_t tmpreg; \ 794 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 795 /* Delay after an RCC peripheral clock enabling */ \ 796 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ 797 UNUSED(tmpreg); \ 798 } while(0) 799 800 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 801 __IO uint32_t tmpreg; \ 802 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 803 /* Delay after an RCC peripheral clock enabling */ \ 804 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 805 UNUSED(tmpreg); \ 806 } while(0) 807 808 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 809 __IO uint32_t tmpreg; \ 810 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 811 /* Delay after an RCC peripheral clock enabling */ \ 812 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 813 UNUSED(tmpreg); \ 814 } while(0) 815 816 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 817 818 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 819 820 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 821 822 #define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) 823 824 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 825 826 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 827 828 #if defined(JPEG) 829 #define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) 830 #endif /* JPEG */ 831 832 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 833 834 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 835 836 #if defined(DMA2D) 837 #define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) 838 #endif /* DMA2D */ 839 840 #if defined(GFXMMU) 841 #define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) 842 #endif /* GFXMMU */ 843 844 #if defined(GPU2D) 845 #define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) 846 #endif /* GPU2D */ 847 848 #if defined(DCACHE2) 849 #define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) 850 #endif /* DCACHE2 */ 851 852 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) 853 854 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) 855 856 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 857 858 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 859 /** 860 * @} 861 */ 862 863 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 864 * @brief Enable or disable the AHB2 peripheral clock. 865 * @note After reset, the peripheral clock (used for registers read/write access) 866 * is disabled and the application software has to enable this clock before 867 * using it. 868 * @{ 869 */ 870 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 871 __IO uint32_t tmpreg; \ 872 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 873 /* Delay after an RCC peripheral clock enabling */ \ 874 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ 875 UNUSED(tmpreg); \ 876 } while(0) 877 878 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 879 __IO uint32_t tmpreg; \ 880 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 881 /* Delay after an RCC peripheral clock enabling */ \ 882 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ 883 UNUSED(tmpreg); \ 884 } while(0) 885 886 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 887 __IO uint32_t tmpreg; \ 888 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 889 /* Delay after an RCC peripheral clock enabling */ \ 890 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ 891 UNUSED(tmpreg); \ 892 } while(0) 893 894 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 895 __IO uint32_t tmpreg; \ 896 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 897 /* Delay after an RCC peripheral clock enabling */ \ 898 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ 899 UNUSED(tmpreg); \ 900 } while(0) 901 902 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 903 __IO uint32_t tmpreg; \ 904 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 905 /* Delay after an RCC peripheral clock enabling */ \ 906 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ 907 UNUSED(tmpreg); \ 908 } while(0) 909 910 #if defined(GPIOF) 911 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 912 __IO uint32_t tmpreg; \ 913 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 914 /* Delay after an RCC peripheral clock enabling */ \ 915 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ 916 UNUSED(tmpreg); \ 917 } while(0) 918 #endif /* GPIOF */ 919 920 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 921 __IO uint32_t tmpreg; \ 922 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 923 /* Delay after an RCC peripheral clock enabling */ \ 924 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ 925 UNUSED(tmpreg); \ 926 } while(0) 927 928 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 929 __IO uint32_t tmpreg; \ 930 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 931 /* Delay after an RCC peripheral clock enabling */ \ 932 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ 933 UNUSED(tmpreg); \ 934 } while(0) 935 936 #if defined (GPIOI) 937 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 938 __IO uint32_t tmpreg; \ 939 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 940 /* Delay after an RCC peripheral clock enabling */ \ 941 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ 942 UNUSED(tmpreg); \ 943 } while(0) 944 #endif /* GPIOI */ 945 946 #if defined(GPIOJ) 947 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ 948 __IO uint32_t tmpreg; \ 949 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ 950 /* Delay after an RCC peripheral clock enabling */ \ 951 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ 952 UNUSED(tmpreg); \ 953 } while(0) 954 955 #endif /* GPIOJ */ 956 957 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ 958 __IO uint32_t tmpreg; \ 959 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ 960 /* Delay after an RCC peripheral clock enabling */ \ 961 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ 962 UNUSED(tmpreg); \ 963 } while(0) 964 965 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 966 __IO uint32_t tmpreg; \ 967 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 968 /* Delay after an RCC peripheral clock enabling */ \ 969 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ 970 UNUSED(tmpreg); \ 971 } while(0) 972 #if defined (USB_OTG_HS) 973 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ 974 __IO uint32_t tmpreg; \ 975 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 976 /* Delay after an RCC peripheral clock enabling */ \ 977 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 978 UNUSED(tmpreg); \ 979 } while(0) 980 #endif /* USB_OTG_HS */ 981 982 #if defined(USB_OTG_FS) 983 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 984 __IO uint32_t tmpreg; \ 985 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 986 /* Delay after an RCC peripheral clock enabling */ \ 987 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ 988 UNUSED(tmpreg); \ 989 } while(0) 990 991 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ 992 #endif /* defined (USB_OTG_FS) */ 993 994 #if defined(RCC_AHB2ENR1_USBPHYCEN) 995 #define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ 996 __IO uint32_t tmpreg; \ 997 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ 998 /* Delay after an RCC peripheral clock enabling */ \ 999 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ 1000 UNUSED(tmpreg); \ 1001 } while(0) 1002 #endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ 1003 1004 #if defined(AES) 1005 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 1006 __IO uint32_t tmpreg; \ 1007 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 1008 /* Delay after an RCC peripheral clock enabling */ \ 1009 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ 1010 UNUSED(tmpreg); \ 1011 } while(0) 1012 #endif /* AES */ 1013 1014 #if defined(HASH) 1015 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1016 __IO uint32_t tmpreg; \ 1017 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 1018 /* Delay after an RCC peripheral clock enabling */ \ 1019 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ 1020 UNUSED(tmpreg); \ 1021 } while(0) 1022 #endif /* HASH */ 1023 1024 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1025 __IO uint32_t tmpreg; \ 1026 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 1027 /* Delay after an RCC peripheral clock enabling */ \ 1028 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ 1029 UNUSED(tmpreg); \ 1030 } while(0) 1031 1032 #if defined(PKA) 1033 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1034 __IO uint32_t tmpreg; \ 1035 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 1036 /* Delay after an RCC peripheral clock enabling */ \ 1037 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ 1038 UNUSED(tmpreg); \ 1039 } while(0) 1040 #endif /* PKA */ 1041 1042 #if defined(SAES) 1043 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1044 __IO uint32_t tmpreg; \ 1045 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 1046 /* Delay after an RCC peripheral clock enabling */ \ 1047 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ 1048 UNUSED(tmpreg); \ 1049 } while(0) 1050 #endif /* SAES */ 1051 1052 #if defined(OCTOSPIM) 1053 #define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ 1054 __IO uint32_t tmpreg; \ 1055 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 1056 /* Delay after an RCC peripheral clock enabling */ \ 1057 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ 1058 UNUSED(tmpreg); \ 1059 } while(0) 1060 #endif /* OCTOSPIM */ 1061 1062 #if defined(OTFDEC1) 1063 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 1064 __IO uint32_t tmpreg; \ 1065 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 1066 /* Delay after an RCC peripheral clock enabling */ \ 1067 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ 1068 UNUSED(tmpreg); \ 1069 } while(0) 1070 #endif /* OTFDEC1 */ 1071 1072 #if defined(OTFDEC2) 1073 #define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ 1074 __IO uint32_t tmpreg; \ 1075 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 1076 /* Delay after an RCC peripheral clock enabling */ \ 1077 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ 1078 UNUSED(tmpreg); \ 1079 } while(0) 1080 #endif /* OTFDEC2 */ 1081 1082 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1083 __IO uint32_t tmpreg; \ 1084 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 1085 /* Delay after an RCC peripheral clock enabling */ \ 1086 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ 1087 UNUSED(tmpreg); \ 1088 } while(0) 1089 1090 #if defined(SDMMC2) 1091 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1092 __IO uint32_t tmpreg; \ 1093 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 1094 /* Delay after an RCC peripheral clock enabling */ \ 1095 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ 1096 UNUSED(tmpreg); \ 1097 } while(0) 1098 #endif /* SDMMC2 */ 1099 1100 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 1101 __IO uint32_t tmpreg; \ 1102 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 1103 /* Delay after an RCC peripheral clock enabling */ \ 1104 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ 1105 UNUSED(tmpreg); \ 1106 } while(0) 1107 #if defined(SRAM3_BASE) 1108 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 1109 __IO uint32_t tmpreg; \ 1110 SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1111 /* Delay after an RCC peripheral clock enabling */ \ 1112 tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ 1113 UNUSED(tmpreg); \ 1114 } while(0) 1115 #endif /* SRAM3_BASE */ 1116 1117 #if defined(FMC_BASE) 1118 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1119 __IO uint32_t tmpreg; \ 1120 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1121 /* Delay after an RCC peripheral clock enabling */ \ 1122 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ 1123 UNUSED(tmpreg); \ 1124 } while(0) 1125 #endif /* FMC_BASE */ 1126 1127 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1128 __IO uint32_t tmpreg; \ 1129 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1130 /* Delay after an RCC peripheral clock enabling */ \ 1131 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ 1132 UNUSED(tmpreg); \ 1133 } while(0) 1134 1135 #if defined(OCTOSPI2) 1136 #define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ 1137 __IO uint32_t tmpreg; \ 1138 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1139 /* Delay after an RCC peripheral clock enabling */ \ 1140 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ 1141 UNUSED(tmpreg); \ 1142 } while(0) 1143 #endif /* OCTOSPI2 */ 1144 1145 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) 1146 1147 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) 1148 1149 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) 1150 1151 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) 1152 1153 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) 1154 1155 #if defined(GPIOF) 1156 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) 1157 #endif /* GPIOF */ 1158 1159 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) 1160 1161 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) 1162 1163 #if defined(GPIOI) 1164 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) 1165 #endif /* GPIOI */ 1166 1167 #if defined(GPIOJ) 1168 #define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) 1169 #endif /* GPIOJ */ 1170 1171 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) 1172 1173 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) 1174 1175 #if defined(USB_OTG_HS) 1176 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1177 #endif /* USB_OTG_HS */ 1178 1179 #if defined(USB_OTG_FS) 1180 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) 1181 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ 1182 #endif /* USB_OTG_FS */ 1183 1184 #if defined(RCC_AHB2ENR1_USBPHYCEN) 1185 #define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) 1186 #endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ 1187 1188 #if defined(AES) 1189 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) 1190 #endif /* AES */ 1191 1192 #if defined(HASH) 1193 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) 1194 #endif /* HASH */ 1195 1196 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) 1197 1198 #if defined(PKA) 1199 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) 1200 #endif /* PKA */ 1201 1202 #if defined(SAES) 1203 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) 1204 #endif /* SAES */ 1205 1206 #if defined(OCTOSPIM) 1207 #define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) 1208 #endif /* OCTOSPIM */ 1209 1210 #if defined(OTFDEC1) 1211 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) 1212 #endif /* OTFDEC1 */ 1213 1214 #if defined(OTFDEC2) 1215 #define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) 1216 #endif /* OTFDEC2 */ 1217 1218 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) 1219 1220 #if defined(SDMMC2) 1221 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) 1222 #endif /* SDMMC2 */ 1223 1224 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) 1225 1226 #if defined(SRAM3_BASE) 1227 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) 1228 #endif /* SRAM3_BASE */ 1229 1230 #if defined(HSPI1) 1231 #define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ 1232 __IO uint32_t tmpreg; \ 1233 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ 1234 /* Delay after an RCC peripheral clock enabling */ \ 1235 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ 1236 UNUSED(tmpreg); \ 1237 } while(0) 1238 #endif /* HSPI1 */ 1239 1240 #if defined (SRAM6_BASE) 1241 #define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ 1242 __IO uint32_t tmpreg; \ 1243 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ 1244 /* Delay after an RCC peripheral clock enabling */ \ 1245 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ 1246 UNUSED(tmpreg); \ 1247 } while(0) 1248 #endif /* SRAM6_BASE */ 1249 1250 #if defined (SRAM5_BASE) 1251 #define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ 1252 __IO uint32_t tmpreg; \ 1253 SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ 1254 /* Delay after an RCC peripheral clock enabling */ \ 1255 tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ 1256 UNUSED(tmpreg); \ 1257 } while(0) 1258 #endif /* SRAM5_BASE */ 1259 1260 #if defined(FMC_BASE) 1261 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) 1262 #endif /* FMC_BASE */ 1263 1264 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) 1265 1266 #if defined(OCTOSPI2) 1267 #define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) 1268 #endif /* OCTOSPI2 */ 1269 1270 #if defined(HSPI1) 1271 #define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) 1272 #endif /* HSPI1 */ 1273 1274 #if defined (SRAM6_BASE) 1275 #define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) 1276 #endif /* SRAM6_BASE */ 1277 1278 #if defined (SRAM5_BASE) 1279 #define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) 1280 #endif /* SRAM5_BASE */ 1281 /** 1282 * @} 1283 */ 1284 1285 /** @defgroup BUS AHB APB Peripheral Clock Enable Disable 1286 * @{ 1287 */ 1288 #define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); 1289 1290 #define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); 1291 1292 #define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); 1293 1294 #define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); 1295 1296 #define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); 1297 1298 #define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); 1299 1300 #define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); 1301 1302 #define __HAL_RCC_AHB1_CLK_ENABLE() do { \ 1303 __IO uint32_t tmpreg; \ 1304 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1305 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 1306 UNUSED(tmpreg); \ 1307 } while(0) 1308 1309 #define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ 1310 __IO uint32_t tmpreg; \ 1311 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1312 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ 1313 UNUSED(tmpreg); \ 1314 } while(0) 1315 1316 #define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ 1317 __IO uint32_t tmpreg; \ 1318 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1319 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ 1320 UNUSED(tmpreg); \ 1321 } while(0) 1322 1323 1324 #define __HAL_RCC_AHB3_CLK_ENABLE() do { \ 1325 __IO uint32_t tmpreg; \ 1326 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1327 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ 1328 UNUSED(tmpreg); \ 1329 } while(0) 1330 1331 #define __HAL_RCC_APB1_CLK_ENABLE() do { \ 1332 __IO uint32_t tmpreg; \ 1333 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1334 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 1335 UNUSED(tmpreg); \ 1336 } while(0) 1337 1338 #define __HAL_RCC_APB2_CLK_ENABLE() do { \ 1339 __IO uint32_t tmpreg; \ 1340 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1341 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 1342 UNUSED(tmpreg); \ 1343 } while(0) 1344 1345 #define __HAL_RCC_APB3_CLK_ENABLE() do { \ 1346 __IO uint32_t tmpreg; \ 1347 CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1348 tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ 1349 UNUSED(tmpreg); \ 1350 } while(0) 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable 1357 * @brief Enable or disable the AHB3ENR peripheral clock. 1358 * @note After reset, the peripheral clock (used for registers read/write access) 1359 * is disabled and the application software has to enable this clock before 1360 * using it. 1361 * @{ 1362 */ 1363 1364 #define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ 1365 __IO uint32_t tmpreg; \ 1366 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1367 /* Delay after an RCC peripheral clock enabling */ \ 1368 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ 1369 UNUSED(tmpreg); \ 1370 } while(0) 1371 1372 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1373 __IO uint32_t tmpreg; \ 1374 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1375 /* Delay after an RCC peripheral clock enabling */ \ 1376 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ 1377 UNUSED(tmpreg); \ 1378 } while(0) 1379 1380 #define __HAL_RCC_ADC4_CLK_ENABLE() do { \ 1381 __IO uint32_t tmpreg; \ 1382 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1383 /* Delay after an RCC peripheral clock enabling */ \ 1384 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ 1385 UNUSED(tmpreg); \ 1386 } while(0) 1387 1388 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1389 __IO uint32_t tmpreg; \ 1390 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1391 /* Delay after an RCC peripheral clock enabling */ \ 1392 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ 1393 UNUSED(tmpreg); \ 1394 } while(0) 1395 1396 #define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ 1397 __IO uint32_t tmpreg; \ 1398 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1399 /* Delay after an RCC peripheral clock enabling */ \ 1400 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ 1401 UNUSED(tmpreg); \ 1402 } while(0) 1403 1404 #define __HAL_RCC_ADF1_CLK_ENABLE() do { \ 1405 __IO uint32_t tmpreg; \ 1406 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1407 /* Delay after an RCC peripheral clock enabling */ \ 1408 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ 1409 UNUSED(tmpreg); \ 1410 } while(0) 1411 1412 #define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ 1413 __IO uint32_t tmpreg; \ 1414 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1415 /* Delay after an RCC peripheral clock enabling */ \ 1416 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ 1417 UNUSED(tmpreg); \ 1418 } while(0) 1419 1420 #define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ 1421 __IO uint32_t tmpreg; \ 1422 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1423 /* Delay after an RCC peripheral clock enabling */ \ 1424 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ 1425 UNUSED(tmpreg); \ 1426 } while(0) 1427 1428 #define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) 1429 1430 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) 1431 1432 #define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) 1433 1434 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) 1435 1436 #define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) 1437 1438 #define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) 1439 1440 #define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) 1441 1442 #define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) 1443 1444 /** 1445 * @} 1446 */ 1447 1448 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1449 * @brief Enable or disable the APB1 peripheral clock. 1450 * @note After reset, the peripheral clock (used for registers read/write access) 1451 * is disabled and the application software has to enable this clock before 1452 * using it. 1453 * @{ 1454 */ 1455 1456 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1457 __IO uint32_t tmpreg; \ 1458 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1459 /* Delay after an RCC peripheral clock enabling */ \ 1460 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 1461 UNUSED(tmpreg); \ 1462 } while(0) 1463 1464 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1465 __IO uint32_t tmpreg; \ 1466 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1467 /* Delay after an RCC peripheral clock enabling */ \ 1468 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 1469 UNUSED(tmpreg); \ 1470 } while(0) 1471 1472 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1473 __IO uint32_t tmpreg; \ 1474 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1475 /* Delay after an RCC peripheral clock enabling */ \ 1476 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 1477 UNUSED(tmpreg); \ 1478 } while(0) 1479 1480 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1481 __IO uint32_t tmpreg; \ 1482 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1483 /* Delay after an RCC peripheral clock enabling */ \ 1484 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 1485 UNUSED(tmpreg); \ 1486 } while(0) 1487 1488 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1489 __IO uint32_t tmpreg; \ 1490 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1491 /* Delay after an RCC peripheral clock enabling */ \ 1492 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 1493 UNUSED(tmpreg); \ 1494 } while(0) 1495 1496 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1497 __IO uint32_t tmpreg; \ 1498 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1499 /* Delay after an RCC peripheral clock enabling */ \ 1500 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 1501 UNUSED(tmpreg); \ 1502 } while(0) 1503 1504 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1505 __IO uint32_t tmpreg; \ 1506 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1507 /* Delay after an RCC peripheral clock enabling */ \ 1508 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1509 UNUSED(tmpreg); \ 1510 } while(0) 1511 1512 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1513 __IO uint32_t tmpreg; \ 1514 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1515 /* Delay after an RCC peripheral clock enabling */ \ 1516 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1517 UNUSED(tmpreg); \ 1518 } while(0) 1519 1520 #if defined(USART2) 1521 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1522 __IO uint32_t tmpreg; \ 1523 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1524 /* Delay after an RCC peripheral clock enabling */ \ 1525 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1526 UNUSED(tmpreg); \ 1527 } while(0) 1528 #endif /* USART2 */ 1529 1530 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1531 __IO uint32_t tmpreg; \ 1532 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1533 /* Delay after an RCC peripheral clock enabling */ \ 1534 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1535 UNUSED(tmpreg); \ 1536 } while(0) 1537 1538 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1539 __IO uint32_t tmpreg; \ 1540 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1541 /* Delay after an RCC peripheral clock enabling */ \ 1542 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1543 UNUSED(tmpreg); \ 1544 } while(0) 1545 1546 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1547 __IO uint32_t tmpreg; \ 1548 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1549 /* Delay after an RCC peripheral clock enabling */ \ 1550 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1551 UNUSED(tmpreg); \ 1552 } while(0) 1553 1554 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1555 __IO uint32_t tmpreg; \ 1556 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1557 /* Delay after an RCC peripheral clock enabling */ \ 1558 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1559 UNUSED(tmpreg); \ 1560 } while(0) 1561 1562 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1563 __IO uint32_t tmpreg; \ 1564 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1565 /* Delay after an RCC peripheral clock enabling */ \ 1566 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1567 UNUSED(tmpreg); \ 1568 } while(0) 1569 1570 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1571 __IO uint32_t tmpreg; \ 1572 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1573 /* Delay after an RCC peripheral clock enabling */ \ 1574 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1575 UNUSED(tmpreg); \ 1576 } while(0) 1577 1578 1579 #if defined(USART6) 1580 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1581 __IO uint32_t tmpreg; \ 1582 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ 1583 /* Delay after an RCC peripheral clock enabling */ \ 1584 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ 1585 UNUSED(tmpreg); \ 1586 } while(0) 1587 #endif /* USART6 */ 1588 1589 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1590 __IO uint32_t tmpreg; \ 1591 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1592 /* Delay after an RCC peripheral clock enabling */ \ 1593 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1594 UNUSED(tmpreg); \ 1595 } while(0) 1596 1597 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1598 __IO uint32_t tmpreg; \ 1599 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1600 /* Delay after an RCC peripheral clock enabling */ \ 1601 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1602 UNUSED(tmpreg); \ 1603 } while(0) 1604 1605 #if defined(I2C5) 1606 #define __HAL_RCC_I2C5_CLK_ENABLE() do { \ 1607 __IO uint32_t tmpreg; \ 1608 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ 1609 /* Delay after an RCC peripheral clock enabling */ \ 1610 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ 1611 UNUSED(tmpreg); \ 1612 } while(0) 1613 #endif /* I2C5 */ 1614 1615 #if defined(I2C6) 1616 #define __HAL_RCC_I2C6_CLK_ENABLE() do { \ 1617 __IO uint32_t tmpreg; \ 1618 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ 1619 /* Delay after an RCC peripheral clock enabling */ \ 1620 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ 1621 UNUSED(tmpreg); \ 1622 } while(0) 1623 #endif /* I2C6 */ 1624 1625 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1626 __IO uint32_t tmpreg; \ 1627 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1628 /* Delay after an RCC peripheral clock enabling */ \ 1629 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1630 UNUSED(tmpreg); \ 1631 } while(0) 1632 1633 #if defined(UCPD1) 1634 #define __HAL_RCC_UCPD_CLK_ENABLE() do { \ 1635 __IO uint32_t tmpreg; \ 1636 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1637 /* Delay after an RCC peripheral clock enabling */ \ 1638 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1639 UNUSED(tmpreg); \ 1640 } while(0) 1641 #endif /* UCPD1 */ 1642 1643 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1644 1645 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1646 1647 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1648 1649 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1650 1651 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1652 1653 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1654 1655 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1656 1657 #if defined(USART2) 1658 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1659 #endif /* USART2 */ 1660 1661 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1662 1663 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1664 1665 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1666 1667 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1668 1669 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1670 1671 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) 1672 1673 #if defined(USART6) 1674 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) 1675 #endif /* USART6 */ 1676 1677 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1678 1679 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1680 1681 #if defined(I2C5) 1682 #define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) 1683 #endif /* I2C5 */ 1684 1685 #if defined(I2C6) 1686 #define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) 1687 #endif /* I2C6 */ 1688 1689 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1690 1691 #if defined(UCPD1) 1692 #define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) 1693 #endif /* UCPD1 */ 1694 1695 /** 1696 * @} 1697 */ 1698 1699 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1700 * @brief Enable or disable the APB2 peripheral clock. 1701 * @note After reset, the peripheral clock (used for registers read/write access) 1702 * is disabled and the application software has to enable this clock before 1703 * using it. 1704 * @{ 1705 */ 1706 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1707 __IO uint32_t tmpreg; \ 1708 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1709 /* Delay after an RCC peripheral clock enabling */ \ 1710 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1711 UNUSED(tmpreg); \ 1712 } while(0) 1713 1714 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1715 __IO uint32_t tmpreg; \ 1716 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1717 /* Delay after an RCC peripheral clock enabling */ \ 1718 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1719 UNUSED(tmpreg); \ 1720 } while(0) 1721 1722 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1723 __IO uint32_t tmpreg; \ 1724 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1725 /* Delay after an RCC peripheral clock enabling */ \ 1726 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1727 UNUSED(tmpreg); \ 1728 } while(0) 1729 1730 1731 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1732 __IO uint32_t tmpreg; \ 1733 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1734 /* Delay after an RCC peripheral clock enabling */ \ 1735 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1736 UNUSED(tmpreg); \ 1737 } while(0) 1738 1739 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1740 __IO uint32_t tmpreg; \ 1741 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1742 /* Delay after an RCC peripheral clock enabling */ \ 1743 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1744 UNUSED(tmpreg); \ 1745 } while(0) 1746 1747 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1748 __IO uint32_t tmpreg; \ 1749 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1750 /* Delay after an RCC peripheral clock enabling */ \ 1751 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1752 UNUSED(tmpreg); \ 1753 } while(0) 1754 1755 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1756 __IO uint32_t tmpreg; \ 1757 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1758 /* Delay after an RCC peripheral clock enabling */ \ 1759 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1760 UNUSED(tmpreg); \ 1761 } while(0) 1762 1763 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1764 __IO uint32_t tmpreg; \ 1765 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1766 /* Delay after an RCC peripheral clock enabling */ \ 1767 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1768 UNUSED(tmpreg); \ 1769 } while(0) 1770 1771 #if defined (SAI2) 1772 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1773 __IO uint32_t tmpreg; \ 1774 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1775 /* Delay after an RCC peripheral clock enabling */ \ 1776 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1777 UNUSED(tmpreg); \ 1778 } while(0) 1779 #endif /* SAI2 */ 1780 1781 #if defined(USB_DRD_FS) 1782 #define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ 1783 __IO uint32_t tmpreg; \ 1784 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1785 /* Delay after an RCC peripheral clock enabling */ \ 1786 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1787 UNUSED(tmpreg); \ 1788 } while(0) 1789 #endif /* USB_DRD_FS */ 1790 1791 #if defined(GFXTIM) 1792 #define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ 1793 __IO uint32_t tmpreg; \ 1794 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ 1795 /* Delay after an RCC peripheral clock enabling */ \ 1796 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ 1797 UNUSED(tmpreg); \ 1798 } while(0) 1799 #endif /* GFXTIM */ 1800 1801 #if defined(LTDC) 1802 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ 1803 __IO uint32_t tmpreg; \ 1804 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1805 /* Delay after an RCC peripheral clock enabling */ \ 1806 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ 1807 UNUSED(tmpreg); \ 1808 } while(0) 1809 #endif /* LTDC */ 1810 1811 #if defined(DSI) 1812 #define __HAL_RCC_DSI_CLK_ENABLE() do { \ 1813 __IO uint32_t tmpreg; \ 1814 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ 1815 /* Delay after an RCC peripheral clock enabling */ \ 1816 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ 1817 UNUSED(tmpreg); \ 1818 } while(0) 1819 #endif /* DSI */ 1820 1821 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1822 1823 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1824 1825 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1826 1827 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1828 1829 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1830 1831 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1832 1833 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1834 1835 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1836 1837 #if defined (SAI2) 1838 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1839 #endif /* SAI2 */ 1840 1841 #if defined (USB_DRD_FS) 1842 #define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) 1843 #endif /* USB_DRD_FS */ 1844 1845 #if defined(GFXTIM) 1846 #define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) 1847 #endif /* GFXTIM */ 1848 1849 #if defined(LTDC) 1850 #define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) 1851 #endif /* LTDC */ 1852 1853 #if defined(DSI) 1854 #define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) 1855 #endif /* DSI */ 1856 1857 /** 1858 * @} 1859 */ 1860 1861 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1862 * @brief Enable or disable the APB3 peripheral clock. 1863 * @note After reset, the peripheral clock (used for registers read/write access) 1864 * is disabled and the application software has to enable this clock before 1865 * using it. 1866 * @{ 1867 */ 1868 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1869 __IO uint32_t tmpreg; \ 1870 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1871 /* Delay after an RCC peripheral clock enabling */ \ 1872 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ 1873 UNUSED(tmpreg); \ 1874 } while(0) 1875 1876 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1877 __IO uint32_t tmpreg; \ 1878 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1879 /* Delay after an RCC peripheral clock enabling */ \ 1880 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ 1881 UNUSED(tmpreg); \ 1882 } while(0) 1883 1884 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1885 __IO uint32_t tmpreg; \ 1886 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1887 /* Delay after an RCC peripheral clock enabling */ \ 1888 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1889 UNUSED(tmpreg); \ 1890 } while(0) 1891 1892 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1893 __IO uint32_t tmpreg; \ 1894 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1895 /* Delay after an RCC peripheral clock enabling */ \ 1896 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1897 UNUSED(tmpreg); \ 1898 } while(0) 1899 1900 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1901 __IO uint32_t tmpreg; \ 1902 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1903 /* Delay after an RCC peripheral clock enabling */ \ 1904 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1905 UNUSED(tmpreg); \ 1906 } while(0) 1907 1908 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1909 __IO uint32_t tmpreg; \ 1910 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1911 /* Delay after an RCC peripheral clock enabling */ \ 1912 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1913 UNUSED(tmpreg); \ 1914 } while(0) 1915 1916 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1917 __IO uint32_t tmpreg; \ 1918 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1919 /* Delay after an RCC peripheral clock enabling */ \ 1920 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1921 UNUSED(tmpreg); \ 1922 } while(0) 1923 1924 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1925 __IO uint32_t tmpreg; \ 1926 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1927 /* Delay after an RCC peripheral clock enabling */ \ 1928 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ 1929 UNUSED(tmpreg); \ 1930 } while(0) 1931 1932 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1933 __IO uint32_t tmpreg; \ 1934 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1935 /* Delay after an RCC peripheral clock enabling */ \ 1936 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ 1937 UNUSED(tmpreg); \ 1938 } while(0) 1939 1940 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1941 __IO uint32_t tmpreg; \ 1942 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1943 /* Delay after an RCC peripheral clock enabling */ \ 1944 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1945 UNUSED(tmpreg); \ 1946 } while(0) 1947 1948 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 1949 __IO uint32_t tmpreg; \ 1950 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1951 /* Delay after an RCC peripheral clock enabling */ \ 1952 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1953 UNUSED(tmpreg); \ 1954 } while(0) 1955 1956 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) 1957 1958 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) 1959 1960 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1961 1962 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1963 1964 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1965 1966 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1967 1968 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1969 1970 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) 1971 1972 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) 1973 1974 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1975 1976 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1977 /** 1978 * @} 1979 */ 1980 1981 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1982 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1983 * @note After reset, the peripheral clock (used for registers read/write access) 1984 * is disabled and the application software has to enable this clock before 1985 * using it. 1986 * @{ 1987 */ 1988 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 1989 1990 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 1991 1992 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 1993 1994 #define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) 1995 1996 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1997 1998 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1999 2000 #if defined(JPEG) 2001 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) 2002 #endif /* JPEG */ 2003 2004 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 2005 2006 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 2007 2008 #if defined(DMA2D) 2009 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) 2010 #endif /* DMA2D */ 2011 2012 #if defined(GFXMMU) 2013 #define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) 2014 #endif /* GFXMMU */ 2015 2016 #if defined(GPU2D) 2017 #define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) 2018 #endif /* GPU2D */ 2019 2020 #if defined(DCACHE2) 2021 #define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) 2022 #endif /* DCACHE2 */ 2023 2024 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) 2025 2026 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) 2027 2028 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 2029 2030 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 2031 2032 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 2033 2034 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 2035 2036 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 2037 2038 #define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) 2039 2040 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 2041 2042 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 2043 2044 #if defined(JPEG) 2045 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) 2046 #endif /* JPEG */ 2047 2048 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 2049 2050 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 2051 2052 #if defined (DMA2D) 2053 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) 2054 #endif /* DMA2D */ 2055 2056 #if defined(GFXMMU) 2057 #define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) 2058 #endif /* GFXMMU */ 2059 2060 #if defined(GPU2D) 2061 #define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) 2062 #endif /* GPU2D */ 2063 2064 #if defined(DCACHE2) 2065 #define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) 2066 #endif /* DCACHE2 */ 2067 2068 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) 2069 2070 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) 2071 2072 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 2073 2074 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 2075 /** 2076 * @} 2077 */ 2078 2079 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 2080 * @brief Check whether the AHB2 peripheral clock is enabled or not. 2081 * @note After reset, the peripheral clock (used for registers read/write access) 2082 * is disabled and the application software has to enable this clock before 2083 * using it. 2084 * @{ 2085 */ 2086 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) 2087 2088 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) 2089 2090 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) 2091 2092 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) 2093 2094 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) 2095 2096 #if defined(GPIOF) 2097 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) 2098 #endif /* GPIOF */ 2099 2100 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) 2101 2102 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) 2103 2104 #if defined(GPIOI) 2105 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) 2106 #endif /* GPIOI */ 2107 2108 #if defined(GPIOJ) 2109 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) 2110 #endif /* GPIOJ */ 2111 2112 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) 2113 2114 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) 2115 2116 #if defined(USB_OTG_HS) 2117 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 2118 #endif /* USB_OTG_HS */ 2119 2120 #if defined(USB_OTG_FS) 2121 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) 2122 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ 2123 #endif /* USB_OTG_FS */ 2124 2125 #if defined(AES) 2126 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) 2127 #endif /* AES */ 2128 2129 #if defined(HASH) 2130 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) 2131 #endif /* HASH */ 2132 2133 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) 2134 2135 #if defined(PKA) 2136 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) 2137 #endif /* PKA */ 2138 2139 #if defined(SAES) 2140 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) 2141 #endif /* SAES */ 2142 2143 #if defined(OCTOSPIM) 2144 #define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) 2145 #endif /* OCTOSPIM */ 2146 2147 #if defined(OTFDEC1) 2148 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) 2149 #endif /* OTFDEC1 */ 2150 2151 #if defined(OTFDEC2) 2152 #define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) 2153 #endif /* OTFDEC2 */ 2154 2155 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) 2156 2157 #if defined(SDMMC2) 2158 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) 2159 #endif /* SDMMC2 */ 2160 2161 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) 2162 2163 #if defined (SRAM3_BASE) 2164 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) 2165 #endif /* SRAM3_BASE */ 2166 2167 #if defined(FMC_BASE) 2168 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) 2169 #endif /* FMC_BASE */ 2170 2171 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) 2172 2173 #if defined(OCTOSPI2) 2174 #define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) 2175 #endif /* OCTOSPI2 */ 2176 2177 #if defined(HSPI1) 2178 #define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) 2179 #endif /* HSPI1 */ 2180 2181 #if defined (SRAM6_BASE) 2182 #define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) 2183 #endif /* SRAM6_BASE */ 2184 2185 #if defined (SRAM5_BASE) 2186 #define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) 2187 #endif /* SRAM5_BASE */ 2188 2189 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) 2190 2191 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) 2192 2193 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) 2194 2195 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) 2196 2197 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) 2198 2199 #if defined(GPIOF) 2200 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) 2201 #endif /* GPIOF */ 2202 2203 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) 2204 2205 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) 2206 2207 #if defined(GPIOI) 2208 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) 2209 #endif /* GPIOI */ 2210 2211 #if defined(GPIOJ) 2212 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) 2213 #endif /* GPIOJ */ 2214 2215 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) 2216 2217 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) 2218 2219 #if defined(USB_OTG_HS) 2220 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 2221 #endif /* USB_OTG_HS */ 2222 2223 #if defined(USB_OTG_FS) 2224 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) 2225 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ 2226 #endif /* USB_OTG_FS */ 2227 2228 #if defined(AES) 2229 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) 2230 #endif /* AES */ 2231 2232 #if defined(HASH) 2233 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) 2234 #endif /* HASH */ 2235 2236 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) 2237 2238 #if defined(PKA) 2239 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) 2240 #endif /* PKA */ 2241 2242 #if defined(SAES) 2243 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) 2244 #endif /* SAES */ 2245 2246 #if defined(OCTOSPIM) 2247 #define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) 2248 #endif /* OCTOSPIM */ 2249 2250 #if defined(OTFDEC1) 2251 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) 2252 #endif /* OTFDEC1 */ 2253 2254 #if defined (OTFDEC2) 2255 #define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) 2256 #endif /* OTFDEC2 */ 2257 2258 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) 2259 2260 #if defined (SDMMC2) 2261 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) 2262 #endif /* SDMMC2 */ 2263 2264 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) 2265 2266 #if defined (SRAM3_BASE) 2267 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) 2268 #endif /* SRAM3_BASE */ 2269 2270 #if defined(FMC_BASE) 2271 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) 2272 #endif /* FMC_BASE */ 2273 2274 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) 2275 2276 #if defined (OCTOSPI2) 2277 #define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) 2278 #endif /* OCTOSPI2 */ 2279 2280 #if defined(HSPI1) 2281 #define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) 2282 #endif /* HSPI1 */ 2283 2284 #if defined (SRAM6_BASE) 2285 #define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) 2286 #endif /* SRAM6_BASE */ 2287 2288 #if defined (SRAM5_BASE) 2289 #define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) 2290 #endif /* SRAM5_BASE */ 2291 /** 2292 * @} 2293 */ 2294 2295 /** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 2296 * @brief Check whether the AHB3 peripheral clock is enabled or not. 2297 * @note After reset, the peripheral clock (used for registers read/write access) 2298 * is disabled and the application software has to enable this clock before 2299 * using it. 2300 * @{ 2301 */ 2302 #define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) 2303 2304 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) 2305 2306 #define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) 2307 2308 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) 2309 2310 #define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) 2311 2312 #define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) 2313 2314 #define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) 2315 2316 #define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) 2317 2318 #define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) 2319 2320 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) 2321 2322 #define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) 2323 2324 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) 2325 2326 #define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) 2327 2328 #define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) 2329 2330 #define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) 2331 2332 #define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) 2333 2334 /** 2335 * @} 2336 */ 2337 2338 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2339 * @brief Check whether the APB1 peripheral clock is enabled or not. 2340 * @note After reset, the peripheral clock (used for registers read/write access) 2341 * is disabled and the application software has to enable this clock before 2342 * using it. 2343 * @{ 2344 */ 2345 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 2346 2347 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 2348 2349 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 2350 2351 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 2352 2353 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 2354 2355 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 2356 2357 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 2358 2359 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 2360 2361 #if defined(USART2) 2362 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 2363 #endif /* USART2 */ 2364 2365 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 2366 2367 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 2368 2369 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 2370 2371 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 2372 2373 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 2374 2375 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 2376 2377 #if defined(USART6) 2378 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) 2379 #endif /* USART6 */ 2380 2381 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 2382 2383 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 2384 2385 #if defined(I2C5) 2386 #define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) 2387 #endif /* I2C5 */ 2388 2389 #if defined(I2C6) 2390 #define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) 2391 #endif /* I2C6 */ 2392 2393 #define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) 2394 2395 #if defined (UCPD1) 2396 #define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) 2397 #endif /* UCPD1 */ 2398 2399 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 2400 2401 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 2402 2403 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 2404 2405 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 2406 2407 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 2408 2409 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 2410 2411 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 2412 2413 #if defined(USART2) 2414 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 2415 #endif /* USART2 */ 2416 2417 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 2418 2419 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 2420 2421 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 2422 2423 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 2424 2425 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 2426 2427 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 2428 2429 #if defined(USART6) 2430 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) 2431 #endif /* USART6 */ 2432 2433 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 2434 2435 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 2436 2437 #if defined(I2C5) 2438 #define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) 2439 #endif /* I2C5 */ 2440 2441 #if defined(I2C6) 2442 #define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) 2443 #endif /* I2C6 */ 2444 2445 #define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) 2446 2447 #if defined(UCPD1) 2448 #define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) 2449 #endif /* UCPD1 */ 2450 2451 /** 2452 * @} 2453 */ 2454 2455 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2456 * @brief Check whether the APB2 peripheral clock is enabled or not. 2457 * @note After reset, the peripheral clock (used for registers read/write access) 2458 * is disabled and the application software has to enable this clock before 2459 * using it. 2460 * @{ 2461 */ 2462 2463 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2464 2465 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2466 2467 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2468 2469 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2470 2471 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2472 2473 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2474 2475 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2476 2477 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2478 2479 #if defined (SAI2) 2480 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2481 #endif /* SAI2 */ 2482 2483 #if defined (USB_DRD_FS) 2484 #define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) 2485 #endif /* USB_DRD_FS */ 2486 2487 #if defined(GFXTIM) 2488 #define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) 2489 #endif /* GFXTIM */ 2490 2491 #if defined(LTDC) 2492 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) 2493 #endif /* LTDC */ 2494 2495 #if defined(DSI) 2496 #define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) 2497 #endif /* DSI */ 2498 2499 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2500 2501 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2502 2503 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2504 2505 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2506 2507 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2508 2509 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2510 2511 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2512 2513 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2514 2515 #if defined (SAI2) 2516 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2517 #endif /* SAI2 */ 2518 2519 #if defined (USB_DRD_FS) 2520 #define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) 2521 #endif /* USB_DRD_FS */ 2522 2523 #if defined(GFXTIM) 2524 #define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) 2525 #endif /* GFXTIM */ 2526 2527 #if defined(LTDC) 2528 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) 2529 #endif /* LTDC */ 2530 2531 #if defined(DSI) 2532 #define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) 2533 #endif /* DSI */ 2534 2535 /** 2536 * @} 2537 */ 2538 2539 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2540 * @brief Check whether the APB3 peripheral clock is enabled or not. 2541 * @note After reset, the peripheral clock (used for registers read/write access) 2542 * is disabled and the application software has to enable this clock before 2543 * using it. 2544 * @{ 2545 */ 2546 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) 2547 2548 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) 2549 2550 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2551 2552 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2553 2554 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2555 2556 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2557 2558 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2559 2560 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) 2561 2562 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) 2563 2564 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2565 2566 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2567 2568 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) 2569 2570 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) 2571 2572 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2573 2574 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2575 2576 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2577 2578 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2579 2580 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2581 2582 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) 2583 2584 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) 2585 2586 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2587 2588 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2589 /** 2590 * @} 2591 */ 2592 2593 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2594 * @brief Force or release AHB1 peripheral reset. 2595 * @{ 2596 */ 2597 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) 2598 2599 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2600 2601 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2602 2603 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2604 2605 #define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2606 2607 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2608 2609 #if defined(JPEG) 2610 #define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) 2611 #endif /* JPEG */ 2612 2613 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2614 2615 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2616 2617 #if defined(DMA2D) 2618 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2619 #endif /* DMA2D */ 2620 2621 #if defined(GFXMMU) 2622 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2623 #endif /* GFXMMU */ 2624 2625 #if defined(GPU2D) 2626 #define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) 2627 #endif /* GPU2D */ 2628 2629 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2630 2631 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2632 2633 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2634 2635 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2636 2637 #define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) 2638 2639 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2640 2641 #if defined(JPEG) 2642 #define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) 2643 #endif /* JPEG */ 2644 2645 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 2646 2647 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2648 2649 #if defined(DMA2D) 2650 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) 2651 #endif /* DMA2D */ 2652 2653 #if defined(GFXMMU) 2654 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) 2655 #endif /* GFXMMU */ 2656 2657 #if defined(GPU2D) 2658 #define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) 2659 #endif /* GPU2D */ 2660 2661 /** 2662 * @} 2663 */ 2664 2665 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2666 * @brief Force or release AHB2 peripheral reset. 2667 * @{ 2668 */ 2669 #define __HAL_RCC_AHB2_FORCE_RESET() do{\ 2670 WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ 2671 WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ 2672 }while(0) 2673 2674 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2675 2676 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2677 2678 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2679 2680 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2681 2682 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2683 2684 #if defined(GPIOF) 2685 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2686 #endif /* GPIOF */ 2687 2688 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2689 2690 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2691 2692 #if defined(GPIOI) 2693 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2694 #endif /* GPIOI */ 2695 2696 #if defined(GPIOJ) 2697 #define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) 2698 #endif /* GPIOJ */ 2699 2700 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) 2701 2702 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2703 2704 #if defined(USB_OTG_HS) 2705 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2706 #endif /* USB_OTG_HS */ 2707 2708 #if defined(USB_OTG_FS) 2709 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2710 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ 2711 #endif /* USB_OTG_FS */ 2712 2713 #if defined(AES) 2714 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2715 #endif /* AES */ 2716 2717 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2718 2719 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2720 2721 #if defined(PKA) 2722 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2723 #endif /* PKA */ 2724 2725 #if defined(SAES) 2726 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2727 #endif /* SAES */ 2728 2729 #if defined(OCTOSPIM) 2730 #define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2731 #endif /* OCTOSPIM */ 2732 2733 #if defined(OTFDEC1) 2734 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2735 #endif /* OTFDEC1 */ 2736 2737 #if defined(OTFDEC2) 2738 #define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2739 #endif /* OTFDEC2 */ 2740 2741 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2742 2743 #if defined(SDMMC2) 2744 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2745 #endif /* SDMMC2 */ 2746 2747 #if defined(FMC_BASE) 2748 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2749 #endif /* FMC_BASE */ 2750 2751 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2752 2753 #if defined (OCTOSPI2) 2754 #define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2755 #endif /* OCTOSPI2 */ 2756 2757 #if defined(HSPI1) 2758 #define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) 2759 #endif /* HSPI1 */ 2760 2761 #define __HAL_RCC_AHB2_RELEASE_RESET() do{\ 2762 WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ 2763 WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ 2764 }while(0) 2765 2766 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) 2767 2768 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) 2769 2770 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) 2771 2772 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) 2773 2774 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) 2775 2776 #if defined(GPIOF) 2777 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) 2778 #endif /* GPIOF */ 2779 2780 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) 2781 2782 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) 2783 2784 #if defined(GPIOI) 2785 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) 2786 #endif /* GPIOI */ 2787 2788 #if defined(GPIOJ) 2789 #define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) 2790 #endif /* GPIOJ */ 2791 2792 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) 2793 2794 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) 2795 2796 #if defined(USB_OTG_HS) 2797 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2798 #endif /* USB_OTG_HS */ 2799 2800 #if defined(USB_OTG_FS) 2801 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) 2802 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ 2803 #endif /* USB_OTG_FS */ 2804 2805 #if defined(AES) 2806 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) 2807 #endif /* AES */ 2808 2809 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) 2810 2811 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) 2812 2813 #if defined(PKA) 2814 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) 2815 #endif /* PKA */ 2816 2817 #if defined(SAES) 2818 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) 2819 #endif /* SAES */ 2820 2821 #if defined(OCTOSPIM) 2822 #define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) 2823 #endif /* OCTOSPIM */ 2824 2825 #if defined(OTFDEC1) 2826 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) 2827 #endif /* OTFDEC1 */ 2828 2829 #if defined(OTFDEC2) 2830 #define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) 2831 #endif /* OTFDEC2 */ 2832 2833 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) 2834 2835 #if defined(SDMMC2) 2836 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) 2837 #endif /* SDMMC2 */ 2838 2839 #if defined(FMC_BASE) 2840 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) 2841 #endif /* FMC_BASE */ 2842 2843 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) 2844 2845 #if defined(OCTOSPI2) 2846 #define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) 2847 #endif /* OCTOSPI2 */ 2848 2849 #if defined(HSPI1) 2850 #define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) 2851 #endif /* HSPI1 */ 2852 2853 /** 2854 * @} 2855 */ 2856 2857 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 2858 * @brief Force or release AHB3 peripheral reset. 2859 * @{ 2860 */ 2861 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) 2862 2863 #define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2864 2865 #define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2866 2867 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2868 2869 #define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2870 2871 #define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2872 2873 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 2874 2875 #define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) 2876 2877 #define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) 2878 2879 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) 2880 2881 #define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) 2882 2883 #define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) 2884 2885 /** 2886 * @} 2887 */ 2888 2889 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 2890 * @brief Force or release APB1 peripheral reset. 2891 * @{ 2892 */ 2893 2894 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 2895 WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ 2896 WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ 2897 } while(0) 2898 2899 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2900 2901 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2902 2903 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2904 2905 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2906 2907 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2908 2909 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2910 2911 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2912 2913 #if defined (USART2) 2914 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2915 #endif /* USART2 */ 2916 2917 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2918 2919 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2920 2921 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2922 2923 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2924 2925 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2926 2927 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2928 2929 #if defined(USART6) 2930 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) 2931 #endif /* USART6 */ 2932 2933 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2934 2935 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2936 2937 #if defined(I2C5) 2938 #define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) 2939 #endif /* I2C5 */ 2940 2941 #if defined(I2C6) 2942 #define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) 2943 #endif /* I2C6 */ 2944 2945 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 2946 2947 #if defined(UCPD1) 2948 #define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 2949 #endif /* UCPD1 */ 2950 2951 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 2952 WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ 2953 WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ 2954 } while(0) 2955 2956 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 2957 2958 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 2959 2960 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 2961 2962 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 2963 2964 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 2965 2966 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 2967 2968 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 2969 2970 #if defined(USART2) 2971 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 2972 #endif /* USART2 */ 2973 2974 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 2975 2976 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 2977 2978 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 2979 2980 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 2981 2982 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 2983 2984 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 2985 2986 #if defined(USART6) 2987 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) 2988 #endif /* USART6 */ 2989 2990 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 2991 2992 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 2993 2994 #if defined(I2C5) 2995 #define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) 2996 #endif /* I2C5 */ 2997 2998 #if defined(I2C6) 2999 #define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) 3000 #endif /* I2C6 */ 3001 3002 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 3003 3004 #if defined(UCPD1) 3005 #define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 3006 #endif /* UCPD1 */ 3007 3008 /** 3009 * @} 3010 */ 3011 3012 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 3013 * @brief Force or release APB2 peripheral reset. 3014 * @{ 3015 */ 3016 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) 3017 3018 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3019 3020 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3021 3022 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3023 3024 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3025 3026 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3027 3028 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3029 3030 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3031 3032 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3033 3034 #if defined(SAI2) 3035 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3036 #endif /* SAI2 */ 3037 3038 #if defined(USB_DRD_FS) 3039 #define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3040 #endif /* USB_DRD_FS */ 3041 3042 #if defined(GFXTIM) 3043 #define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) 3044 #endif /* GFXTIM */ 3045 3046 #if defined(LTDC) 3047 #define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 3048 #endif /* LTDC */ 3049 3050 #if defined(DSI) 3051 #define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) 3052 #endif /* DSI */ 3053 3054 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 3055 3056 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3057 3058 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3059 3060 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3061 3062 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3063 3064 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3065 3066 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3067 3068 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3069 3070 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3071 3072 #if defined(SAI2) 3073 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3074 #endif /* SAI2 */ 3075 3076 #if defined(USB_DRD_FS) 3077 #define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3078 #endif /* USB_DRD_FS */ 3079 3080 #if defined(GFXTIM) 3081 #define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) 3082 #endif /* GFXTIM */ 3083 3084 #if defined(LTDC) 3085 #define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) 3086 #endif /* LTDC */ 3087 3088 #if defined(DSI) 3089 #define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) 3090 #endif /* DSI */ 3091 3092 /** 3093 * @} 3094 */ 3095 3096 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 3097 * @brief Force or release APB3 peripheral reset. 3098 * @{ 3099 */ 3100 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) 3101 3102 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 3103 3104 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 3105 3106 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3107 3108 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3109 3110 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3111 3112 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3113 3114 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3115 3116 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 3117 3118 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 3119 3120 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3121 3122 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 3123 3124 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) 3125 3126 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) 3127 3128 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3129 3130 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3131 3132 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3133 3134 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3135 3136 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3137 3138 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) 3139 3140 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) 3141 3142 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3143 3144 /** 3145 * @} 3146 */ 3147 3148 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 3149 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. 3150 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3151 * power consumption. 3152 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3153 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3154 * is enabled only when a peripheral requests AHB clock. 3155 * @{ 3156 */ 3157 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 3158 3159 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 3160 3161 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 3162 3163 #define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 3164 3165 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 3166 3167 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 3168 3169 #if defined(JPEG) 3170 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) 3171 #endif /* JPEG */ 3172 3173 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 3174 3175 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 3176 3177 #if defined(DMA2D) 3178 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 3179 #endif /* DMA2D */ 3180 3181 #if defined(GFXMMU) 3182 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 3183 #endif /* GFXMMU */ 3184 3185 #if defined(GPU2D) 3186 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) 3187 #endif /* GPU2D */ 3188 3189 #if defined(DCACHE2) 3190 #define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) 3191 #endif /* DCACHE2 */ 3192 3193 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 3194 3195 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 3196 3197 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 3198 3199 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 3200 3201 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 3202 3203 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) 3204 3205 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) 3206 3207 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) 3208 3209 #define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) 3210 3211 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 3212 3213 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 3214 3215 #if defined(JPEG) 3216 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) 3217 #endif /* JPEG */ 3218 3219 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 3220 3221 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) 3222 3223 #if defined(DMA2D) 3224 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) 3225 #endif /* DMA2D */ 3226 3227 #if defined(GFXMMU) 3228 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) 3229 #endif /* GFXMMU */ 3230 3231 #if defined(GPU2D) 3232 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) 3233 #endif /* GPU2D */ 3234 3235 #if defined(DCACHE2) 3236 #define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) 3237 #endif /* DCACHE2 */ 3238 3239 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) 3240 3241 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) 3242 3243 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 3244 3245 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) 3246 3247 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 3248 3249 /** 3250 * @} 3251 */ 3252 3253 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 3254 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. 3255 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3256 * power consumption. 3257 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3258 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3259 * is enabled only when a peripheral requests AHB clock. 3260 * @{ 3261 */ 3262 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 3263 3264 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 3265 3266 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 3267 3268 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 3269 3270 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 3271 3272 #if defined(GPIOF) 3273 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 3274 #endif /* GPIOF */ 3275 3276 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 3277 3278 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 3279 3280 #if defined(GPIOI) 3281 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 3282 #endif /* GPIOI */ 3283 3284 #if defined(GPIOJ) 3285 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) 3286 #endif /* GPIOJ */ 3287 3288 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) 3289 3290 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 3291 3292 #if defined(USB_OTG_HS) 3293 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3294 #endif /* USB_OTG_HS */ 3295 3296 #if defined(USB_OTG_FS) 3297 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3298 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ 3299 #endif /* USB_OTG_FS */ 3300 3301 #if defined(RCC_AHB2SMENR1_USBPHYCSMEN) 3302 #define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) 3303 #endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ 3304 3305 #if defined(AES) 3306 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) 3307 #endif /* AES */ 3308 3309 #if defined(HASH) 3310 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 3311 #endif /* HASH */ 3312 3313 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 3314 3315 #if defined(PKA) 3316 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 3317 #endif /* PKA */ 3318 3319 #if defined(SAES) 3320 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 3321 #endif /* SAES */ 3322 3323 #if defined(OCTOSPIM) 3324 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 3325 #endif /* OCTOSPIM */ 3326 3327 #if defined(OTFDEC1) 3328 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 3329 #endif /* OTFDEC1 */ 3330 3331 #if defined(OTFDEC2) 3332 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 3333 #endif /* OTFDEC2 */ 3334 3335 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 3336 3337 #if defined(SDMMC2) 3338 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 3339 #endif /* SDMMC2 */ 3340 3341 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 3342 3343 #if defined(SRAM3_BASE) 3344 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 3345 #endif /* SRAM3_BASE */ 3346 3347 #if defined(FMC_BASE) 3348 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 3349 #endif /* FMC_BASE */ 3350 3351 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 3352 3353 #if defined(OCTOSPI2) 3354 #define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 3355 #endif /* OCTOSPI2 */ 3356 3357 #if defined(HSPI1) 3358 #define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) 3359 #endif /* HSPI1 */ 3360 3361 #if defined(SRAM6_BASE) 3362 #define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) 3363 #endif /* SRAM6_BASE */ 3364 3365 #if defined(SRAM5_BASE) 3366 #define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) 3367 #endif /* SRAM5_BASE */ 3368 3369 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) 3370 3371 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) 3372 3373 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) 3374 3375 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) 3376 3377 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) 3378 3379 #if defined(GPIOF) 3380 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) 3381 #endif /* GPIOF */ 3382 3383 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) 3384 3385 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) 3386 3387 #if defined(GPIOI) 3388 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) 3389 #endif /* GPIOI */ 3390 3391 #if defined(GPIOJ) 3392 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) 3393 #endif /* GPIOJ */ 3394 3395 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) 3396 3397 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) 3398 3399 #if defined(USB_OTG_HS) 3400 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3401 #endif /* USB_OTG_HS */ 3402 3403 #if defined(USB_OTG_FS) 3404 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) 3405 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ 3406 #endif /* USB_OTG_FS */ 3407 3408 #if defined(RCC_AHB2SMENR1_USBPHYCSMEN) 3409 #define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) 3410 #endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ 3411 3412 #if defined(AES) 3413 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) 3414 #endif /* AES */ 3415 3416 #if defined(HASH) 3417 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) 3418 #endif /* HASH */ 3419 3420 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) 3421 3422 #if defined(PKA) 3423 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) 3424 #endif /* PKA */ 3425 3426 #if defined(SAES) 3427 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) 3428 #endif /* SAES */ 3429 3430 #if defined(OCTOSPIM) 3431 #define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) 3432 #endif /* OCTOSPIM */ 3433 3434 #if defined(OTFDEC1) 3435 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) 3436 #endif /* OTFDEC1 */ 3437 3438 #if defined(OTFDEC2) 3439 #define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) 3440 #endif /* OTFDEC2 */ 3441 3442 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) 3443 3444 #if defined(SDMMC2) 3445 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) 3446 #endif /* SDMMC2 */ 3447 3448 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) 3449 3450 #if defined(SRAM3_BASE) 3451 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) 3452 #endif /* SRAM3_BASE */ 3453 3454 #if defined(FMC_BASE) 3455 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) 3456 #endif /* FMC_BASE */ 3457 3458 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) 3459 3460 #if defined(OCTOSPI2) 3461 #define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) 3462 #endif /* OCTOSPI2 */ 3463 3464 #if defined(HSPI1) 3465 #define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) 3466 #endif /* HSPI1 */ 3467 3468 #if defined(SRAM6_BASE) 3469 #define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) 3470 #endif /* SRAM6_BASE */ 3471 3472 #if defined(SRAM5_BASE) 3473 #define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) 3474 #endif /* SRAM5_BASE */ 3475 3476 /** 3477 * @} 3478 */ 3479 3480 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable 3481 * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. 3482 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3483 * power consumption. 3484 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3485 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3486 * is enabled only when a peripheral requests AHB clock. 3487 * @{ 3488 */ 3489 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 3490 3491 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 3492 3493 #define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 3494 3495 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 3496 3497 #define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 3498 3499 #define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 3500 3501 #define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 3502 3503 #define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 3504 3505 #define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) 3506 3507 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) 3508 3509 #define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) 3510 3511 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) 3512 3513 #define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) 3514 3515 #define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) 3516 3517 #define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) 3518 3519 #define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) 3520 3521 /** 3522 * @} 3523 */ 3524 3525 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3526 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. 3527 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3528 * power consumption. 3529 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3530 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3531 * is enabled only when a peripheral requests APB clock. 3532 * @{ 3533 */ 3534 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3535 3536 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3537 3538 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3539 3540 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3541 3542 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3543 3544 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3545 3546 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3547 3548 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3549 3550 #if defined(USART2) 3551 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3552 #endif /* USART2 */ 3553 3554 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3555 3556 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3557 3558 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3559 3560 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3561 3562 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3563 3564 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3565 3566 #if defined(USART6) 3567 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) 3568 #endif /* USART6 */ 3569 3570 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3571 3572 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3573 3574 #if defined(I2C5) 3575 #define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) 3576 #endif /* I2C5 */ 3577 3578 #if defined(I2C6) 3579 #define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) 3580 #endif /* I2C6 */ 3581 3582 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 3583 3584 #if defined(UCPD1) 3585 #define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 3586 #endif /* UCPD1 */ 3587 3588 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 3589 3590 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 3591 3592 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 3593 3594 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 3595 3596 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 3597 3598 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 3599 3600 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 3601 3602 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 3603 3604 #if defined(USART2) 3605 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 3606 #endif /* USART2 */ 3607 3608 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 3609 3610 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 3611 3612 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 3613 3614 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 3615 3616 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 3617 3618 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 3619 3620 #if defined(USART6) 3621 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) 3622 #endif /* USART6 */ 3623 3624 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 3625 3626 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 3627 3628 #if defined(I2C5) 3629 #define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) 3630 #endif /* I2C5 */ 3631 3632 #if defined(I2C6) 3633 #define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) 3634 #endif /* I2C6 */ 3635 3636 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 3637 3638 #if defined(UCPD1) 3639 #define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 3640 #endif /* UCPD1 */ 3641 3642 /** 3643 * @} 3644 */ 3645 3646 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3647 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. 3648 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3649 * power consumption. 3650 * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. 3651 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3652 * is enabled only when a peripheral requests APB clock. 3653 * @{ 3654 */ 3655 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3656 3657 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3658 3659 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3660 3661 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3662 3663 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3664 3665 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3666 3667 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3668 3669 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3670 3671 #if defined(SAI2) 3672 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3673 #endif /* SAI2 */ 3674 3675 #if defined(USB_DRD_FS) 3676 #define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) 3677 #endif /* USB_DRD_FS */ 3678 3679 #if defined(GFXTIM) 3680 #define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) 3681 #endif /* GFXTIM */ 3682 3683 #if defined(LTDC) 3684 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3685 #endif /* LTDC */ 3686 3687 #if defined(DSI) 3688 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) 3689 #endif /* DSI */ 3690 3691 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 3692 3693 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 3694 3695 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 3696 3697 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 3698 3699 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 3700 3701 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 3702 3703 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 3704 3705 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 3706 3707 #if defined(SAI2) 3708 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 3709 #endif /* SAI2 */ 3710 3711 #if defined(USB_DRD_FS) 3712 #define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) 3713 #endif /* USB_DRD_FS */ 3714 3715 #if defined(GFXTIM) 3716 #define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) 3717 #endif /* GFXTIM */ 3718 3719 #if defined(LTDC) 3720 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) 3721 #endif /* LTDC */ 3722 3723 #if defined(DSI) 3724 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) 3725 #endif /* DSI */ 3726 3727 /** 3728 * @} 3729 */ 3730 3731 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 3732 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. 3733 * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce 3734 * power consumption. 3735 * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. 3736 * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock 3737 * is enabled only when a peripheral requests APB clock. 3738 * @{ 3739 */ 3740 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 3741 3742 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 3743 3744 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 3745 3746 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 3747 3748 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 3749 3750 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 3751 3752 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 3753 3754 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 3755 3756 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 3757 3758 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 3759 3760 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 3761 3762 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) 3763 3764 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) 3765 3766 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) 3767 3768 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) 3769 3770 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) 3771 3772 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) 3773 3774 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) 3775 3776 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) 3777 3778 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) 3779 3780 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) 3781 3782 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) 3783 3784 /** 3785 * @} 3786 */ 3787 3788 /** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN 3789 * @note After reset, peripheral clock is disabled when CPUs are in CSTOP 3790 * @{ 3791 */ 3792 #define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 3793 3794 #define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 3795 3796 #define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 3797 3798 #define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 3799 3800 #define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 3801 3802 #define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 3803 3804 #define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 3805 3806 #define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 3807 3808 #define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 3809 3810 #define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 3811 3812 #define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 3813 3814 #define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 3815 3816 #define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 3817 3818 #define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 3819 3820 #define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 3821 3822 #define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 3823 3824 #define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) 3825 3826 #define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) 3827 3828 #define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) 3829 3830 #define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) 3831 3832 #define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) 3833 3834 #define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) 3835 3836 #define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) 3837 3838 #define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) 3839 3840 #define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) 3841 3842 #define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) 3843 3844 #define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) 3845 3846 #define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) 3847 3848 #define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) 3849 3850 #define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) 3851 3852 #define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) 3853 3854 #define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) 3855 3856 /** 3857 * @} 3858 */ 3859 3860 3861 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 3862 * @{ 3863 */ 3864 3865 /** @brief Macros to force or release the Backup domain reset. 3866 * @note This function resets the RTC peripheral (including the backup registers) 3867 * and the RTC clock source selection in RCC_CSR register. 3868 * @note The BKPSRAM is not affected by this reset. 3869 * @retval None 3870 */ 3871 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3872 3873 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 3874 3875 /** 3876 * @} 3877 */ 3878 3879 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 3880 * @{ 3881 */ 3882 3883 /** @brief Macros to enable or disable the RTC clock. 3884 * @note As the RTC is in the Backup domain and write access is denied to 3885 * this domain after reset, you have to enable write access using 3886 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 3887 * (to be done once after reset). 3888 * @note These macros must be used after the RTC clock source was selected. 3889 * @retval None 3890 */ 3891 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3892 3893 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 3894 3895 /** 3896 * @} 3897 */ 3898 3899 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 3900 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 3901 * It is used (enabled by hardware) as system clock source after startup 3902 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 3903 * of the HSE used directly or indirectly as system clock (if the Clock 3904 * Security System CSS is enabled). 3905 * @note HSI can not be stopped if it is used as system clock source. In this case, 3906 * you have to select another source of the system clock then stop the HSI. 3907 * @note After enabling the HSI, the application software should wait on HSIRDY 3908 * flag to be set indicating that HSI clock is stable and can be used as 3909 * system clock source. 3910 * This parameter can be: ENABLE or DISABLE. 3911 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 3912 * clock cycles. 3913 * @retval None 3914 */ 3915 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 3916 3917 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 3918 3919 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 3920 * @note The calibration is used to compensate for the variations in voltage 3921 * and temperature that influence the frequency of the internal HSI RC. 3922 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 3923 * (default is RCC_HSICALIBRATION_DEFAULT). 3924 * This parameter must be a number between 0 and 0x20. 3925 * @retval None 3926 */ 3927 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 3928 MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) 3929 3930 /** 3931 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 3932 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3933 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 3934 * speed because of the HSI startup time. 3935 * @note The enable of this function has not effect on the HSION bit. 3936 * This parameter can be: ENABLE or DISABLE. 3937 * @retval None 3938 */ 3939 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 3940 3941 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 3942 3943 /** 3944 * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) 3945 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 3946 * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication 3947 * speed because of the MSIK startup time. 3948 * @note The enable of this function has not effect on the MSIKON bit. 3949 * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. 3950 * This parameter can be: ENABLE or DISABLE. 3951 * @retval None 3952 */ 3953 #define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) 3954 3955 #define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) 3956 3957 /** 3958 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 3959 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 3960 * It is used (enabled by hardware) as system clock source after 3961 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 3962 * of failure of the HSE used directly or indirectly as system clock 3963 * (if the Clock Security System CSS is enabled). 3964 * @note MSI can not be stopped if it is used as system clock source. 3965 * In this case, you have to select another source of the system 3966 * clock then stop the MSI. 3967 * @note After enabling the MSI, the application software should wait on 3968 * MSIRDY flag to be set indicating that MSI clock is stable and can 3969 * be used as system clock source. 3970 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 3971 * clock cycles. 3972 * @retval None 3973 */ 3974 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) 3975 3976 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) 3977 3978 /** 3979 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 3980 * @note After restart from Reset , the MSI clock is around 4 MHz. 3981 * After stop the startup clock can be MSI (at any of its possible 3982 * frequencies, the one that was used before entering stop mode) or HSI. 3983 * After Standby its frequency can be selected between 4 possible values 3984 * (1, 3.072, 4 or 8 MHz). 3985 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 3986 * (MSIRDY=1). 3987 * @note The MSI clock range after reset can be modified on the fly. 3988 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 3989 * This parameter must be one of the following values: 3990 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 3991 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 3992 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 3993 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 3994 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 3995 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 3996 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 3997 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 3998 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 3999 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4000 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4001 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4002 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4003 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4004 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4005 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4006 * @retval None 4007 */ 4008 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 4009 do { \ 4010 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4011 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ 4012 } while(0) 4013 4014 /** 4015 * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 4016 * @note After restart from Reset , the MSIK clock is around 4 MHz. 4017 * After stop the startup clock can be MSIK (at any of its possible 4018 * frequencies, the one that was used before entering stop mode) or HSI. 4019 * After Standby its frequency can be selected between 4 possible values 4020 * (1, 3.072, 4 or 8 MHz). 4021 * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready 4022 * (MSIKRDY=1). 4023 * @note The MSI clock range after reset can be modified on the fly. 4024 * @param __MSIKRANGEVALUE__: specifies the MSI clock range. 4025 * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz 4026 * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz 4027 * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz 4028 * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz 4029 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 4030 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 4031 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 4032 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 4033 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 4034 * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz 4035 * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz 4036 * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz 4037 * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz 4038 * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz 4039 * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz 4040 * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz 4041 * @retval None 4042 */ 4043 #define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 4044 do { \ 4045 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4046 MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ 4047 } while(0) 4048 4049 /** @brief Macros to enable or disable the MSI bias mode selection. 4050 * @note By default the MSI bias is in continuous mode in order to maintain 4051 * the output clocks accuracy. 4052 * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. 4053 * @retval None 4054 */ 4055 #define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 4056 4057 #define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) 4058 4059 /** @brief Macros to enable or disable LSE clock glitch filter . 4060 * @note The glitches on LSE can be filtred by setting the LSEGFON. 4061 * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). 4062 * @retval None 4063 */ 4064 4065 #define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 4066 4067 #define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) 4068 4069 /** 4070 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 4071 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). 4072 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 4073 * This parameter must be one of the following values: 4074 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) 4075 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4076 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4077 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4078 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4079 * @retval None 4080 */ 4081 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ 4082 MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ 4083 (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ 4084 RCC_CSR_MSISSRANGE_Pos));\ 4085 } while(0) 4086 /** 4087 * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode 4088 * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). 4089 * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. 4090 * This parameter must be one of the following values: 4091 * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) 4092 * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz 4093 * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz 4094 * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz 4095 * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz 4096 * @retval None 4097 */ 4098 #define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \ 4099 do { \ 4100 SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ 4101 MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \ 4102 (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \ 4103 } while(0) 4104 4105 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 4106 * @retval MSI clock range. 4107 * This parameter must be one of the following values: 4108 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 4109 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 4110 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 4111 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 4112 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 4113 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4114 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4115 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4116 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4117 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4118 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4119 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4120 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4121 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4122 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4123 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4124 */ 4125 #define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 4126 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ 4127 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ 4128 (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) 4129 4130 /** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode 4131 * @retval MSIK clock range. 4132 * This parameter must be one of the following values: 4133 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz 4134 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz 4135 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz 4136 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz 4137 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz 4138 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 4139 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz 4140 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz 4141 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz 4142 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz 4143 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz 4144 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz 4145 * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz 4146 * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz 4147 * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz 4148 * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz 4149 */ 4150 #define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ 4151 (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ 4152 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ 4153 (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) 4154 4155 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4156 * @note After enabling the LSI, the application software should wait on 4157 * LSIRDY flag to be set indicating that LSI clock is stable and can 4158 * be used to clock the IWDG and/or the RTC. 4159 * @note LSI can not be disabled if the IWDG is running. 4160 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4161 * clock cycles. 4162 * @retval None 4163 */ 4164 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 4165 4166 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) 4167 4168 /** 4169 * @brief Macro to configure the External High Speed oscillator (HSE). 4170 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4171 * supported by this macro. User should request a transition to HSE Off 4172 * first and then HSE On or HSE Bypass. 4173 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4174 * software should wait on HSERDY flag to be set indicating that HSE clock 4175 * is stable and can be used to clock the PLL and/or system clock. 4176 * @note HSE state can not be changed if it is used directly or through the 4177 * PLL as system clock. In this case, you have to select another source 4178 * of the system clock then change the HSE state (ex. disable it). 4179 * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. 4180 * @param __STATE__: specifies the new state of the HSE. 4181 * This parameter can be one of the following values: 4182 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4183 * 6 HSE oscillator clock cycles. 4184 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4185 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4186 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . 4187 * @retval None 4188 */ 4189 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4190 do { \ 4191 if((__STATE__) == RCC_HSE_ON) \ 4192 { \ 4193 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4194 } \ 4195 else if((__STATE__) == RCC_HSE_BYPASS) \ 4196 { \ 4197 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4198 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4199 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4200 } \ 4201 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 4202 { \ 4203 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4204 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4205 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4206 } \ 4207 else \ 4208 { \ 4209 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4210 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4211 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4212 } \ 4213 } while(0) 4214 4215 /** @brief Macro to enable or disable the LSE system clock. 4216 * @note This clock can be used by any peripheral when its source clock is the LSE or at system 4217 * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. 4218 * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by 4219 * the CSS on LSE, by a peripheral or any other source clock using LSE. 4220 * @retval None 4221 */ 4222 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 4223 4224 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) 4225 4226 /** @brief Macro to set Low-speed clock (LSI) divider. 4227 * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). 4228 * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 4229 * 4230 * @param __DIVIDER__ : specifies the divider value 4231 * This parameter can be one of the following values 4232 * @arg @ref RCC_LSI_DIV1 4233 * @arg @ref RCC_LSI_DIV128 4234 * @retval None 4235 */ 4236 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ 4237 do { \ 4238 if((__DIVIDER__) == RCC_LSI_DIV128) \ 4239 { \ 4240 SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 4241 } \ 4242 else \ 4243 { \ 4244 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ 4245 } \ 4246 } while(0) 4247 4248 /** 4249 * @brief Macro to configure the External Low Speed oscillator (LSE). 4250 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4251 * supported by this macro. User should request a transition to LSE Off 4252 * first and then LSE On or LSE Bypass. 4253 * @note As the LSE is in the Backup domain and write access is denied to 4254 * this domain after reset, you have to enable write access using 4255 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4256 * (to be done once after reset). 4257 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4258 * software should wait on LSERDY flag to be set indicating that LSE clock 4259 * is stable and can be used to clock the RTC. 4260 * @param __STATE__: specifies the new state of the LSE. 4261 * This parameter can be one of the following values: 4262 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4263 * 6 LSE oscillator clock cycles. 4264 * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. 4265 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. 4266 * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. 4267 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral 4268 * @retval None 4269 */ 4270 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4271 do { \ 4272 if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ 4273 { \ 4274 SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ 4275 } \ 4276 else if((__STATE__) == RCC_LSE_ON) \ 4277 { \ 4278 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4279 } \ 4280 else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ 4281 { \ 4282 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4283 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4284 } \ 4285 else if((__STATE__) == RCC_LSE_BYPASS) \ 4286 { \ 4287 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4288 SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4289 } \ 4290 else \ 4291 { \ 4292 CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ 4293 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4294 } \ 4295 } while(0) 4296 4297 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4298 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4299 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4300 * flag to be set indicating that HSI48 clock is stable. 4301 * This parameter can be: ENABLE or DISABLE. 4302 * @retval None 4303 */ 4304 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 4305 4306 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 4307 4308 /** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). 4309 * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up 4310 * @note After enabling the MSIK, the application software should wait on MSIKRDY 4311 * flag to be set indicating that MSIK clock is stable. 4312 * This parameter can be: ENABLE or DISABLE. 4313 * @retval None 4314 */ 4315 #define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) 4316 4317 #define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) 4318 4319 /** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). 4320 * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. 4321 * @note After enabling the SHSI, the application software should wait on SHSI 4322 * flag to be set indicating that SHSI clock is stable. 4323 * This parameter can be: ENABLE or DISABLE. 4324 * @retval None 4325 */ 4326 #define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) 4327 4328 #define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) 4329 4330 /** @brief Macros to configure the RTC clock (RTCCLK). 4331 * @note As the RTC clock configuration bits are in the Backup domain and write 4332 * access is denied to this domain after reset, you have to enable write 4333 * access using the Power Backup Access macro before to configure 4334 * the RTC clock source (to be done once after reset). 4335 * @note Once the RTC clock is configured it cannot be changed unless the 4336 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 4337 * a Power On Reset (POR). 4338 * 4339 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 4340 * This parameter can be one of the following values: 4341 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4342 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4343 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4344 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4345 * 4346 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4347 * work in STOP and STANDBY modes, and can be used as wakeup source. 4348 * However, when the HSE clock is used as RTC clock source, the RTC 4349 * cannot be used in STOP and STANDBY modes. 4350 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4351 * RTC clock source). 4352 * @retval None 4353 */ 4354 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 4355 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 4356 4357 /** @brief Macro to get the RTC clock source. 4358 * @retval The returned value can be one of the following: 4359 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4360 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4361 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4362 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 4363 */ 4364 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 4365 4366 /** @brief Macros to enable or disable the main PLL. 4367 * @note After enabling the main PLL, the application software should wait on 4368 * PLLRDY flag to be set indicating that PLL clock is stable and can 4369 * be used as system clock source. 4370 * @note The main PLL can not be disabled if it is used as system clock source 4371 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4372 */ 4373 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 4374 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 4375 4376 /** 4377 * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) 4378 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, 4379 * This is mainly used to save Power. 4380 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 4381 * This parameter can be one of the following values: 4382 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 4383 * high-quality audio performance on SAI interface. 4384 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 4385 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 4386 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 4387 * @retval None 4388 * 4389 */ 4390 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4391 4392 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4393 4394 /** 4395 * @brief Macro to get the PLL clock output enable status. 4396 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 4397 * This parameter can be one of the following values: 4398 * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, 4399 * high-quality audio performance on SAI interface. 4400 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), 4401 * the random analog generator (<=48 MHz) and the OCTOSPI1/2. 4402 * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) 4403 * @retval SET / RESET 4404 */ 4405 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4406 4407 /** 4408 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 4409 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 4410 * @retval None 4411 */ 4412 #define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4413 4414 #define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4415 4416 /** 4417 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 4418 * @note This function must be used only when the main PLL is disabled. 4419 * 4420 * @param __PLL1SOURCE__: specifies the PLL entry clock source. 4421 * This parameter can be one of the following values: 4422 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 4423 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 4424 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 4425 * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . 4426 * 4427 * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock 4428 * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. 4429 * 4430 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 4431 * This parameter must be a number between 1 and 63. 4432 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 4433 * frequency ranges from 1 to 16 MHz. 4434 * 4435 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 4436 * This parameter must be a number between 4 and 512. 4437 * @note You have to set the PLLN parameter correctly to ensure that the VCO 4438 * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) 4439 * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. 4440 * 4441 * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. 4442 * This parameter must be a number between 1 and 128 4443 * 4444 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. 4445 * This parameter must be a number between 1 and 128 4446 * 4447 * @param __PLL1R__: specifies the division factor for system clock. 4448 * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) 4449 * 4450 * @retval None 4451 */ 4452 #define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 4453 do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ 4454 RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ 4455 (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ 4456 MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ 4457 RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ 4458 ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ 4459 RCC_PLL1DIVR_PLL1P) | \ 4460 ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ 4461 RCC_PLL1DIVR_PLL1Q) |\ 4462 ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ 4463 RCC_PLL1DIVR_PLL1R))); \ 4464 } while(0) 4465 4466 /** @brief Macro to configure the PLLs clock source. 4467 * @note This function must be used only when all PLLs are disabled. 4468 * @param __PLL1SOURCE__: specifies the PLLs entry clock source. 4469 * This parameter can be one of the following values: 4470 * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry 4471 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry 4472 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry 4473 */ 4474 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 4475 4476 /** 4477 * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor 4478 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 4479 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 4480 * It should be a value between 0 and 8191 4481 * @note Warning: The software has to set correctly these bits to insure that the VCO 4482 * output frequency is between its valid frequency range, which is: 4483 * 192 to 836 MHz if PLL1VCOSEL = 0 4484 * 150 to 420 MHz if PLL1VCOSEL = 1. 4485 * @retval None 4486 */ 4487 #define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ 4488 (uint32_t)(__PLL1FRACN__) << \ 4489 RCC_PLL1FRACR_PLL1FRACN_Pos) 4490 4491 /** @brief Macro to select the PLL1 reference frequency range. 4492 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 4493 * This parameter can be one of the following values: 4494 * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz 4495 * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz 4496 * @retval None 4497 */ 4498 #define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ 4499 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 4500 4501 /** @brief Macro to get the oscillator used as PLL1 clock source. 4502 * @retval The oscillator used as PLL1 clock source. The returned value can be one 4503 * of the following: 4504 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 4505 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 4506 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 4507 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 4508 */ 4509 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 4510 4511 /** 4512 * @brief Macro to configure the system clock source. 4513 * @param __SYSCLKSOURCE__: specifies the system clock source. 4514 * This parameter can be one of the following values: 4515 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 4516 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4517 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4518 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. 4519 * @retval None 4520 */ 4521 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4522 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 4523 4524 /** @brief Macro to get the clock source used as system clock. 4525 * @retval The clock source used as system clock. The returned value can be one 4526 * of the following: 4527 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 4528 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4529 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4530 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. 4531 */ 4532 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 4533 4534 /** 4535 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4536 * @note As the LSE is in the Backup domain and write access is denied to 4537 * this domain after reset, you have to enable write access using 4538 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4539 * (to be done once after reset). 4540 * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) 4541 * when the LSE is ON. However, once LSEDRV is selected, the drive 4542 * capability can not be increased if LSEON = 1. 4543 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 4544 * This parameter can be one of the following values: 4545 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4546 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4547 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4548 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4549 * @retval None 4550 */ 4551 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4552 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 4553 4554 /** 4555 * @brief Macro to configure the wake up from stop clock. 4556 * @note The selected clock is also used as emergency clock for the clock security system on HSE. 4557 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 4558 * This parameter can be one of the following values: 4559 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock 4560 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock 4561 * @retval None 4562 */ 4563 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4564 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 4565 4566 /** 4567 * @brief Macro to configure the Kernel wake up from stop clock. 4568 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 4569 * This parameter can be one of the following values: 4570 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source 4571 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 4572 * @retval None 4573 */ 4574 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 4575 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 4576 4577 /** @brief Macro to configure the MCO clock. 4578 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 4579 * This parameter can be one of the following values: 4580 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 4581 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 4582 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 4583 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 4584 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 4585 * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source 4586 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 4587 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 4588 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 4589 * @param __MCODIV__ specifies the MCO clock prescaler. 4590 * This parameter can be one of the following values: 4591 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 4592 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 4593 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 4594 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 4595 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 4596 */ 4597 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4598 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4599 4600 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4601 * @brief macros to manage the specified RCC Flags and interrupts. 4602 * @{ 4603 */ 4604 4605 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 4606 * the selected interrupts). 4607 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4608 * This parameter can be any combination of the following values: 4609 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4610 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4611 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4612 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4613 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4614 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4615 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4616 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4617 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4618 * @retval None 4619 */ 4620 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4621 4622 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 4623 * the selected interrupts). 4624 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4625 * This parameter can be any combination of the following values: 4626 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4627 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4628 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 4629 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4630 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4631 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4632 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4633 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4634 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4635 * @retval None 4636 */ 4637 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4638 4639 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 4640 * bits to clear the selected interrupt pending bits. 4641 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4642 * This parameter can be any combination of the following values: 4643 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4644 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4645 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4646 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4647 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4648 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4649 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4650 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4651 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4652 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4653 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 4654 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 4655 * @retval None 4656 */ 4657 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4658 4659 /** @brief Check whether the RCC interrupt has occurred or not. 4660 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4661 * This parameter can be one of the following values: 4662 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4663 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4664 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 4665 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4666 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4667 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 4668 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4669 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt 4670 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 4671 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4672 * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt 4673 * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt 4674 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4675 */ 4676 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4677 4678 /** @brief Set RMVF bit to clear the reset flags. 4679 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4680 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4681 * @retval None 4682 */ 4683 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 4684 4685 /** @brief Check whether the selected RCC flag is set or not. 4686 * @param __FLAG__: specifies the flag to check. 4687 * This parameter can be one of the following values: 4688 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 4689 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4690 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4691 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 4692 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4693 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready 4694 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4695 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4696 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4697 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4698 * @arg @ref RCC_FLAG_BORRST BOR reset 4699 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 4700 * @arg @ref RCC_FLAG_PINRST Pin reset 4701 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 4702 * @arg @ref RCC_FLAG_SFTRST Software reset 4703 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4704 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4705 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4706 * @retval The new state of __FLAG__ (TRUE or FALSE). 4707 */ 4708 #define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4709 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4710 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 4711 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4712 /** 4713 * @} 4714 */ 4715 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ 4716 ((SOURCE) == RCC_PLLSOURCE_HSI) || \ 4717 ((SOURCE) == RCC_PLLSOURCE_HSE)) 4718 4719 #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) 4720 #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4721 #define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4722 #define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4723 #define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4724 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ 4725 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 4726 4727 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ 4728 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 4729 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 4730 ((__RANGE__) == RCC_MSIRANGE_1) || \ 4731 ((__RANGE__) == RCC_MSIRANGE_2) || \ 4732 ((__RANGE__) == RCC_MSIRANGE_3) || \ 4733 ((__RANGE__) == RCC_MSIRANGE_4) || \ 4734 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4735 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4736 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4737 ((__RANGE__) == RCC_MSIRANGE_8) || \ 4738 ((__RANGE__) == RCC_MSIRANGE_9) || \ 4739 ((__RANGE__) == RCC_MSIRANGE_10) || \ 4740 ((__RANGE__) == RCC_MSIRANGE_11) || \ 4741 ((__RANGE__) == RCC_MSIRANGE_12) || \ 4742 ((__RANGE__) == RCC_MSIRANGE_13) || \ 4743 ((__RANGE__) == RCC_MSIRANGE_14) || \ 4744 ((__RANGE__) == RCC_MSIRANGE_15)) 4745 4746 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 4747 ((__RANGE__) == RCC_MSIRANGE_5) || \ 4748 ((__RANGE__) == RCC_MSIRANGE_6) || \ 4749 ((__RANGE__) == RCC_MSIRANGE_7) || \ 4750 ((__RANGE__) == RCC_MSIRANGE_8)) 4751 4752 #define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ 4753 ((__RANGE__) == RCC_MSIKRANGE_1) || \ 4754 ((__RANGE__) == RCC_MSIKRANGE_2) || \ 4755 ((__RANGE__) == RCC_MSIKRANGE_3) || \ 4756 ((__RANGE__) == RCC_MSIKRANGE_4) || \ 4757 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 4758 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 4759 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 4760 ((__RANGE__) == RCC_MSIKRANGE_8) || \ 4761 ((__RANGE__) == RCC_MSIKRANGE_9) || \ 4762 ((__RANGE__) == RCC_MSIKRANGE_10) || \ 4763 ((__RANGE__) == RCC_MSIKRANGE_11) || \ 4764 ((__RANGE__) == RCC_MSIKRANGE_12) || \ 4765 ((__RANGE__) == RCC_MSIKRANGE_13) || \ 4766 ((__RANGE__) == RCC_MSIKRANGE_14) || \ 4767 ((__RANGE__) == RCC_MSIKRANGE_15)) 4768 4769 #define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ 4770 ((__RANGE__) == RCC_MSIKRANGE_5) || \ 4771 ((__RANGE__) == RCC_MSIKRANGE_6) || \ 4772 ((__RANGE__) == RCC_MSIKRANGE_7) || \ 4773 ((__RANGE__) == RCC_MSIKRANGE_8)) 4774 4775 /** 4776 * @} 4777 */ 4778 4779 /* Include RCC HAL Extended module */ 4780 #include "stm32u5xx_hal_rcc_ex.h" 4781 4782 /* Exported functions --------------------------------------------------------*/ 4783 /** @addtogroup RCC_Exported_Functions 4784 * @{ 4785 */ 4786 4787 /** @addtogroup RCC_Exported_Functions_Group1 4788 * @{ 4789 */ 4790 4791 /* Initialization and de-initialization functions ******************************/ 4792 HAL_StatusTypeDef HAL_RCC_DeInit(void); 4793 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); 4794 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); 4795 4796 /** 4797 * @} 4798 */ 4799 4800 /** @addtogroup RCC_Exported_Functions_Group2 4801 * @{ 4802 */ 4803 4804 /* Peripheral Control functions **********************************************/ 4805 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 4806 void HAL_RCC_EnableCSS(void); 4807 uint32_t HAL_RCC_GetSysClockFreq(void); 4808 uint32_t HAL_RCC_GetHCLKFreq(void); 4809 uint32_t HAL_RCC_GetPCLK1Freq(void); 4810 uint32_t HAL_RCC_GetPCLK2Freq(void); 4811 uint32_t HAL_RCC_GetPCLK3Freq(void); 4812 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); 4813 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); 4814 uint32_t HAL_RCC_GetResetSource(void); 4815 /* CSS NMI IRQ handler */ 4816 void HAL_RCC_NMI_IRQHandler(void); 4817 /* User Callbacks in non blocking mode (IT mode) */ 4818 void HAL_RCC_CSSCallback(void); 4819 4820 /** 4821 * @} 4822 */ 4823 4824 /* Attributes management functions ********************************************/ 4825 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 4826 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 4827 4828 /** 4829 * @} 4830 */ 4831 4832 /** 4833 * @} 4834 */ 4835 /** 4836 * @} 4837 */ 4838 4839 #ifdef __cplusplus 4840 } 4841 #endif 4842 4843 #endif /* STM32U5xx_HAL_RCC_H */ 4844
