1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_RCC_H 21 #define __STM32H5xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL1 configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PLLState; /*!< PLLState: The new state of the PLL1. 49 This parameter can be a value of @ref RCC_PLL1_Config */ 50 51 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 52 This parameter must be a value of @ref RCC_PLL1_Clock_Source */ 53 54 uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. 55 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ 56 57 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. 58 This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ 59 60 uint32_t PLLP; /*!< PLLP: Division factor for system clock. 61 This parameter must be a number between Min_Data = 2 and Max_Data = 128 62 odd division factors are not allowed */ 63 64 uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. 65 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 66 67 uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. 68 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 69 70 uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range 71 This parameter must be a value of @ref RCC_PLL1_VCI_Range */ 72 73 uint32_t PLLVCOSEL; /*!< PLLVCOSEL: PLL1 clock Output range 74 This parameter must be a value of @ref RCC_PLL1_VCO_Range */ 75 76 uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for 77 PLL1 VCO It should be a value between 0 and 8191 */ 78 79 } RCC_PLLInitTypeDef; 80 81 /** 82 * @brief RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition 83 */ 84 typedef struct 85 { 86 uint32_t OscillatorType; /*!< The oscillators to be configured. 87 This parameter can be a value of @ref RCC_Oscillator_Type */ 88 89 uint32_t HSEState; /*!< The new state of the HSE. 90 This parameter can be a value of @ref RCC_HSE_Config */ 91 92 uint32_t LSEState; /*!< The new state of the LSE. 93 This parameter can be a value of @ref RCC_LSE_Config */ 94 95 uint32_t HSIState; /*!< The new state of the HSI. 96 This parameter can be a value of @ref RCC_HSI_Config */ 97 98 uint32_t HSIDiv; /*!< The division factor of the HSI. 99 This parameter can be a value of @ref RCC_HSI_Div */ 100 101 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F 103 on the other devices */ 104 105 uint32_t LSIState; /*!< The new state of the LSI. 106 This parameter can be a value of @ref RCC_LSI_Config */ 107 108 uint32_t CSIState; /*!< The new state of the CSI. 109 This parameter can be a value of @ref RCC_CSI_Config */ 110 111 uint32_t CSICalibrationValue; /*!< The calibration trimming value (default is RCC_CSICALIBRATION_DEFAULT). 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F */ 113 114 uint32_t HSI48State; /*!< The new state of the HSI48. 115 This parameter can be a value of @ref RCC_HSI48_Config */ 116 117 RCC_PLLInitTypeDef PLL; /*!< PLL1 structure parameters */ 118 119 } RCC_OscInitTypeDef; 120 121 /** 122 * @brief RCC System, AHB and APB busses clock configuration structure definition 123 */ 124 typedef struct 125 { 126 uint32_t ClockType; /*!< The clock to be configured. 127 This parameter can be a value of @ref RCC_System_Clock_Type */ 128 129 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 130 This parameter can be a value of @ref RCC_System_Clock_Source */ 131 132 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 133 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 134 135 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 136 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 137 138 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 139 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 140 141 uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). 142 This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ 143 } RCC_ClkInitTypeDef; 144 145 /** 146 * @} 147 */ 148 149 /* Exported constants --------------------------------------------------------*/ 150 /** @defgroup RCC_Exported_Constants RCC Exported Constants 151 * @{ 152 */ 153 154 /** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping 155 * @{ 156 */ 157 158 /** 159 * @} 160 */ 161 162 /** @defgroup RCC_Oscillator_Type Oscillator Type 163 * @{ 164 */ 165 #define RCC_OSCILLATORTYPE_NONE (0x00000000U) /*!< Oscillator configuration unchanged */ 166 #define RCC_OSCILLATORTYPE_HSE (0x00000001U) /*!< HSE to configure */ 167 #define RCC_OSCILLATORTYPE_HSI (0x00000002U) /*!< HSI to configure */ 168 #define RCC_OSCILLATORTYPE_LSE (0x00000004U) /*!< LSE to configure */ 169 #define RCC_OSCILLATORTYPE_LSI (0x00000008U) /*!< LSI to configure */ 170 #define RCC_OSCILLATORTYPE_CSI (0x00000010U) /*!< CSI to configure */ 171 #define RCC_OSCILLATORTYPE_HSI48 (0x00000020U) /*!< HSI48 to configure */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup RCC_HSE_Config HSE Config 177 * @{ 178 */ 179 #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ 180 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 181 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Analog clock source for HSE clock */ 182 #define RCC_HSE_BYPASS_DIGITAL ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External Digital clock source for HSE clock */ 183 /** 184 * @} 185 */ 186 187 /** @defgroup RCC_LSE_Config LSE Config 188 * @{ 189 */ 190 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 191 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 192 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock */ 193 #define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup RCC_HSI_Config HSI Config 199 * @{ 200 */ 201 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 202 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 203 204 #define RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup RCC_HSI_Div HSI Div 210 * @{ 211 */ 212 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 213 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 214 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 215 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 216 /** 217 * @} 218 */ 219 220 /** @defgroup RCC_LSI_Config LSI Config 221 * @{ 222 */ 223 #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ 224 #define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ 225 /** 226 * @} 227 */ 228 229 /** @defgroup RCC_CSI_Config CSI Config 230 * @{ 231 */ 232 #define RCC_CSI_OFF (0x00000000U) /*!< CSI clock deactivation */ 233 #define RCC_CSI_ON RCC_CR_CSION /*!< CSI clock activation */ 234 235 #define RCC_CSICALIBRATION_DEFAULT (0x20U) /*!< Default CSI calibration trimming value */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup RCC_HSI48_Config HSI48 Config 241 * @{ 242 */ 243 #define RCC_HSI48_OFF (0x00000000U) /*!< HSI48 clock deactivation */ 244 #define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup RCC_PLL1_Config RCC PLL1 Config 250 * @{ 251 */ 252 #define RCC_PLL_NONE (0x00000000U) 253 #define RCC_PLL_OFF (0x00000001U) 254 #define RCC_PLL_ON (0x00000002U) 255 /** 256 * @} 257 */ 258 259 /** @defgroup RCC_PLL1_Clock_Output RCC PLL1 Clock Output 260 * @{ 261 */ 262 #define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN 263 #define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN 264 #define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN 265 /** 266 * @} 267 */ 268 269 /** @defgroup RCC_PLL1_VCI_Range RCC PLL1 VCI Range 270 * @{ 271 */ 272 #define RCC_PLL1_VCIRANGE_0 (0x00000000U) /*!< Clock range frequency between 1 and 2 MHz */ 273 #define RCC_PLL1_VCIRANGE_1 RCC_PLL1CFGR_PLL1RGE_0 /*!< Clock range frequency between 2 and 4 MHz */ 274 #define RCC_PLL1_VCIRANGE_2 RCC_PLL1CFGR_PLL1RGE_1 /*!< Clock range frequency between 4 and 8 MHz */ 275 #define RCC_PLL1_VCIRANGE_3 (RCC_PLL1CFGR_PLL1RGE_0 | RCC_PLL1CFGR_PLL1RGE_1) /*!< Clock range frequency between 8 and 16 MHz */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup RCC_PLL1_VCO_Range RCC PLL1 VCO Range 281 * @{ 282 */ 283 #define RCC_PLL1_VCORANGE_WIDE (0x00000000U) /*!< Clock range frequency between 192 and 836 MHz */ 284 #define RCC_PLL1_VCORANGE_MEDIUM RCC_PLL1CFGR_PLL1VCOSEL /*!< Clock range frequency between 150 and 420 MHz */ 285 286 /** 287 * @} 288 */ 289 290 /** @defgroup RCC_PLL1_Clock_Source RCC PLL1 Clock Source 291 * @{ 292 */ 293 #define RCC_PLL1_SOURCE_NONE (0x00000000U) 294 #define RCC_PLL1_SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_0 295 #define RCC_PLL1_SOURCE_CSI RCC_PLL1CFGR_PLL1SRC_1 296 #define RCC_PLL1_SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) 297 /** 298 * @} 299 */ 300 301 302 /** @defgroup RCC_System_Clock_Type System Clock Type 303 * @{ 304 */ 305 #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ 306 #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ 307 #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ 308 #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ 309 #define RCC_CLOCKTYPE_PCLK3 (0x00000010U) /*!< PCLK3 to configure */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCC_System_Clock_Source System Clock Source 315 * @{ 316 */ 317 #define RCC_SYSCLKSOURCE_HSI (0x00000000U) /*!< HSI selection as system clock */ 318 #define RCC_SYSCLKSOURCE_CSI RCC_CFGR1_SW_0 /*!< CSI selection as system clock */ 319 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ 320 #define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ 321 /** 322 * @} 323 */ 324 325 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 326 * @{ 327 */ 328 #define RCC_SYSCLKSOURCE_STATUS_HSI (0x00000000U) /*!< HSI used as system clock */ 329 #define RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR1_SWS_0 /*!< CSI used as system clock */ 330 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ 331 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 337 * @{ 338 */ 339 #define RCC_SYSCLK_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 340 #define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ 341 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ 342 #define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ 343 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ 344 #define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ 345 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ 346 #define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ 347 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ 348 /** 349 * @} 350 */ 351 352 /** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source 353 * @{ 354 */ 355 #define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ 356 #define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ 357 #define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ 358 #define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ 359 #define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler 365 * @{ 366 */ 367 #define RCC_RTC_HSE_NOCLOCK (0x00000000U) 368 #define RCC_RTC_HSE_DIV2 (0x00000200U) 369 #define RCC_RTC_HSE_DIV3 (0x00000300U) 370 #define RCC_RTC_HSE_DIV4 (0x00000400U) 371 #define RCC_RTC_HSE_DIV5 (0x00000500U) 372 #define RCC_RTC_HSE_DIV6 (0x00000600U) 373 #define RCC_RTC_HSE_DIV7 (0x00000700U) 374 #define RCC_RTC_HSE_DIV8 (0x00000800U) 375 #define RCC_RTC_HSE_DIV9 (0x00000900U) 376 #define RCC_RTC_HSE_DIV10 (0x00000A00U) 377 #define RCC_RTC_HSE_DIV11 (0x00000B00U) 378 #define RCC_RTC_HSE_DIV12 (0x00000C00U) 379 #define RCC_RTC_HSE_DIV13 (0x00000D00U) 380 #define RCC_RTC_HSE_DIV14 (0x00000E00U) 381 #define RCC_RTC_HSE_DIV15 (0x00000F00U) 382 #define RCC_RTC_HSE_DIV16 (0x00001000U) 383 #define RCC_RTC_HSE_DIV17 (0x00001100U) 384 #define RCC_RTC_HSE_DIV18 (0x00001200U) 385 #define RCC_RTC_HSE_DIV19 (0x00001300U) 386 #define RCC_RTC_HSE_DIV20 (0x00001400U) 387 #define RCC_RTC_HSE_DIV21 (0x00001500U) 388 #define RCC_RTC_HSE_DIV22 (0x00001600U) 389 #define RCC_RTC_HSE_DIV23 (0x00001700U) 390 #define RCC_RTC_HSE_DIV24 (0x00001800U) 391 #define RCC_RTC_HSE_DIV25 (0x00001900U) 392 #define RCC_RTC_HSE_DIV26 (0x00001A00U) 393 #define RCC_RTC_HSE_DIV27 (0x00001B00U) 394 #define RCC_RTC_HSE_DIV28 (0x00001C00U) 395 #define RCC_RTC_HSE_DIV29 (0x00001D00U) 396 #define RCC_RTC_HSE_DIV30 (0x00001E00U) 397 #define RCC_RTC_HSE_DIV31 (0x00001F00U) 398 #define RCC_RTC_HSE_DIV32 (0x00002000U) 399 #define RCC_RTC_HSE_DIV33 (0x00002100U) 400 #define RCC_RTC_HSE_DIV34 (0x00002200U) 401 #define RCC_RTC_HSE_DIV35 (0x00002300U) 402 #define RCC_RTC_HSE_DIV36 (0x00002400U) 403 #define RCC_RTC_HSE_DIV37 (0x00002500U) 404 #define RCC_RTC_HSE_DIV38 (0x00002600U) 405 #define RCC_RTC_HSE_DIV39 (0x00002700U) 406 #define RCC_RTC_HSE_DIV40 (0x00002800U) 407 #define RCC_RTC_HSE_DIV41 (0x00002900U) 408 #define RCC_RTC_HSE_DIV42 (0x00002A00U) 409 #define RCC_RTC_HSE_DIV43 (0x00002B00U) 410 #define RCC_RTC_HSE_DIV44 (0x00002C00U) 411 #define RCC_RTC_HSE_DIV45 (0x00002D00U) 412 #define RCC_RTC_HSE_DIV46 (0x00002E00U) 413 #define RCC_RTC_HSE_DIV47 (0x00002F00U) 414 #define RCC_RTC_HSE_DIV48 (0x00003000U) 415 #define RCC_RTC_HSE_DIV49 (0x00003100U) 416 #define RCC_RTC_HSE_DIV50 (0x00003200U) 417 #define RCC_RTC_HSE_DIV51 (0x00003300U) 418 #define RCC_RTC_HSE_DIV52 (0x00003400U) 419 #define RCC_RTC_HSE_DIV53 (0x00003500U) 420 #define RCC_RTC_HSE_DIV54 (0x00003600U) 421 #define RCC_RTC_HSE_DIV55 (0x00003700U) 422 #define RCC_RTC_HSE_DIV56 (0x00003800U) 423 #define RCC_RTC_HSE_DIV57 (0x00003900U) 424 #define RCC_RTC_HSE_DIV58 (0x00003A00U) 425 #define RCC_RTC_HSE_DIV59 (0x00003B00U) 426 #define RCC_RTC_HSE_DIV60 (0x00003C00U) 427 #define RCC_RTC_HSE_DIV61 (0x00003D00U) 428 #define RCC_RTC_HSE_DIV62 (0x00003E00U) 429 #define RCC_RTC_HSE_DIV63 (0x00003F00U) 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 435 * @{ 436 */ 437 #define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock used as RTC clock source */ 438 #define RCC_RTCCLKSOURCE_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock source */ 439 #define RCC_RTCCLKSOURCE_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock source */ 440 #define RCC_RTCCLKSOURCE_HSE_DIVx (0x00000300U) /*!< HSE oscillator clock divided by X used as RTC clock source */ 441 #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) 442 #define RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U) 443 #define RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U) 444 #define RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U) 445 #define RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U) 446 #define RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U) 447 #define RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U) 448 #define RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U) 449 #define RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U) 450 #define RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U) 451 #define RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U) 452 #define RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U) 453 #define RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U) 454 #define RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U) 455 #define RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U) 456 #define RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U) 457 #define RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U) 458 #define RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U) 459 #define RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U) 460 #define RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U) 461 #define RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U) 462 #define RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U) 463 #define RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U) 464 #define RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U) 465 #define RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U) 466 #define RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U) 467 #define RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U) 468 #define RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U) 469 #define RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U) 470 #define RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U) 471 #define RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U) 472 #define RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U) 473 #define RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U) 474 #define RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U) 475 #define RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U) 476 #define RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U) 477 #define RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U) 478 #define RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U) 479 #define RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U) 480 #define RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U) 481 #define RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U) 482 #define RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U) 483 #define RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U) 484 #define RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U) 485 #define RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U) 486 #define RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U) 487 #define RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U) 488 #define RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U) 489 #define RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U) 490 #define RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U) 491 #define RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U) 492 #define RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U) 493 #define RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U) 494 #define RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U) 495 #define RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U) 496 #define RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U) 497 #define RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U) 498 #define RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U) 499 #define RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U) 500 #define RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U) 501 #define RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U) 502 #define RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U) 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCC_MCO_Index MCO Index 508 * @{ 509 */ 510 #define RCC_MCO1 (0x00000000U) 511 #define RCC_MCO2 (0x00000001U) 512 /** 513 * @} 514 */ 515 516 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source 517 * @{ 518 */ 519 #define RCC_MCO1SOURCE_HSI (0x00000000U) 520 #define RCC_MCO1SOURCE_LSE RCC_CFGR1_MCO1SEL_0 521 #define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCO1SEL_1 522 #define RCC_MCO1SOURCE_PLL1Q ((uint32_t)RCC_CFGR1_MCO1SEL_0 | RCC_CFGR1_MCO1SEL_1) 523 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCO1SEL_2 524 525 /** 526 * @} 527 */ 528 529 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source 530 * @{ 531 */ 532 #define RCC_MCO2SOURCE_SYSCLK (0x00000000U) 533 #define RCC_MCO2SOURCE_PLL2P RCC_CFGR1_MCO2SEL_0 534 #define RCC_MCO2SOURCE_HSE RCC_CFGR1_MCO2SEL_1 535 #define RCC_MCO2SOURCE_PLL1P ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_1) 536 #define RCC_MCO2SOURCE_CSI RCC_CFGR1_MCO2SEL_2 537 #define RCC_MCO2SOURCE_LSI ((uint32_t)RCC_CFGR1_MCO2SEL_0 | RCC_CFGR1_MCO2SEL_2) 538 539 /** 540 * @} 541 */ 542 543 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler 544 * @{ 545 */ 546 #define RCC_MCODIV_1 RCC_CFGR1_MCO1PRE_0 547 #define RCC_MCODIV_2 RCC_CFGR1_MCO1PRE_1 548 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1) 549 #define RCC_MCODIV_4 RCC_CFGR1_MCO1PRE_2 550 #define RCC_MCODIV_5 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2) 551 #define RCC_MCODIV_6 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 552 #define RCC_MCODIV_7 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2) 553 #define RCC_MCODIV_8 RCC_CFGR1_MCO1PRE_3 554 #define RCC_MCODIV_9 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_3) 555 #define RCC_MCODIV_10 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 556 #define RCC_MCODIV_11 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_3) 557 #define RCC_MCODIV_12 ((uint32_t)RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 558 #define RCC_MCODIV_13 ((uint32_t)RCC_CFGR1_MCO1PRE_0 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 559 #define RCC_MCODIV_14 ((uint32_t)RCC_CFGR1_MCO1PRE_1 | RCC_CFGR1_MCO1PRE_2 | RCC_CFGR1_MCO1PRE_3) 560 #define RCC_MCODIV_15 RCC_CFGR1_MCO1PRE 561 /** 562 * @} 563 */ 564 565 /** @defgroup RCC_Interrupt Interrupts 566 * @{ 567 */ 568 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 569 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 570 #define RCC_IT_CSIRDY RCC_CIFR_CSIRDYF /*!< CSI Ready Interrupt flag */ 571 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 572 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 573 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 574 #define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ 575 #define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 576 #if defined(RCC_CR_PLL3ON) 577 #define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ 578 #endif /* RCC_CR_PLL3ON */ 579 #define RCC_IT_HSECSS RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */ 580 581 /** 582 * @} 583 */ 584 585 /** @defgroup RCC_Flag Flags 586 * Elements values convention: XXXYYYYYb 587 * - YYYYY : Flag position in the register 588 * - XXX : Register index 589 * - 001: CR register 590 * - 010: BDCR register 591 * - 011: RSR register 592 * @{ 593 */ 594 /* Flags in the CR register */ 595 #define RCC_FLAG_CSIRDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_CSIRDY_Pos)) /*!< CSI Ready flag */ 596 #define RCC_FLAG_HSIRDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ 597 #define RCC_FLAG_HSIDIVF ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIDIVF_Pos)) /*!< HSI divider flag */ 598 #define RCC_FLAG_HSERDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ 599 #define RCC_FLAG_PLL1RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL1 Ready flag */ 600 #define RCC_FLAG_PLL2RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ 601 #if defined(RCC_CR_PLL3ON) 602 #define RCC_FLAG_PLL3RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ 603 #endif /* RCC_CR_PLL3ON */ 604 #define RCC_FLAG_HSI48RDY ((uint32_t)((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ 605 606 /* Flags in the BDCR register */ 607 #define RCC_FLAG_LSERDY ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ 608 #define RCC_FLAG_LSECSSD ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ 609 #define RCC_FLAG_LSIRDY ((uint32_t)((RCC_BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ 610 611 /* Flags in the RSR register */ 612 #define RCC_FLAG_RMVF ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_RMVF_Pos)) /*!< Remove reset flag */ 613 #define RCC_FLAG_PINRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_PINRSTF_Pos)) /*!< PIN reset flag */ 614 #define RCC_FLAG_BORRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_BORRSTF_Pos)) /*!< BOR reset flag */ 615 #define RCC_FLAG_SFTRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 616 #define RCC_FLAG_IWDGRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 617 #define RCC_FLAG_WWDGRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 618 #define RCC_FLAG_LPWRRST ((uint32_t)((RCC_RSR_REG_INDEX << 5U) | RCC_RSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 619 620 /** 621 * @} 622 */ 623 624 /** @defgroup RCC_Reset_Flag Reset Flag 625 * @{ 626 */ 627 #define RCC_RESET_FLAG_PIN RCC_RSR_PINRSTF /*!< PIN reset flag */ 628 #define RCC_RESET_FLAG_PWR RCC_RSR_BORRSTF /*!< BOR or POR/PDR reset flag */ 629 #define RCC_RESET_FLAG_SW RCC_RSR_SFTRSTF /*!< Software Reset flag */ 630 #define RCC_RESET_FLAG_IWDG RCC_RSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 631 #define RCC_RESET_FLAG_WWDG RCC_RSR_WWDGRSTF /*!< Window watchdog reset flag */ 632 #define RCC_RESET_FLAG_LPWR RCC_RSR_LPWRRSTF /*!< Low power reset flag */ 633 #define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | RCC_RESET_FLAG_SW | \ 634 RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | RCC_RESET_FLAG_LPWR) 635 /** 636 * @} 637 */ 638 639 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 640 * @{ 641 */ 642 #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< LSE low drive capability */ 643 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 644 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 645 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 646 /** 647 * @} 648 */ 649 650 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 651 * @{ 652 */ 653 #define RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U) /*!< HSI selection after wake-up from STOP */ 654 #define RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR1_STOPWUCK /*!< CSI selection after wake-up from STOP */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock 660 * @{ 661 */ 662 #define RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U) /*!< HSI kernel clock selection after wake-up from STOP */ 663 #define RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR1_STOPKERWUCK /*!< CSI kernel clock selection after wake-up from STOP */ 664 665 /** 666 * @} 667 */ 668 669 #if defined(RCC_SECCFGR_HSISEC) 670 /** @defgroup RCC_items RCC items 671 * @brief RCC items to configure attributes on 672 * @{ 673 */ 674 #define RCC_HSI RCC_SECCFGR_HSISEC 675 #define RCC_HSE RCC_SECCFGR_HSESEC 676 #define RCC_CSI RCC_SECCFGR_CSISEC 677 #define RCC_LSI RCC_SECCFGR_LSISEC 678 #define RCC_LSE RCC_SECCFGR_LSESEC 679 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 680 #define RCC_PRESC RCC_SECCFGR_PRESCSEC 681 #define RCC_PLL1 RCC_SECCFGR_PLL1SEC 682 #define RCC_PLL2 RCC_SECCFGR_PLL2SEC 683 #define RCC_PLL3 RCC_SECCFGR_PLL3SEC 684 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 685 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 686 #define RCC_CKPERSEL RCC_SECCFGR_CKPERSELSEC 687 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_CSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 688 RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ 689 RCC_PLL3|RCC_CKPERSEL|RCC_RMVF) 690 /** 691 * @} 692 */ 693 #endif /* RCC_SECCFGR_HSISEC */ 694 695 /** @defgroup RCC_attributes RCC attributes 696 * @brief RCC privilege/non-privilege and secure/non-secure attributes 697 * @{ 698 */ 699 #if defined(RCC_PRIVCFGR_NSPRIV) 700 #define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ 701 #define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ 702 #else 703 #define RCC_PRIV 0x00000001U /*!< Privilege attribute item */ 704 #define RCC_NPRIV 0x00000002U /*!< Non-privilege attribute item */ 705 #endif /* RCC_PRIVCFGR_NSPRIV */ 706 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 707 #define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ 708 #define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ 709 #endif /* __ARM_FEATURE_CMSE */ 710 /** 711 * @} 712 */ 713 714 /** 715 * @} 716 */ 717 718 /* Exported macros -----------------------------------------------------------*/ 719 720 /** @defgroup RCC_Exported_Macros RCC Exported Macros 721 * @{ 722 */ 723 724 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 725 * @brief Enable or disable the AHB1 peripheral clock. 726 * @note After reset, the peripheral clock (used for registers read/write access) 727 * is disabled and the application software has to enable this clock before 728 * using it. 729 * @{ 730 */ 731 732 #define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ 733 __IO uint32_t tmpreg; \ 734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 735 /* Delay after an RCC peripheral clock enabling */ \ 736 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 737 UNUSED(tmpreg); \ 738 } while(0) 739 740 #define __HAL_RCC_GPDMA2_CLK_ENABLE() do { \ 741 __IO uint32_t tmpreg; \ 742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 743 /* Delay after an RCC peripheral clock enabling */ \ 744 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 745 UNUSED(tmpreg); \ 746 } while(0) 747 748 #if defined(CORDIC) 749 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ 750 __IO uint32_t tmpreg; \ 751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 752 /* Delay after an RCC peripheral clock enabling */ \ 753 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 754 UNUSED(tmpreg); \ 755 } while(0) 756 #endif /* CORDIC */ 757 758 #if defined(FMAC) 759 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ 760 __IO uint32_t tmpreg; \ 761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 762 /* Delay after an RCC peripheral clock enabling */ \ 763 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 764 UNUSED(tmpreg); \ 765 } while(0) 766 #endif /* FMAC */ 767 768 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 769 __IO uint32_t tmpreg; \ 770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 771 /* Delay after an RCC peripheral clock enabling */ \ 772 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 773 UNUSED(tmpreg); \ 774 } while(0) 775 776 #define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ 777 __IO uint32_t tmpreg; \ 778 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 779 /* Delay after an RCC peripheral clock enabling */ \ 780 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 781 UNUSED(tmpreg); \ 782 } while(0) 783 784 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 785 __IO uint32_t tmpreg; \ 786 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 787 /* Delay after an RCC peripheral clock enabling */ \ 788 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 789 UNUSED(tmpreg); \ 790 } while(0) 791 792 #if defined(ETH) 793 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 794 __IO uint32_t tmpreg; \ 795 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 796 /* Delay after an RCC peripheral clock enabling */ \ 797 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 798 UNUSED(tmpreg); \ 799 } while(0) 800 801 #define __HAL_RCC_ETHTX_CLK_ENABLE() do { \ 802 __IO uint32_t tmpreg; \ 803 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 804 /* Delay after an RCC peripheral clock enabling */ \ 805 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 806 UNUSED(tmpreg); \ 807 } while(0) 808 809 #define __HAL_RCC_ETHRX_CLK_ENABLE() do { \ 810 __IO uint32_t tmpreg; \ 811 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 812 /* Delay after an RCC peripheral clock enabling */ \ 813 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ 814 UNUSED(tmpreg); \ 815 } while(0) 816 #endif /*ETH*/ 817 818 #define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ 819 __IO uint32_t tmpreg; \ 820 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 821 /* Delay after an RCC peripheral clock enabling */ \ 822 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN); \ 823 UNUSED(tmpreg); \ 824 } while(0) 825 826 #define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ 827 __IO uint32_t tmpreg; \ 828 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 829 /* Delay after an RCC peripheral clock enabling */ \ 830 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN); \ 831 UNUSED(tmpreg); \ 832 } while(0) 833 834 #if defined(DCACHE1) 835 #define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ 836 __IO uint32_t tmpreg; \ 837 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 838 /* Delay after an RCC peripheral clock enabling */ \ 839 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ 840 UNUSED(tmpreg); \ 841 } while(0) 842 #endif /* DCACHE1 */ 843 844 #define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ 845 __IO uint32_t tmpreg; \ 846 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 847 /* Delay after an RCC peripheral clock enabling */ \ 848 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 849 UNUSED(tmpreg); \ 850 } while(0) 851 852 #define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) 853 854 #define __HAL_RCC_GPDMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) 855 856 #if defined(CORDIC) 857 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) 858 #endif /* CORDIC */ 859 860 #if defined(FMAC) 861 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) 862 #endif /* FMAC */ 863 864 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) 865 866 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 867 868 #define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) 869 870 #if defined(ETH) 871 #define __HAL_RCC_ETH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) 872 873 #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) 874 875 #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) 876 877 #endif /*ETH*/ 878 879 #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) 880 881 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) 882 883 #if defined(DCACHE1) 884 #define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) 885 #endif /* DCACHE1 */ 886 887 #define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) 888 /** 889 * @} 890 */ 891 892 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 893 * @brief Enable or disable the AHB2 peripheral clock. 894 * @note After reset, the peripheral clock (used for registers read/write access) 895 * is disabled and the application software has to enable this clock before 896 * using it. 897 * @{ 898 */ 899 900 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 901 __IO uint32_t tmpreg; \ 902 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 903 /* Delay after an RCC peripheral clock enabling */ \ 904 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 905 UNUSED(tmpreg); \ 906 } while(0) 907 908 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 909 __IO uint32_t tmpreg; \ 910 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 911 /* Delay after an RCC peripheral clock enabling */ \ 912 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 913 UNUSED(tmpreg); \ 914 } while(0) 915 916 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 917 __IO uint32_t tmpreg; \ 918 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 919 /* Delay after an RCC peripheral clock enabling */ \ 920 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 921 UNUSED(tmpreg); \ 922 } while(0) 923 924 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 925 __IO uint32_t tmpreg; \ 926 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 927 /* Delay after an RCC peripheral clock enabling */ \ 928 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 929 UNUSED(tmpreg); \ 930 } while(0) 931 932 #if defined(GPIOE) 933 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 934 __IO uint32_t tmpreg; \ 935 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 936 /* Delay after an RCC peripheral clock enabling */ \ 937 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 938 UNUSED(tmpreg); \ 939 } while(0) 940 #endif /* GPIOE */ 941 942 #if defined(GPIOF) 943 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 944 __IO uint32_t tmpreg; \ 945 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 946 /* Delay after an RCC peripheral clock enabling */ \ 947 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 948 UNUSED(tmpreg); \ 949 } while(0) 950 #endif /* GPIOF */ 951 952 #if defined(GPIOG) 953 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 954 __IO uint32_t tmpreg; \ 955 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 956 /* Delay after an RCC peripheral clock enabling */ \ 957 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 958 UNUSED(tmpreg); \ 959 } while(0) 960 #endif /* GPIOG */ 961 962 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 963 __IO uint32_t tmpreg; \ 964 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 965 /* Delay after an RCC peripheral clock enabling */ \ 966 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 967 UNUSED(tmpreg); \ 968 } while(0) 969 970 #if defined(GPIOI) 971 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg; \ 973 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ 976 UNUSED(tmpreg); \ 977 } while(0) 978 #endif /* GPIOI */ 979 980 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 981 __IO uint32_t tmpreg; \ 982 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 983 /* Delay after an RCC peripheral clock enabling */ \ 984 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 985 UNUSED(tmpreg); \ 986 } while(0) 987 988 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 989 __IO uint32_t tmpreg; \ 990 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 991 /* Delay after an RCC peripheral clock enabling */ \ 992 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ 993 UNUSED(tmpreg); \ 994 } while(0) 995 996 #if defined(DCMI) 997 #define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ 998 __IO uint32_t tmpreg; \ 999 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1000 /* Delay after an RCC peripheral clock enabling */ \ 1001 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ 1002 UNUSED(tmpreg); \ 1003 } while(0) 1004 1005 #define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility */ 1006 #endif /* DCMI */ 1007 1008 #if defined(AES) 1009 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 1010 __IO uint32_t tmpreg; \ 1011 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1012 /* Delay after an RCC peripheral clock enabling */ \ 1013 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 1014 UNUSED(tmpreg); \ 1015 } while(0) 1016 #endif /* AES */ 1017 1018 #if defined(HASH) 1019 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg; \ 1021 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 1024 UNUSED(tmpreg); \ 1025 } while(0) 1026 #endif /* HASH */ 1027 1028 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 1029 __IO uint32_t tmpreg; \ 1030 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1031 /* Delay after an RCC peripheral clock enabling */ \ 1032 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 1033 UNUSED(tmpreg); \ 1034 } while(0) 1035 1036 #if defined(PKA) 1037 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 1038 __IO uint32_t tmpreg; \ 1039 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1040 /* Delay after an RCC peripheral clock enabling */ \ 1041 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 1042 UNUSED(tmpreg); \ 1043 } while(0) 1044 #endif /* PKA */ 1045 1046 #if defined(SAES) 1047 #define __HAL_RCC_SAES_CLK_ENABLE() do { \ 1048 __IO uint32_t tmpreg; \ 1049 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1050 /* Delay after an RCC peripheral clock enabling */ \ 1051 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ 1052 UNUSED(tmpreg); \ 1053 } while(0) 1054 #endif /* SAES */ 1055 1056 #define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ 1057 __IO uint32_t tmpreg; \ 1058 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1059 /* Delay after an RCC peripheral clock enabling */ \ 1060 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ 1061 UNUSED(tmpreg); \ 1062 } while(0) 1063 #if defined(SRAM3_BASE) 1064 #define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ 1065 __IO uint32_t tmpreg; \ 1066 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1067 /* Delay after an RCC peripheral clock enabling */ \ 1068 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN); \ 1069 UNUSED(tmpreg); \ 1070 } while(0) 1071 #endif /* SRAM3_BASE */ 1072 1073 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 1074 1075 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 1076 1077 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 1078 1079 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 1080 1081 #if defined(GPIOE) 1082 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 1083 #endif /* GPIOE */ 1084 1085 #if defined(GPIOF) 1086 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 1087 #endif /* GPIOF */ 1088 1089 #if defined(GPIOG) 1090 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 1091 #endif /* GPIOG */ 1092 1093 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 1094 1095 #if defined(GPIOI) 1096 #define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) 1097 #endif /* GPIOI */ 1098 1099 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 1100 1101 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) 1102 1103 #if defined(DCMI) 1104 #define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) 1105 #define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ 1106 #endif /* DCMI */ 1107 1108 #if defined(AES) 1109 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 1110 #endif /* AES */ 1111 1112 #if defined(HASH) 1113 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 1114 #endif /* HASH */ 1115 1116 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 1117 1118 #if defined(PKA) 1119 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 1120 #endif /* PKA */ 1121 1122 #if defined(SAES) 1123 #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) 1124 #endif /* SAES */ 1125 1126 1127 #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) 1128 1129 #if defined(SRAM3_BASE) 1130 #define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) 1131 #endif /* SRAM3_BASE */ 1132 /** 1133 * @} 1134 */ 1135 1136 /** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4 Peripheral Clock Enable Disable 1137 * @brief Enable or disable the AHB4 peripheral clock. 1138 * @note After reset, the peripheral clock (used for registers read/write access) 1139 * is disabled and the application software has to enable this clock before 1140 * using it. 1141 * @{ 1142 */ 1143 1144 #if defined(OTFDEC1) 1145 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 1146 __IO uint32_t tmpreg; \ 1147 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1148 /* Delay after an RCC peripheral clock enabling */ \ 1149 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN); \ 1150 UNUSED(tmpreg); \ 1151 } while(0) 1152 #endif /* OTFDEC1 */ 1153 1154 #if defined(SDMMC1) 1155 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 1156 __IO uint32_t tmpreg; \ 1157 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1158 /* Delay after an RCC peripheral clock enabling */ \ 1159 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN); \ 1160 UNUSED(tmpreg); \ 1161 } while(0) 1162 #endif /* SDMMC1 */ 1163 1164 #if defined(SDMMC2) 1165 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ 1166 __IO uint32_t tmpreg; \ 1167 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1168 /* Delay after an RCC peripheral clock enabling */ \ 1169 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN); \ 1170 UNUSED(tmpreg); \ 1171 } while(0) 1172 #endif /* SDMMC2 */ 1173 1174 #if defined(FMC_BASE) 1175 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 1176 __IO uint32_t tmpreg; \ 1177 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1178 /* Delay after an RCC peripheral clock enabling */ \ 1179 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN); \ 1180 UNUSED(tmpreg); \ 1181 } while(0) 1182 #endif /* FMC_BASE */ 1183 1184 #if defined(OCTOSPI1) 1185 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 1186 __IO uint32_t tmpreg; \ 1187 SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1188 /* Delay after an RCC peripheral clock enabling */ \ 1189 tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN); \ 1190 UNUSED(tmpreg); \ 1191 } while(0) 1192 #endif /* OCTOSPI1 */ 1193 1194 #if defined(OTFDEC1) 1195 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) 1196 #endif /* OTFDEC1 */ 1197 1198 #if defined(SDMMC1) 1199 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) 1200 #endif /* SDMMC1 */ 1201 1202 #if defined(SDMMC2) 1203 #define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) 1204 #endif /* SDMMC2 */ 1205 1206 #if defined(FMC_BASE) 1207 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) 1208 #endif /* FMC_BASE */ 1209 1210 #if defined(OCTOSPI1) 1211 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) 1212 #endif /* OCTOSPI1 */ 1213 1214 /** 1215 * @} 1216 */ 1217 1218 1219 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 1220 * @brief Enable or disable the APB1 peripheral clock. 1221 * @note After reset, the peripheral clock (used for registers read/write access) 1222 * is disabled and the application software has to enable this clock before 1223 * using it. 1224 * @{ 1225 */ 1226 1227 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 1228 __IO uint32_t tmpreg; \ 1229 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1230 /* Delay after an RCC peripheral clock enabling */ \ 1231 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); \ 1232 UNUSED(tmpreg); \ 1233 } while(0) 1234 1235 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 1236 __IO uint32_t tmpreg; \ 1237 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1238 /* Delay after an RCC peripheral clock enabling */ \ 1239 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN); \ 1240 UNUSED(tmpreg); \ 1241 } while(0) 1242 1243 #if defined(TIM4) 1244 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN); \ 1249 UNUSED(tmpreg); \ 1250 } while(0) 1251 #endif /* TIM4 */ 1252 1253 #if defined(TIM5) 1254 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 1255 __IO uint32_t tmpreg; \ 1256 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1257 /* Delay after an RCC peripheral clock enabling */ \ 1258 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN); \ 1259 UNUSED(tmpreg); \ 1260 } while(0) 1261 #endif /* TIM5 */ 1262 1263 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 1264 __IO uint32_t tmpreg; \ 1265 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1266 /* Delay after an RCC peripheral clock enabling */ \ 1267 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN); \ 1268 UNUSED(tmpreg); \ 1269 } while(0) 1270 1271 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 1272 __IO uint32_t tmpreg; \ 1273 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1274 /* Delay after an RCC peripheral clock enabling */ \ 1275 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN); \ 1276 UNUSED(tmpreg); \ 1277 } while(0) 1278 1279 #if defined(TIM12) 1280 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1281 __IO uint32_t tmpreg; \ 1282 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1283 /* Delay after an RCC peripheral clock enabling */ \ 1284 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN); \ 1285 UNUSED(tmpreg); \ 1286 } while(0) 1287 1288 #endif /* TIM12 */ 1289 1290 #if defined(TIM13) 1291 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1292 __IO uint32_t tmpreg; \ 1293 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1294 /* Delay after an RCC peripheral clock enabling */ \ 1295 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN); \ 1296 UNUSED(tmpreg); \ 1297 } while(0) 1298 #endif /* TIM13 */ 1299 1300 #if defined(TIM14) 1301 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1302 __IO uint32_t tmpreg; \ 1303 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1304 /* Delay after an RCC peripheral clock enabling */ \ 1305 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN); \ 1306 UNUSED(tmpreg); \ 1307 } while(0) 1308 #endif /* TIM14 */ 1309 1310 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 1311 __IO uint32_t tmpreg; \ 1312 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1313 /* Delay after an RCC peripheral clock enabling */ \ 1314 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN); \ 1315 UNUSED(tmpreg); \ 1316 } while(0) 1317 1318 #if defined(OPAMP1) 1319 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1320 __IO uint32_t tmpreg; \ 1321 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1322 /* Delay after an RCC peripheral clock enabling */ \ 1323 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN); \ 1324 UNUSED(tmpreg); \ 1325 } while(0) 1326 #endif /* OPAMP1 */ 1327 1328 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1329 __IO uint32_t tmpreg; \ 1330 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1331 /* Delay after an RCC peripheral clock enabling */ \ 1332 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN); \ 1333 UNUSED(tmpreg); \ 1334 } while(0) 1335 1336 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1337 __IO uint32_t tmpreg; \ 1338 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1339 /* Delay after an RCC peripheral clock enabling */ \ 1340 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN); \ 1341 UNUSED(tmpreg); \ 1342 } while(0) 1343 1344 #if defined(COMP1) 1345 #define __HAL_RCC_COMP_CLK_ENABLE() do { \ 1346 __IO uint32_t tmpreg; \ 1347 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1348 /* Delay after an RCC peripheral clock enabling */ \ 1349 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN); \ 1350 UNUSED(tmpreg); \ 1351 } while(0) 1352 #endif /* COMP1 */ 1353 1354 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1355 __IO uint32_t tmpreg; \ 1356 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1357 /* Delay after an RCC peripheral clock enabling */ \ 1358 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN); \ 1359 UNUSED(tmpreg); \ 1360 } while(0) 1361 1362 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1363 __IO uint32_t tmpreg; \ 1364 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1365 /* Delay after an RCC peripheral clock enabling */ \ 1366 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN); \ 1367 UNUSED(tmpreg); \ 1368 } while(0) 1369 1370 #if defined(UART4) 1371 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1372 __IO uint32_t tmpreg; \ 1373 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1374 /* Delay after an RCC peripheral clock enabling */ \ 1375 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN); \ 1376 UNUSED(tmpreg); \ 1377 } while(0) 1378 #endif /* UART4 */ 1379 1380 #if defined(UART5) 1381 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1382 __IO uint32_t tmpreg; \ 1383 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1384 /* Delay after an RCC peripheral clock enabling */ \ 1385 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN); \ 1386 UNUSED(tmpreg); \ 1387 } while(0) 1388 #endif /* UART5 */ 1389 1390 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1391 __IO uint32_t tmpreg; \ 1392 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1393 /* Delay after an RCC peripheral clock enabling */ \ 1394 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN); \ 1395 UNUSED(tmpreg); \ 1396 } while(0) 1397 1398 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1399 __IO uint32_t tmpreg; \ 1400 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1401 /* Delay after an RCC peripheral clock enabling */ \ 1402 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN); \ 1403 UNUSED(tmpreg); \ 1404 } while(0) 1405 1406 #define __HAL_RCC_I3C1_CLK_ENABLE() do { \ 1407 __IO uint32_t tmpreg; \ 1408 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1409 /* Delay after an RCC peripheral clock enabling */ \ 1410 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN); \ 1411 UNUSED(tmpreg); \ 1412 } while(0) 1413 1414 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1415 __IO uint32_t tmpreg; \ 1416 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1417 /* Delay after an RCC peripheral clock enabling */ \ 1418 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN); \ 1419 UNUSED(tmpreg); \ 1420 } while(0) 1421 1422 #if defined(USART6) 1423 #define __HAL_RCC_USART6_CLK_ENABLE() do { \ 1424 __IO uint32_t tmpreg; \ 1425 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1426 /* Delay after an RCC peripheral clock enabling */ \ 1427 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN); \ 1428 UNUSED(tmpreg); \ 1429 } while(0) 1430 #endif /* USART6 */ 1431 1432 #if defined(USART10) 1433 #define __HAL_RCC_USART10_CLK_ENABLE() do { \ 1434 __IO uint32_t tmpreg; \ 1435 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1436 /* Delay after an RCC peripheral clock enabling */ \ 1437 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN); \ 1438 UNUSED(tmpreg); \ 1439 } while(0) 1440 #endif /* USART10 */ 1441 1442 #if defined(USART11) 1443 #define __HAL_RCC_USART11_CLK_ENABLE() do { \ 1444 __IO uint32_t tmpreg; \ 1445 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1446 /* Delay after an RCC peripheral clock enabling */ \ 1447 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN); \ 1448 UNUSED(tmpreg); \ 1449 } while(0) 1450 #endif /* USART11 */ 1451 1452 #if defined(CEC) 1453 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 1454 __IO uint32_t tmpreg; \ 1455 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1456 /* Delay after an RCC peripheral clock enabling */ \ 1457 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN); \ 1458 UNUSED(tmpreg); \ 1459 } while(0) 1460 #endif /* CEC */ 1461 1462 #if defined(UART7) 1463 #define __HAL_RCC_UART7_CLK_ENABLE() do { \ 1464 __IO uint32_t tmpreg; \ 1465 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1466 /* Delay after an RCC peripheral clock enabling */ \ 1467 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN); \ 1468 UNUSED(tmpreg); \ 1469 } while(0) 1470 #endif /* UART7 */ 1471 1472 #if defined(UART8) 1473 #define __HAL_RCC_UART8_CLK_ENABLE() do { \ 1474 __IO uint32_t tmpreg; \ 1475 SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1476 /* Delay after an RCC peripheral clock enabling */ \ 1477 tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN); \ 1478 UNUSED(tmpreg); \ 1479 } while(0) 1480 #endif /* UART8 */ 1481 1482 #if defined(UART9) 1483 #define __HAL_RCC_UART9_CLK_ENABLE() do { \ 1484 __IO uint32_t tmpreg; \ 1485 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1486 /* Delay after an RCC peripheral clock enabling */ \ 1487 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN); \ 1488 UNUSED(tmpreg); \ 1489 } while(0) 1490 #endif /* UART9 */ 1491 1492 #if defined(UART12) 1493 #define __HAL_RCC_UART12_CLK_ENABLE() do { \ 1494 __IO uint32_t tmpreg; \ 1495 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1496 /* Delay after an RCC peripheral clock enabling */ \ 1497 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN); \ 1498 UNUSED(tmpreg); \ 1499 } while(0) 1500 #endif /* UART12 */ 1501 1502 #define __HAL_RCC_DTS_CLK_ENABLE() do { \ 1503 __IO uint32_t tmpreg; \ 1504 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1505 /* Delay after an RCC peripheral clock enabling */ \ 1506 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN); \ 1507 UNUSED(tmpreg); \ 1508 } while(0) 1509 1510 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1511 __IO uint32_t tmpreg; \ 1512 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1513 /* Delay after an RCC peripheral clock enabling */ \ 1514 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN); \ 1515 UNUSED(tmpreg); \ 1516 } while(0) 1517 1518 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ 1519 __IO uint32_t tmpreg; \ 1520 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ 1521 /* Delay after an RCC peripheral clock enabling */ \ 1522 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN); \ 1523 UNUSED(tmpreg); \ 1524 } while(0) 1525 1526 #if defined(UCPD1) 1527 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1528 __IO uint32_t tmpreg; \ 1529 SET_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1530 /* Delay after an RCC peripheral clock enabling */ \ 1531 tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN); \ 1532 UNUSED(tmpreg); \ 1533 } while(0) 1534 #endif /* UCPD1 */ 1535 1536 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) 1537 1538 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) 1539 1540 #if defined(TIM4) 1541 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) 1542 #endif /* TIM4 */ 1543 1544 #if defined(TIM5) 1545 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) 1546 #endif /* TIM5 */ 1547 1548 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) 1549 1550 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) 1551 1552 #if defined(TIM12) 1553 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) 1554 #endif /* TIM12 */ 1555 1556 #if defined(TIM13) 1557 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) 1558 #endif /* TIM13 */ 1559 1560 #if defined(TIM14) 1561 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) 1562 #endif /* TIM14 */ 1563 1564 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) 1565 1566 #if defined(OPAMP1) 1567 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) 1568 #endif /* OPAMP1 */ 1569 1570 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) 1571 1572 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) 1573 1574 #if defined(COMP1) 1575 #define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) 1576 #endif /* COMP1 */ 1577 1578 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) 1579 1580 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) 1581 1582 #if defined(UART4) 1583 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) 1584 #endif /* UART4 */ 1585 1586 #if defined(UART5) 1587 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) 1588 #endif /* UART5 */ 1589 1590 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) 1591 1592 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) 1593 1594 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) 1595 1596 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) 1597 1598 #if defined(USART6) 1599 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) 1600 #endif /* USART6 */ 1601 1602 #if defined(USART10) 1603 #define __HAL_RCC_USART10_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) 1604 #endif /* USART10 */ 1605 1606 #if defined(USART11) 1607 #define __HAL_RCC_USART11_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) 1608 #endif /* USART11 */ 1609 1610 #if defined(CEC) 1611 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) 1612 #endif /* CEC */ 1613 1614 #if defined(UART7) 1615 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) 1616 #endif /* UART7 */ 1617 1618 #if defined(UART8) 1619 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) 1620 #endif /* UART8 */ 1621 1622 1623 #if defined(UART9) 1624 #define __HAL_RCC_UART9_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) 1625 #endif /* UART9 */ 1626 1627 #if defined(UART12) 1628 #define __HAL_RCC_UART12_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) 1629 #endif /* UART12 */ 1630 1631 #define __HAL_RCC_DTS_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR , RCC_APB1HENR_DTSEN) 1632 1633 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) 1634 1635 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) 1636 1637 #if defined(UCPD1) 1638 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) 1639 #endif /* UCPD1 */ 1640 1641 /** 1642 * @} 1643 */ 1644 1645 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1646 * @brief Enable or disable the APB2 peripheral clock. 1647 * @note After reset, the peripheral clock (used for registers read/write access) 1648 * is disabled and the application software has to enable this clock before 1649 * using it. 1650 * @{ 1651 */ 1652 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1653 __IO uint32_t tmpreg; \ 1654 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1655 /* Delay after an RCC peripheral clock enabling */ \ 1656 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1657 UNUSED(tmpreg); \ 1658 } while(0) 1659 1660 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1661 __IO uint32_t tmpreg; \ 1662 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1663 /* Delay after an RCC peripheral clock enabling */ \ 1664 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1665 UNUSED(tmpreg); \ 1666 } while(0) 1667 1668 #if defined(TIM8) 1669 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1670 __IO uint32_t tmpreg; \ 1671 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1672 /* Delay after an RCC peripheral clock enabling */ \ 1673 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1674 UNUSED(tmpreg); \ 1675 } while(0) 1676 #endif /* TIM8 */ 1677 1678 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1679 __IO uint32_t tmpreg; \ 1680 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1681 /* Delay after an RCC peripheral clock enabling */ \ 1682 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1683 UNUSED(tmpreg); \ 1684 } while(0) 1685 1686 #if defined(TIM15) 1687 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1688 __IO uint32_t tmpreg; \ 1689 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1690 /* Delay after an RCC peripheral clock enabling */ \ 1691 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1692 UNUSED(tmpreg); \ 1693 } while(0) 1694 #endif /* TIM15 */ 1695 1696 #if defined(TIM16) 1697 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1698 __IO uint32_t tmpreg; \ 1699 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1700 /* Delay after an RCC peripheral clock enabling */ \ 1701 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1702 UNUSED(tmpreg); \ 1703 } while(0) 1704 #endif /* TIM16 */ 1705 1706 #if defined(TIM17) 1707 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1708 __IO uint32_t tmpreg; \ 1709 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1710 /* Delay after an RCC peripheral clock enabling */ \ 1711 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1712 UNUSED(tmpreg); \ 1713 } while(0) 1714 #endif /* TIM17 */ 1715 1716 #if defined(SPI4) 1717 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ 1718 __IO uint32_t tmpreg; \ 1719 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1720 /* Delay after an RCC peripheral clock enabling */ \ 1721 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ 1722 UNUSED(tmpreg); \ 1723 } while(0) 1724 #endif /* SPI4 */ 1725 1726 #if defined(SPI6) 1727 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \ 1728 __IO uint32_t tmpreg; \ 1729 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1730 /* Delay after an RCC peripheral clock enabling */ \ 1731 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN); \ 1732 UNUSED(tmpreg); \ 1733 } while(0) 1734 #endif /* SPI6 */ 1735 1736 #if defined(SAI1) 1737 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1738 __IO uint32_t tmpreg; \ 1739 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1740 /* Delay after an RCC peripheral clock enabling */ \ 1741 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1742 UNUSED(tmpreg); \ 1743 } while(0) 1744 #endif /* SAI1 */ 1745 1746 #if defined(SAI2) 1747 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1748 __IO uint32_t tmpreg; \ 1749 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1750 /* Delay after an RCC peripheral clock enabling */ \ 1751 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1752 UNUSED(tmpreg); \ 1753 } while(0) 1754 #endif /* SAI2 */ 1755 1756 #if defined(USB_DRD_FS) 1757 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1758 __IO uint32_t tmpreg; \ 1759 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1760 /* Delay after an RCC peripheral clock enabling */ \ 1761 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ 1762 UNUSED(tmpreg); \ 1763 } while(0) 1764 #endif /*USB_DRD_FS*/ 1765 1766 1767 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1768 1769 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1770 1771 #if defined(TIM8) 1772 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1773 #endif /* TIM8 */ 1774 1775 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1776 1777 #if defined(TIM15) 1778 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1779 #endif /* TIM15 */ 1780 1781 #if defined(TIM16) 1782 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1783 #endif /* TIM16 */ 1784 1785 #if defined(TIM17) 1786 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1787 #endif /* TIM17 */ 1788 1789 #if defined(SPI4) 1790 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) 1791 #endif /* SPI4 */ 1792 1793 #if defined(SPI6) 1794 #define __HAL_RCC_SPI6_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) 1795 #endif /* SPI6 */ 1796 1797 #if defined(SAI1) 1798 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1799 #endif /* SAI1 */ 1800 1801 #if defined(SAI2) 1802 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1803 #endif /* SAI2 */ 1804 1805 #if defined(USB_DRD_FS) 1806 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) 1807 #endif /* USB_DRD_FS */ 1808 /** 1809 * @} 1810 */ 1811 1812 /** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable 1813 * @brief Enable or disable the APB3 peripheral clock. 1814 * @note After reset, the peripheral clock (used for registers read/write access) 1815 * is disabled and the application software has to enable this clock before 1816 * using it. 1817 * @{ 1818 */ 1819 #define __HAL_RCC_SBS_CLK_ENABLE() do { \ 1820 __IO uint32_t tmpreg; \ 1821 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1822 /* Delay after an RCC peripheral clock enabling */ \ 1823 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN); \ 1824 UNUSED(tmpreg); \ 1825 } while(0) 1826 1827 #if defined(SPI5) 1828 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \ 1829 __IO uint32_t tmpreg; \ 1830 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1831 /* Delay after an RCC peripheral clock enabling */ \ 1832 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN); \ 1833 UNUSED(tmpreg); \ 1834 } while(0) 1835 #endif /* SPI5 */ 1836 1837 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1838 __IO uint32_t tmpreg; \ 1839 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1840 /* Delay after an RCC peripheral clock enabling */ \ 1841 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ 1842 UNUSED(tmpreg); \ 1843 } while(0) 1844 1845 #if defined(I2C3) 1846 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1847 __IO uint32_t tmpreg; \ 1848 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1849 /* Delay after an RCC peripheral clock enabling */ \ 1850 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ 1851 UNUSED(tmpreg); \ 1852 } while(0) 1853 #endif /* I2C3 */ 1854 1855 #if defined(I2C4) 1856 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1857 __IO uint32_t tmpreg; \ 1858 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1859 /* Delay after an RCC peripheral clock enabling */ \ 1860 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN); \ 1861 UNUSED(tmpreg); \ 1862 } while(0) 1863 #endif /* I2C4 */ 1864 1865 #if defined(I3C2) 1866 #define __HAL_RCC_I3C2_CLK_ENABLE() do { \ 1867 __IO uint32_t tmpreg; \ 1868 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1869 /* Delay after an RCC peripheral clock enabling */ \ 1870 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN); \ 1871 UNUSED(tmpreg); \ 1872 } while(0) 1873 #endif /* I3C2 */ 1874 1875 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1876 __IO uint32_t tmpreg; \ 1877 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1878 /* Delay after an RCC peripheral clock enabling */ \ 1879 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ 1880 UNUSED(tmpreg); \ 1881 } while(0) 1882 1883 #if defined(LPTIM3) 1884 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1885 __IO uint32_t tmpreg; \ 1886 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1887 /* Delay after an RCC peripheral clock enabling */ \ 1888 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ 1889 UNUSED(tmpreg); \ 1890 } while(0) 1891 #endif /* LPTIM3 */ 1892 1893 #if defined(LPTIM4) 1894 #define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ 1895 __IO uint32_t tmpreg; \ 1896 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1897 /* Delay after an RCC peripheral clock enabling */ \ 1898 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ 1899 UNUSED(tmpreg); \ 1900 } while(0) 1901 #endif /* LPTIM4 */ 1902 1903 #if defined(LPTIM5) 1904 #define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ 1905 __IO uint32_t tmpreg; \ 1906 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1907 /* Delay after an RCC peripheral clock enabling */ \ 1908 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN); \ 1909 UNUSED(tmpreg); \ 1910 } while(0) 1911 #endif /* LPTIM5 */ 1912 1913 #if defined(LPTIM6) 1914 #define __HAL_RCC_LPTIM6_CLK_ENABLE() do { \ 1915 __IO uint32_t tmpreg; \ 1916 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1917 /* Delay after an RCC peripheral clock enabling */ \ 1918 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN); \ 1919 UNUSED(tmpreg); \ 1920 } while(0) 1921 #endif /* LPTIM6 */ 1922 1923 #if defined(VREFBUF) 1924 #define __HAL_RCC_VREF_CLK_ENABLE() do { \ 1925 __IO uint32_t tmpreg; \ 1926 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1927 /* Delay after an RCC peripheral clock enabling */ \ 1928 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ 1929 UNUSED(tmpreg); \ 1930 } while(0) 1931 #endif /* VREFBUF */ 1932 1933 #define __HAL_RCC_RTC_CLK_ENABLE() do { \ 1934 __IO uint32_t tmpreg; \ 1935 SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1936 /* Delay after an RCC peripheral clock enabling */ \ 1937 tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ 1938 UNUSED(tmpreg); \ 1939 } while(0) 1940 1941 #define __HAL_RCC_SBS_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) 1942 1943 #if defined(SPI5) 1944 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) 1945 #endif /* SPI5 */ 1946 1947 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) 1948 1949 #if defined(I2C3) 1950 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) 1951 #endif /* I2C3 */ 1952 1953 #if defined(I2C4) 1954 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) 1955 #endif /* I2C4 */ 1956 1957 #if defined(I3C2) 1958 #define __HAL_RCC_I3C2_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) 1959 #endif /* I3C2 */ 1960 1961 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) 1962 1963 #if defined(LPTIM3) 1964 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) 1965 #endif /* LPTIM3 */ 1966 1967 #if defined(LPTIM4) 1968 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) 1969 #endif /* LPTIM4 */ 1970 1971 #if defined(LPTIM5) 1972 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) 1973 #endif /* LPTIM5 */ 1974 1975 #if defined(LPTIM6) 1976 #define __HAL_RCC_LPTIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) 1977 #endif /* LPTIM6 */ 1978 1979 #if defined(VREFBUF) 1980 #define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) 1981 #endif /* VREFBUF */ 1982 1983 #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) 1984 1985 /** 1986 * @} 1987 */ 1988 1989 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable AHB APB Branch Clock Disable Clear Disable 1990 * @brief Disable or clear Disable the AHBx/APBx branch clock for all AHBx/APBx peripherals. 1991 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 1992 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 1993 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 1994 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 1995 * @{ 1996 */ 1997 1998 #define __HAL_RCC_AHB1_CLK_DISABLE() do { \ 1999 __IO uint32_t tmpreg; \ 2000 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2001 /* Delay after AHB peripherals bus clocks branch disable */ \ 2002 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ 2003 UNUSED(tmpreg); \ 2004 } while(0) 2005 2006 #define __HAL_RCC_AHB2_CLK_DISABLE() do { \ 2007 __IO uint32_t tmpreg; \ 2008 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2009 /* Delay after AHB peripherals bus clocks branch disable */ \ 2010 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS); \ 2011 UNUSED(tmpreg); \ 2012 } while(0) 2013 2014 #if defined(AHB4PERIPH_BASE) 2015 #define __HAL_RCC_AHB4_CLK_DISABLE() do { \ 2016 __IO uint32_t tmpreg; \ 2017 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2018 /* Delay after AHB peripherals bus clocks branch disable */ \ 2019 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS); \ 2020 UNUSED(tmpreg); \ 2021 } while(0) 2022 #endif /* AHB4PERIPH_BASE */ 2023 2024 #define __HAL_RCC_APB1_CLK_DISABLE() do { \ 2025 __IO uint32_t tmpreg; \ 2026 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2027 /* Delay after APB peripherals bus clocks branch disable */ \ 2028 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ 2029 UNUSED(tmpreg); \ 2030 } while(0) 2031 2032 #define __HAL_RCC_APB2_CLK_DISABLE() do { \ 2033 __IO uint32_t tmpreg; \ 2034 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2035 /* Delay after APB peripherals bus clocks branch disable */ \ 2036 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ 2037 UNUSED(tmpreg); \ 2038 } while(0) 2039 2040 #define __HAL_RCC_APB3_CLK_DISABLE() do { \ 2041 __IO uint32_t tmpreg; \ 2042 SET_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2043 /* Delay after APB peripherals bus clocks branch disable */ \ 2044 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS); \ 2045 UNUSED(tmpreg); \ 2046 } while(0) 2047 2048 2049 #define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) 2050 2051 #define __HAL_RCC_AHB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) 2052 2053 #if defined(AHB4PERIPH_BASE) 2054 #define __HAL_RCC_AHB4_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) 2055 #endif /* AHB4PERIPH_BASE */ 2056 2057 #define __HAL_RCC_APB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) 2058 2059 #define __HAL_RCC_APB2_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) 2060 2061 #define __HAL_RCC_APB3_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) 2062 2063 /** 2064 * @} 2065 */ 2066 2067 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 2068 * @brief Check whether the AHB1 peripheral clock is enabled or not. 2069 * @note After reset, the peripheral clock (used for registers read/write access) 2070 * is disabled and the application software has to enable this clock before 2071 * using it. 2072 * @{ 2073 */ 2074 #define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) 2075 2076 #define __HAL_RCC_GPDMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) != 0U) 2077 2078 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) != 0U) 2079 2080 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 2081 2082 #if defined(CORDIC) 2083 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) 2084 #endif /* CORDIC */ 2085 2086 #if defined(FMAC) 2087 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) 2088 #endif /* FMAC */ 2089 2090 #define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) 2091 2092 #if defined(ETH) 2093 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) != 0U) 2094 2095 #define __HAL_RCC_ETHTX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) != 0U) 2096 2097 #define __HAL_RCC_ETHRX_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) != 0U) 2098 #endif /*ETH*/ 2099 2100 #define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) != 0U) 2101 2102 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) != 0U) 2103 2104 #if defined(DCACHE1) 2105 #define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) 2106 #endif /* DCACHE1 */ 2107 2108 #define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) 2109 2110 2111 #define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) 2112 2113 #define __HAL_RCC_GPDMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN) == 0U) 2114 2115 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN) == 0U) 2116 2117 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 2118 2119 #if defined(CORDIC) 2120 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) 2121 #endif /* CORDIC */ 2122 2123 #if defined(FMAC) 2124 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) 2125 #endif /* FMAC */ 2126 2127 #define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) 2128 2129 #if defined(ETH) 2130 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN) == 0U) 2131 2132 #define __HAL_RCC_ETHTX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) == 0U) 2133 2134 #define __HAL_RCC_ETHRX_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) == 0U) 2135 #endif /*ETH*/ 2136 2137 #define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) == 0U) 2138 2139 #define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPRAMEN) == 0U) 2140 2141 #if defined(DCACHE1) 2142 #define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) 2143 #endif /* DCACHE1 */ 2144 2145 #define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) 2146 /** 2147 * @} 2148 */ 2149 2150 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 2151 * @brief Check whether the AHB2 peripheral clock is enabled or not. 2152 * @note After reset, the peripheral clock (used for registers read/write access) 2153 * is disabled and the application software has to enable this clock before 2154 * using it. 2155 * @{ 2156 */ 2157 2158 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 2159 2160 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) 2161 2162 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 2163 2164 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 2165 2166 #if defined(GPIOE) 2167 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 2168 #endif /* GPIOE */ 2169 2170 #if defined(GPIOF) 2171 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 2172 #endif /* GPIOF */ 2173 2174 #if defined(GPIOG) 2175 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 2176 #endif /* GPIOG */ 2177 2178 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 2179 2180 #if defined(GPIOI) 2181 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != 0U) 2182 #endif /* GPIOI */ 2183 2184 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 2185 2186 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) 2187 2188 #if defined(DCMI) 2189 #define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) != 0U) 2190 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility */ 2191 #endif /* DCMI */ 2192 2193 #if defined(AES) 2194 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 2195 #endif /* AES */ 2196 2197 #if defined(HASH) 2198 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 2199 #endif /* HASH */ 2200 2201 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 2202 2203 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 2204 2205 #if defined(SAES) 2206 #define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) 2207 #endif /*SAES*/ 2208 2209 #define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) 2210 2211 #if defined(SRAM3_BASE) 2212 #define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) != 0U) 2213 #endif /* SRAM3_BASE */ 2214 2215 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 2216 2217 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 2218 2219 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 2220 2221 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 2222 2223 #if defined(GPIOE) 2224 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 2225 #endif /* GPIOE */ 2226 2227 #if defined(GPIOF) 2228 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 2229 #endif /* GPIOF */ 2230 2231 #if defined(GPIOG) 2232 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 2233 #endif /* GPIOG */ 2234 2235 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 2236 2237 #if defined(GPIOI) 2238 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == 0U) 2239 #endif /* GPIOI */ 2240 2241 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 2242 2243 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) 2244 2245 #if defined(DCMI) 2246 #define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN) == 0U) 2247 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility */ 2248 #endif /* DCMI */ 2249 2250 #if defined(AES) 2251 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 2252 #endif /* AES */ 2253 2254 #if defined(HASH) 2255 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 2256 #endif /* HASH */ 2257 2258 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 2259 2260 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 2261 2262 #if defined(SAES) 2263 #define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) == 0U) 2264 #endif /* SAES */ 2265 2266 #define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) == 0U) 2267 2268 #if defined(SRAM3_BASE) 2269 #define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM3EN) == 0U) 2270 #endif /* SRAM3_BASE */ 2271 /** 2272 * @} 2273 */ 2274 2275 /** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status 2276 * @brief Check whether the AHB4 peripheral clock is enabled or not. 2277 * @note After reset, the peripheral clock (used for registers read/write access) 2278 * is disabled and the application software has to enable this clock before 2279 * using it. 2280 * @{ 2281 */ 2282 2283 #if defined(OTFDEC1) 2284 #define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) != 0U) 2285 #endif /* OTFDEC1 */ 2286 2287 #if defined(SDMMC1) 2288 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) != 0U) 2289 #endif /* SDMMC1 */ 2290 2291 #if defined(SDMMC2) 2292 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) != 0U) 2293 #endif /* SDMMC2 */ 2294 2295 #if defined(FMC_BASE) 2296 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) != 0U) 2297 #endif /* FMC_BASE */ 2298 2299 #if defined(OCTOSPI1) 2300 #define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) != 0U) 2301 #endif /* OCTOSPI1 */ 2302 2303 #if defined(OTFDEC1) 2304 #define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OTFDEC1EN) == 0U) 2305 #endif /* OTFDEC1 */ 2306 2307 #if defined(SDMMC1) 2308 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC1EN) == 0U) 2309 #endif /* SDMMC1 */ 2310 2311 #if defined(SDMMC2) 2312 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SDMMC2EN) == 0U) 2313 #endif /* SDMMC2 */ 2314 2315 #if defined(FMC_BASE) 2316 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_FMCEN) == 0U) 2317 #endif /* FMC_BASE */ 2318 2319 #if defined(OCTOSPI1) 2320 #define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) == 0U) 2321 #endif /* OCTOSPI1 */ 2322 2323 /** 2324 * @} 2325 */ 2326 2327 2328 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 2329 * @brief Check whether the APB1 peripheral clock is enabled or not. 2330 * @note After reset, the peripheral clock (used for registers read/write access) 2331 * is disabled and the application software has to enable this clock before 2332 * using it. 2333 * @{ 2334 */ 2335 2336 2337 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) != 0U) 2338 2339 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) != 0U) 2340 2341 #if defined(TIM4) 2342 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) != 0U) 2343 #endif /* TIM4 */ 2344 2345 #if defined(TIM5) 2346 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) != 0U) 2347 #endif /* TIM5 */ 2348 2349 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) != 0U) 2350 2351 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) != 0U) 2352 2353 #if defined(TIM12) 2354 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) != 0U) 2355 #endif /* TIM12 */ 2356 2357 #if defined(TIM13) 2358 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) != 0U) 2359 #endif /* TIM13 */ 2360 2361 #if defined(TIM14) 2362 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) != 0U) 2363 #endif /* TIM14 */ 2364 2365 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) != 0U) 2366 2367 #if defined(OPAMP1) 2368 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) != 0U) 2369 #endif /* OPAMP1 */ 2370 2371 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) != 0U) 2372 2373 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) != 0U) 2374 2375 #if defined(COMP1) 2376 #define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) != 0U) 2377 #endif /* COMP1 */ 2378 2379 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) != 0U) 2380 2381 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) != 0U) 2382 2383 #if defined(UART4) 2384 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) != 0U) 2385 #endif /* UART4 */ 2386 2387 #if defined(UART5) 2388 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) != 0U) 2389 #endif /* UART5 */ 2390 2391 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) != 0U) 2392 2393 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) != 0U) 2394 2395 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) != 0U) 2396 2397 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) != 0U) 2398 2399 #if defined(USART6) 2400 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) != 0U) 2401 #endif /* USART6 */ 2402 2403 #if defined(USART10) 2404 #define __HAL_RCC_USART10_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) != 0U) 2405 #endif /* USART10 */ 2406 2407 #if defined(USART11) 2408 #define __HAL_RCC_USART11_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) != 0U) 2409 #endif /* USART11 */ 2410 2411 #if defined(CEC) 2412 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) != 0U) 2413 #endif /* CEC */ 2414 2415 #if defined(UART7) 2416 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) != 0U) 2417 #endif /* UART7 */ 2418 2419 #if defined(UART8) 2420 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) != 0U) 2421 #endif /* UART8 */ 2422 2423 2424 #if defined(UART9) 2425 #define __HAL_RCC_UART9_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) != 0U) 2426 #endif /* UART9 */ 2427 2428 #if defined(UART12) 2429 #define __HAL_RCC_UART12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) != 0U) 2430 #endif /* UART12 */ 2431 2432 #define __HAL_RCC_DTS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) != 0U) 2433 2434 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) != 0U) 2435 2436 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) != 0U) 2437 2438 #if defined(UCPD1) 2439 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) != 0U) 2440 #endif /* UCPD1 */ 2441 2442 2443 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN) == 0U) 2444 2445 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN) == 0U) 2446 2447 #if defined(TIM4) 2448 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN) == 0U) 2449 #endif /* TIM4 */ 2450 2451 #if defined(TIM5) 2452 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN) == 0U) 2453 #endif /* TIM5 */ 2454 2455 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN) == 0U) 2456 2457 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN) == 0U) 2458 2459 #if defined(TIM12) 2460 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN) == 0U) 2461 #endif /* TIM12 */ 2462 2463 #if defined(TIM13) 2464 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN) == 0U) 2465 #endif /* TIM13 */ 2466 2467 #if defined(TIM14) 2468 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN) == 0U) 2469 #endif /* TIM14 */ 2470 2471 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDGEN) == 0U) 2472 2473 #if defined(OPAMP1) 2474 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_OPAMPEN) == 0U) 2475 #endif /* OPAMP1 */ 2476 2477 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN) == 0U) 2478 2479 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN) == 0U) 2480 2481 #if defined(COMP1) 2482 #define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_COMPEN) == 0U) 2483 #endif /* COMP1 */ 2484 2485 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN) == 0U) 2486 2487 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN) == 0U) 2488 2489 #if defined(UART4) 2490 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN) == 0U) 2491 #endif /* UART4 */ 2492 2493 #if defined(UART5) 2494 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN) == 0U) 2495 #endif /* UART5 */ 2496 2497 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN) == 0U) 2498 2499 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN) == 0U) 2500 2501 #define __HAL_RCC_I3C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I3C1EN) == 0U) 2502 2503 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CRSEN) == 0U) 2504 2505 #if defined(USART6) 2506 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART6EN) == 0U) 2507 #endif /* USART6 */ 2508 2509 #if defined(USART10) 2510 #define __HAL_RCC_USART10_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART10EN) == 0U) 2511 #endif /* USART10 */ 2512 2513 #if defined(USART11) 2514 #define __HAL_RCC_USART11_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART11EN) == 0U) 2515 #endif /* USART11 */ 2516 2517 #if defined(CEC) 2518 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN) == 0U) 2519 #endif /* CEC */ 2520 2521 #if defined(UART7) 2522 #define __HAL_RCC_UART7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN) == 0U) 2523 #endif /* UART7 */ 2524 2525 #if defined(UART8) 2526 #define __HAL_RCC_UART8_IS_CLK_DISABLED() (READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN) == 0U) 2527 #endif /* UART8 */ 2528 2529 2530 #if defined(UART9) 2531 #define __HAL_RCC_UART9_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART9EN) == 0U) 2532 #endif /* UART9 */ 2533 2534 #if defined(UART12) 2535 #define __HAL_RCC_UART12_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UART12EN) == 0U) 2536 #endif /* UART12 */ 2537 2538 #define __HAL_RCC_DTS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_DTSEN) == 0U) 2539 2540 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_LPTIM2EN) == 0U) 2541 2542 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN) == 0U) 2543 2544 #if defined(UCPD1) 2545 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1HENR, RCC_APB1HENR_UCPD1EN) == 0U) 2546 #endif /* UCPD1 */ 2547 /** 2548 * @} 2549 */ 2550 2551 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 2552 * @brief Check whether the APB2 peripheral clock is enabled or not. 2553 * @note After reset, the peripheral clock (used for registers read/write access) 2554 * is disabled and the application software has to enable this clock before 2555 * using it. 2556 * @{ 2557 */ 2558 2559 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 2560 2561 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 2562 2563 #if defined(TIM8) 2564 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 2565 #endif /* TIM8 */ 2566 2567 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 2568 2569 #if defined(TIM15) 2570 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 2571 #endif /* TIM15 */ 2572 2573 #if defined(TIM16) 2574 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 2575 #endif /* TIM16 */ 2576 2577 #if defined(TIM17) 2578 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 2579 #endif /* TIM17 */ 2580 2581 #if defined(SPI4) 2582 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) 2583 #endif /* SPI4 */ 2584 2585 #if defined(SPI6) 2586 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) != 0U) 2587 #endif /* SPI6 */ 2588 2589 #if defined(SAI1) 2590 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 2591 #endif /* SAI1 */ 2592 2593 #if defined(SAI2) 2594 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 2595 #endif /* SAI2 */ 2596 2597 #if defined(USB_DRD_FS) 2598 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) 2599 #endif /* USB_DRD_FS */ 2600 2601 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 2602 2603 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 2604 2605 #if defined(TIM8) 2606 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 2607 #endif /* TIM8 */ 2608 2609 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 2610 2611 #if defined(TIM15) 2612 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 2613 #endif /* TIM15 */ 2614 2615 #if defined(TIM16) 2616 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 2617 #endif /* TIM16 */ 2618 2619 #if defined(TIM17) 2620 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 2621 #endif /* TIM17 */ 2622 2623 #if defined(SPI4) 2624 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) 2625 #endif /* SPI4 */ 2626 2627 #if defined(SPI6) 2628 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN) == 0U) 2629 #endif /* SPI6 */ 2630 2631 #if defined(SAI1) 2632 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 2633 #endif /* SAI1 */ 2634 2635 #if defined(SAI2) 2636 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 2637 #endif /* SAI2 */ 2638 2639 #if defined(USB_DRD_FS) 2640 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) 2641 #endif /* USB_DRD_FS */ 2642 /** 2643 * @} 2644 */ 2645 2646 /** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status 2647 * @brief Check whether the APB3 peripheral clock is enabled or not. 2648 * @note After reset, the peripheral clock (used for registers read/write access) 2649 * is disabled and the application software has to enable this clock before 2650 * using it. 2651 * @{ 2652 */ 2653 2654 #define __HAL_RCC_SBS_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) != 0U) 2655 2656 #if defined(SPI5) 2657 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) != 0U) 2658 #endif /* SPI5 */ 2659 2660 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) 2661 2662 #if defined(I2C3) 2663 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) 2664 #endif /* I2C3 */ 2665 2666 #if defined(I2C4) 2667 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) != 0U) 2668 #endif /* I2C4 */ 2669 2670 #if defined(I3C2) 2671 #define __HAL_RCC_I3C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) != 0U) 2672 #endif /* I3C2 */ 2673 2674 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) 2675 2676 #if defined(LPTIM3) 2677 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) 2678 #endif /* LPTIM3 */ 2679 2680 #if defined(LPTIM4) 2681 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) 2682 #endif /* LPTIM4 */ 2683 2684 #if defined(LPTIM5) 2685 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) != 0U) 2686 #endif /* LPTIM5 */ 2687 2688 #if defined(LPTIM6) 2689 #define __HAL_RCC_LPTIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) != 0U) 2690 #endif /* LPTIM6 */ 2691 2692 #if defined(VREFBUF) 2693 #define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) 2694 #endif /* VREFBUF */ 2695 2696 #define __HAL_RCC_RTC_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) 2697 2698 #define __HAL_RCC_SBS_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SBSEN) == 0U) 2699 2700 #if defined(SPI5) 2701 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI5EN) == 0U) 2702 #endif /* SPI5 */ 2703 2704 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) 2705 2706 #if defined(I2C3) 2707 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) 2708 #endif /* I2C3 */ 2709 2710 #if defined(I2C4) 2711 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C4EN) == 0U) 2712 #endif /* I2C4 */ 2713 2714 #if defined(I3C2) 2715 #define __HAL_RCC_I3C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I3C2EN) == 0U) 2716 #endif /* I3C2 */ 2717 2718 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) 2719 2720 #if defined(LPTIM3) 2721 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) 2722 #endif /* LPTIM3 */ 2723 2724 #if defined(LPTIM4) 2725 #define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) 2726 #endif /* LPTIM4 */ 2727 2728 #if defined(LPTIM5) 2729 #define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM5EN) == 0U) 2730 #endif /* LPTIM5 */ 2731 2732 #if defined(LPTIM6) 2733 #define __HAL_RCC_LPTIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM6EN) == 0U) 2734 #endif /* LPTIM6 */ 2735 2736 #if defined(VREFBUF) 2737 #define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) 2738 #endif /* VREFBUF */ 2739 2740 #define __HAL_RCC_RTC_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) 2741 2742 /** 2743 * @} 2744 */ 2745 2746 /** @defgroup RCC_AHB_APB_Branch_Clock_Disable_Status AHB APB Branch Clock Disabled Status 2747 * @brief Check whether the AHBx/APBx branch clock for all AHBx/APBx peripherals is disabled or not. 2748 * @note It is recommended to disable the clock of all peripherals (by writing 0 in 2749 * the AHBxENR/APBxENR register) before Disabling the corresponding Bus Branch clock. 2750 * Some peripheral bus clocks are not affected by branch clock disabling as IWDG (APB1), 2751 * SRAM2/SRAM3 (AHB2) and FLITF/BKRAM/ICACHE/DCACHE/SRAM1 (AHB1). 2752 * @{ 2753 */ 2754 2755 #define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U) 2756 2757 #define __HAL_RCC_AHB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS) != 0U) 2758 2759 #if defined(AHB4PERIPH_BASE) 2760 #define __HAL_RCC_AHB4_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB4DIS) != 0U) 2761 #endif /* AHB4PERIPH_BASE */ 2762 2763 #define __HAL_RCC_APB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS) != 0U) 2764 2765 #define __HAL_RCC_APB2_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS) != 0U) 2766 2767 #define __HAL_RCC_APB3_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_APB3DIS) != 0U) 2768 2769 /** 2770 * @} 2771 */ 2772 2773 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 2774 * @brief Force or release AHB1 peripheral reset. 2775 * @{ 2776 */ 2777 2778 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x010AD003U) 2779 2780 #define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2781 2782 #define __HAL_RCC_GPDMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2783 2784 #if defined(CORDIC) 2785 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2786 #endif /* CORDIC */ 2787 2788 #if defined(FMAC) 2789 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2790 #endif /* FMAC */ 2791 2792 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2793 2794 #define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2795 2796 #if defined(ETH) 2797 #define __HAL_RCC_ETH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2798 #endif /* ETH */ 2799 2800 #define __HAL_RCC_GTZC1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2801 2802 2803 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 2804 2805 #define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) 2806 2807 #define __HAL_RCC_GPDMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA2RST) 2808 2809 #if defined(CORDIC) 2810 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) 2811 #endif /* CORDIC */ 2812 2813 #if defined(FMAC) 2814 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) 2815 #endif /* FMAC */ 2816 2817 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 2818 2819 #define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) 2820 2821 #if defined(ETH) 2822 #define __HAL_RCC_ETH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_ETHRST) 2823 #endif /* ETH */ 2824 2825 #define __HAL_RCC_GTZC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TZSC1RST) 2826 2827 /** 2828 * @} 2829 */ 2830 2831 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 2832 * @brief Force or release AHB2 peripheral reset. 2833 * @{ 2834 */ 2835 2836 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x001F1DFFU) 2837 2838 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2839 2840 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2841 2842 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2843 2844 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2845 2846 #if defined(GPIOE) 2847 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2848 #endif /* GPIOE */ 2849 2850 #if defined(GPIOF) 2851 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2852 #endif /* GPIOF */ 2853 2854 #if defined(GPIOG) 2855 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2856 #endif /* GPIOG */ 2857 2858 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2859 2860 #if defined(GPIOI) 2861 #define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2862 #endif /* GPIOI */ 2863 2864 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2865 2866 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 2867 2868 #if defined(DCMI) 2869 #define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2870 #define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility */ 2871 #endif /* DCMI */ 2872 2873 #if defined(AES) 2874 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2875 #endif /* AES */ 2876 2877 #if defined(HASH) 2878 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2879 #endif /* HASH */ 2880 2881 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2882 2883 #if defined(PKA) 2884 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2885 #endif /* PKA */ 2886 2887 #if defined(SAES) 2888 #define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2889 #endif /* SAES*/ 2890 2891 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 2892 2893 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 2894 2895 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 2896 2897 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 2898 2899 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 2900 2901 #if defined(GPIOE) 2902 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 2903 #endif /* GPIOE */ 2904 2905 #if defined(GPIOF) 2906 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 2907 #endif /* GPIOF */ 2908 2909 #if defined(GPIOG) 2910 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 2911 #endif /* GPIOG */ 2912 2913 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 2914 2915 #if defined(GPIOG) 2916 #define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) 2917 #endif /* GPIOI */ 2918 2919 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 2920 2921 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) 2922 2923 #if defined(DCMI) 2924 #define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMI_PSSIRST) 2925 #define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility */ 2926 #endif /* DCMI */ 2927 2928 #if defined(AES) 2929 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 2930 #endif /* AES */ 2931 2932 #if defined(HASH) 2933 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 2934 #endif /* HASH */ 2935 2936 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 2937 2938 #if defined(PKA) 2939 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 2940 #endif /* PKA */ 2941 2942 #if defined(SAES) 2943 #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) 2944 #endif /* SAES*/ 2945 2946 /** 2947 * @} 2948 */ 2949 2950 /** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset 2951 * @brief Force or release AHB4 peripheral reset. 2952 * @{ 2953 */ 2954 2955 #if defined(FMC_BASE) 2956 #define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00111880U) 2957 #endif /* FMC_BASE */ 2958 2959 #if defined(OTFDEC1) 2960 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 2961 #endif /* OTFDEC1 */ 2962 2963 #if defined(SDMMC1) 2964 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 2965 #endif /* SDMMC1 */ 2966 2967 #if defined(SDMMC2) 2968 #define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 2969 #endif /* SDMMC2 */ 2970 2971 #if defined(FMC_BASE) 2972 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 2973 #endif /* FMC_BASE */ 2974 2975 #if defined(OCTOSPI1) 2976 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 2977 #endif /* OCTOSPI1 */ 2978 2979 #if defined(FMC_BASE) 2980 #define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) 2981 #endif /* FMC_BASE */ 2982 2983 #if defined(OTFDEC1) 2984 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OTFDEC1RST) 2985 #endif /* OTFDEC1 */ 2986 2987 #if defined(SDMMC1) 2988 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC1RST) 2989 #endif /* SDMMC1 */ 2990 2991 #if defined(SDMMC2) 2992 #define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_SDMMC2RST) 2993 #endif /* SDMMC2 */ 2994 2995 #if defined(FMC_BASE) 2996 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_FMCRST) 2997 #endif /* FMC_BASE */ 2998 2999 #if defined(OCTOSPI1) 3000 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_OCTOSPI1RST) 3001 #endif /* OCTOSPI1 */ 3002 3003 /** 3004 * @} 3005 */ 3006 3007 3008 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 3009 * @brief Force or release APB1 peripheral reset. 3010 * @{ 3011 */ 3012 3013 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 3014 WRITE_REG(RCC->APB1LRSTR, 0xDFFEC1FFU); \ 3015 WRITE_REG(RCC->APB1HRSTR, 0x4080062BU); \ 3016 } while(0) 3017 3018 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3019 3020 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3021 3022 #if defined(TIM4) 3023 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3024 #endif /* TIM4 */ 3025 3026 #if defined(TIM5) 3027 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3028 #endif /* TIM5 */ 3029 3030 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3031 3032 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3033 3034 #if defined(TIM12) 3035 #define __HAL_RCC_TIM12_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3036 #endif /* TIM12 */ 3037 3038 #if defined(TIM13) 3039 #define __HAL_RCC_TIM13_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3040 #endif /* TIM13 */ 3041 3042 #if defined(TIM14) 3043 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3044 #endif /* TIM14 */ 3045 3046 #if defined(OPAMP1) 3047 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3048 #endif /* OPAMP1 */ 3049 3050 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3051 3052 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3053 3054 #if defined(COMP1) 3055 #define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3056 #endif /* COMP1 */ 3057 3058 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3059 3060 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3061 3062 #if defined(UART4) 3063 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3064 #endif /* UART4 */ 3065 3066 #if defined(UART5) 3067 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3068 #endif /* UART5 */ 3069 3070 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3071 3072 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3073 3074 #define __HAL_RCC_I3C1_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3075 3076 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3077 3078 #if defined(USART6) 3079 #define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3080 #endif /* USART6 */ 3081 3082 #if defined(USART10) 3083 #define __HAL_RCC_USART10_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3084 #endif /* USART10 */ 3085 3086 #if defined(USART11) 3087 #define __HAL_RCC_USART11_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3088 #endif /* USART11 */ 3089 3090 #if defined(CEC) 3091 #define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3092 #endif /* CEC */ 3093 3094 #if defined(UART7) 3095 #define __HAL_RCC_UART7_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3096 #endif /* UART7 */ 3097 3098 #if defined(UART8) 3099 #define __HAL_RCC_UART8_FORCE_RESET() SET_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3100 #endif /* UART8 */ 3101 3102 3103 #if defined(UART9) 3104 #define __HAL_RCC_UART9_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3105 #endif /* UART9 */ 3106 3107 #if defined(UART12) 3108 #define __HAL_RCC_UART12_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3109 #endif /* UART12 */ 3110 3111 #define __HAL_RCC_DTS_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3112 3113 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3114 3115 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) 3116 3117 #if defined(UCPD1) 3118 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3119 #endif /* UCPD1 */ 3120 3121 3122 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 3123 WRITE_REG(RCC->APB1LRSTR, 0x00000000U); \ 3124 WRITE_REG(RCC->APB1HRSTR, 0x00000000U); \ 3125 } while(0) 3126 3127 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM2RST) 3128 3129 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM3RST) 3130 3131 #if defined(TIM4) 3132 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM4RST) 3133 #endif /* TIM4 */ 3134 3135 #if defined(TIM5) 3136 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM5RST) 3137 #endif /* TIM5 */ 3138 3139 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM6RST) 3140 3141 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM7RST) 3142 3143 #if defined(TIM12) 3144 #define __HAL_RCC_TIM12_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM12RST) 3145 #endif /* TIM12 */ 3146 3147 #if defined(TIM13) 3148 #define __HAL_RCC_TIM13_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM13RST) 3149 #endif /* TIM13 */ 3150 3151 #if defined(TIM14) 3152 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_TIM14RST) 3153 #endif /* TIM14 */ 3154 3155 #if defined(OPAMP1) 3156 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_OPAMPRST) 3157 #endif /* OPAMP1 */ 3158 3159 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI2RST) 3160 3161 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_SPI3RST) 3162 3163 #if defined(COMP1) 3164 #define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_COMPRST) 3165 #endif /* COMP1 */ 3166 3167 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART2RST) 3168 3169 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART3RST) 3170 3171 #if defined(UART4) 3172 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART4RST) 3173 #endif /* UART4 */ 3174 3175 #if defined(UART5) 3176 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART5RST) 3177 #endif /* UART5 */ 3178 3179 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C1RST) 3180 3181 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I2C2RST) 3182 3183 #define __HAL_RCC_I3C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_I3C1RST) 3184 3185 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CRSRST) 3186 3187 #if defined(USART6) 3188 #define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART6RST) 3189 #endif /* USART6 */ 3190 3191 #if defined(USART10) 3192 #define __HAL_RCC_USART10_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART10RST) 3193 #endif /* USART10 */ 3194 3195 #if defined(USART11) 3196 #define __HAL_RCC_USART11_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_USART11RST) 3197 #endif /* USART11 */ 3198 3199 #if defined(CEC) 3200 #define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_CECRST) 3201 #endif /* CEC */ 3202 3203 #if defined(UART7) 3204 #define __HAL_RCC_UART7_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART7RST) 3205 #endif /* UART7 */ 3206 3207 #if defined(UART8) 3208 #define __HAL_RCC_UART8_RELEASE_RESET() CLEAR_BIT(RCC->APB1LRSTR, RCC_APB1LRSTR_UART8RST) 3209 #endif /* UART8 */ 3210 3211 3212 #if defined(UART9) 3213 #define __HAL_RCC_UART9_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART9RST) 3214 #endif /* UART9 */ 3215 3216 #if defined(UART12) 3217 #define __HAL_RCC_UART12_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UART12RST) 3218 #endif /* UART12 */ 3219 3220 #define __HAL_RCC_DTS_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_DTSRST) 3221 3222 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_LPTIM2RST) 3223 3224 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_FDCANRST) 3225 3226 #if defined(UCPD1) 3227 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_UCPD1RST) 3228 #endif /* UCPD1 */ 3229 3230 /** 3231 * @} 3232 */ 3233 3234 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 3235 * @brief Force or release APB2 peripheral reset. 3236 * @{ 3237 */ 3238 3239 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x017F7800U) 3240 3241 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3242 3243 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3244 3245 #if defined(TIM8) 3246 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3247 #endif /* TIM8 */ 3248 3249 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3250 3251 #if defined(TIM15) 3252 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3253 #endif /* TIM15 */ 3254 3255 #if defined(TIM16) 3256 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3257 #endif /* TIM16 */ 3258 3259 #if defined(TIM17) 3260 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3261 #endif /* TIM17 */ 3262 3263 #if defined(SPI4) 3264 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3265 #endif /* SPI4 */ 3266 3267 #if defined(SPI6) 3268 #define __HAL_RCC_SPI6_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3269 #endif /* SPI6 */ 3270 3271 #if defined(SAI1) 3272 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3273 #endif /* SAI1 */ 3274 3275 #if defined(SAI2) 3276 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3277 #endif /* SAI2 */ 3278 3279 #if defined(USB_DRD_FS) 3280 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3281 #endif /* USB_DRD_FS */ 3282 3283 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 3284 3285 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 3286 3287 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 3288 3289 #if defined(TIM8) 3290 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 3291 #endif /* TIM8 */ 3292 3293 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 3294 3295 #if defined(TIM15) 3296 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 3297 #endif /* TIM15 */ 3298 3299 #if defined(TIM16) 3300 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 3301 #endif /* TIM16 */ 3302 3303 #if defined(TIM17) 3304 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 3305 #endif /* TIM17 */ 3306 3307 #if defined(SPI4) 3308 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) 3309 #endif /* SPI4 */ 3310 3311 #if defined(SPI6) 3312 #define __HAL_RCC_SPI6_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI6RST) 3313 #endif /* SPI6 */ 3314 3315 #if defined(SAI1) 3316 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 3317 #endif /* SAI1 */ 3318 3319 #if defined(SAI2) 3320 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 3321 #endif /* SAI2 */ 3322 3323 #if defined(USB_DRD_FS) 3324 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) 3325 #endif /* USB_DRD_FS */ 3326 3327 /** 3328 * @} 3329 */ 3330 3331 /** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset 3332 * @brief Force or release APB3 peripheral reset. 3333 * @{ 3334 */ 3335 3336 #define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x001008E0U) 3337 3338 #if defined(SPI5) 3339 #define __HAL_RCC_SPI5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3340 #endif /* SPI5 */ 3341 3342 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3343 3344 #if defined(I2C3) 3345 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3346 #endif /* I2C3 */ 3347 3348 #if defined(I2C4) 3349 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3350 #endif /* I2C4 */ 3351 3352 #if defined(I3C2) 3353 #define __HAL_RCC_I3C2_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3354 #endif /* I3C2 */ 3355 3356 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3357 3358 #if defined(LPTIM3) 3359 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3360 #endif /* LPTIM3 */ 3361 3362 #if defined(LPTIM4) 3363 #define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3364 #endif /* LPTIM4 */ 3365 3366 #if defined(LPTIM5) 3367 #define __HAL_RCC_LPTIM5_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3368 #endif /* LPTIM5 */ 3369 3370 #if defined(LPTIM6) 3371 #define __HAL_RCC_LPTIM6_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3372 #endif /* LPTIM6 */ 3373 3374 #if defined(VREFBUF) 3375 #define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3376 #endif /* VREFBUF */ 3377 3378 #define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) 3379 3380 #if defined(SPI5) 3381 #define __HAL_RCC_SPI5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI5RST) 3382 #endif /* SPI5 */ 3383 3384 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) 3385 3386 #if defined(I2C3) 3387 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) 3388 #endif /* I2C3 */ 3389 3390 #if defined(I2C4) 3391 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C4RST) 3392 #endif /* I2C4 */ 3393 3394 #if defined(I3C2) 3395 #define __HAL_RCC_I3C2_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I3C2RST) 3396 #endif /* I3C2 */ 3397 3398 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) 3399 3400 #if defined(LPTIM3) 3401 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) 3402 #endif /* LPTIM3 */ 3403 3404 #if defined(LPTIM4) 3405 #define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) 3406 #endif /* LPTIM4 */ 3407 3408 #if defined(LPTIM5) 3409 #define __HAL_RCC_LPTIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM5RST) 3410 #endif /* LPTIM5 */ 3411 3412 #if defined(LPTIM6) 3413 #define __HAL_RCC_LPTIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM6RST) 3414 #endif /* LPTIM6 */ 3415 3416 #if defined(VREFBUF) 3417 #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) 3418 #endif /* VREFBUF */ 3419 3420 /** 3421 * @} 3422 */ 3423 3424 /** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 3425 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 3426 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3427 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3428 * @{ 3429 */ 3430 3431 #define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3432 3433 #define __HAL_RCC_GPDMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3434 3435 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3436 3437 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3438 3439 #if defined(CORDIC) 3440 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3441 #endif /* CORDIC */ 3442 3443 #if defined(FMAC) 3444 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3445 #endif /* FMAC */ 3446 3447 #define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3448 3449 #if defined(ETH) 3450 #define __HAL_RCC_ETH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3451 3452 #define __HAL_RCC_ETHTX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3453 3454 #define __HAL_RCC_ETHRX_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3455 #endif /* ETH */ 3456 3457 #define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3458 3459 #define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3460 3461 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3462 3463 #if defined(DCACHE1) 3464 #define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3465 #endif /* DCACHE1 */ 3466 3467 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3468 3469 3470 #define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA1LPEN) 3471 3472 #define __HAL_RCC_GPDMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_GPDMA2LPEN) 3473 3474 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FLITFLPEN) 3475 3476 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CRCLPEN) 3477 3478 #if defined(CORDIC) 3479 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_CORDICLPEN) 3480 #endif /* CORDIC */ 3481 3482 #if defined(FMAC) 3483 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_FMACLPEN) 3484 #endif /* FMAC */ 3485 3486 #define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_RAMCFGLPEN) 3487 3488 #if defined(ETH) 3489 #define __HAL_RCC_ETH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHLPEN) 3490 3491 #define __HAL_RCC_ETHTX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHTXLPEN) 3492 3493 #define __HAL_RCC_ETHRX_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ETHRXLPEN) 3494 #endif /* ETH */ 3495 3496 #define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_TZSC1LPEN) 3497 3498 #define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_BKPRAMLPEN) 3499 3500 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_ICACHELPEN) 3501 3502 #if defined(DCACHE1) 3503 #define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_DCACHE1LPEN) 3504 #endif /* DCACHE1 */ 3505 3506 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_SRAM1LPEN) 3507 3508 /** 3509 * @} 3510 */ 3511 3512 /** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 3513 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 3514 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3515 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3516 * @{ 3517 */ 3518 3519 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3520 3521 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3522 3523 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3524 3525 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3526 3527 #if defined(GPIOE) 3528 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3529 #endif /* GPIOE */ 3530 3531 #if defined(GPIOF) 3532 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3533 #endif /* GPIOF */ 3534 3535 #if defined(GPIOG) 3536 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3537 #endif /* GPIOG */ 3538 3539 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3540 3541 #if defined(GPIOI) 3542 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3543 #endif /* GPIOI */ 3544 3545 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) 3546 3547 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) 3548 3549 #if defined(DCMI) 3550 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3551 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility */ 3552 #endif /* DCMI */ 3553 3554 #if defined(AES) 3555 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3556 #endif /* AES */ 3557 3558 #if defined(HASH) 3559 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3560 #endif /* HASH */ 3561 3562 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3563 3564 #if defined(PKA) 3565 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3566 #endif /*PKA*/ 3567 3568 #if defined(SAES) 3569 #define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3570 #endif /* AES */ 3571 3572 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3573 3574 #if defined(SRAM3_BASE) 3575 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3576 #endif /* SRAM3_BASE */ 3577 3578 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOALPEN) 3579 3580 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOBLPEN) 3581 3582 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOCLPEN) 3583 3584 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIODLPEN) 3585 3586 #if defined(GPIOE) 3587 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOELPEN) 3588 #endif /* GPIOE */ 3589 3590 #if defined(GPIOF) 3591 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOFLPEN) 3592 #endif /* GPIOF */ 3593 3594 #if defined(GPIOG) 3595 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOGLPEN) 3596 #endif /* GPIOG */ 3597 3598 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOHLPEN) 3599 3600 #if defined(GPIOI) 3601 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_GPIOILPEN) 3602 #endif /* GPIOI */ 3603 3604 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_ADCLPEN) 3605 3606 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DAC1LPEN) 3607 3608 #if defined(DCMI) 3609 #define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_DCMI_PSSILPEN) 3610 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility */ 3611 #endif /* DCMI */ 3612 3613 #if defined(AES) 3614 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_AESLPEN); 3615 #endif /* AES */ 3616 3617 #if defined(HASH) 3618 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_HASHLPEN) 3619 #endif /* HASH */ 3620 3621 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN) 3622 3623 #if defined(PKA) 3624 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_PKALPEN) 3625 #endif /*PKA*/ 3626 3627 #define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SAESLPEN) 3628 3629 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM2LPEN) 3630 3631 #if defined(SRAM3_BASE) 3632 #define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2LPENR, RCC_AHB2LPENR_SRAM3LPEN) 3633 #endif /* SRAM3_BASE */ 3634 /** 3635 * @} 3636 */ 3637 3638 /** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4 Peripheral Clock Sleep Enable Disable 3639 * @brief Enable or disable the AHB4 peripheral clock during Low Power (Sleep) mode. 3640 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3641 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3642 * @{ 3643 */ 3644 3645 #if defined(OTFDEC1) 3646 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3647 #endif /* OTFDEC1 */ 3648 3649 #if defined(SDMMC1) 3650 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3651 #endif /* SDMMC1*/ 3652 3653 #if defined(SDMMC2) 3654 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3655 #endif /* SDMMC2*/ 3656 3657 #if defined(FMC_BASE) 3658 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3659 #endif /* FMC_BASE */ 3660 3661 #if defined(OCTOSPI1) 3662 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3663 #endif /* OCTOSPI1 */ 3664 3665 #if defined(OTFDEC1) 3666 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OTFDEC1LPEN) 3667 #endif /* OTFDEC1 */ 3668 3669 #if defined(SDMMC1) 3670 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC1LPEN) 3671 #endif /* SDMMC1*/ 3672 3673 #if defined(SDMMC2) 3674 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_SDMMC2LPEN) 3675 #endif /* SDMMC2*/ 3676 3677 #if defined(FMC_BASE) 3678 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_FMCLPEN) 3679 #endif /* FMC_BASE */ 3680 3681 #if defined(OCTOSPI1) 3682 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4LPENR, RCC_AHB4LPENR_OCTOSPI1LPEN) 3683 #endif /* OCTOSPI1 */ 3684 3685 /** 3686 * @} 3687 */ 3688 3689 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 3690 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 3691 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3692 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3693 * @{ 3694 */ 3695 3696 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3697 3698 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3699 3700 #if defined(TIM4) 3701 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3702 #endif /* TIM4 */ 3703 3704 #if defined(TIM5) 3705 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3706 #endif /* TIM5 */ 3707 3708 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3709 3710 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3711 3712 #if defined(TIM12) 3713 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3714 #endif /* TIM12 */ 3715 3716 #if defined(TIM13) 3717 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3718 #endif /* TIM13 */ 3719 3720 #if defined(TIM14) 3721 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3722 #endif /* TIM14 */ 3723 3724 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3725 3726 #if defined(OPAMP1) 3727 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3728 #endif /* OPAMP1 */ 3729 3730 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3731 3732 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3733 3734 #if defined(COMP1) 3735 #define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3736 #endif /* COMP1 */ 3737 3738 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3739 3740 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3741 3742 #if defined(UART4) 3743 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3744 #endif /* UART4 */ 3745 3746 #if defined(UART5) 3747 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3748 #endif /* UART5 */ 3749 3750 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3751 3752 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3753 3754 #define __HAL_RCC_I3C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3755 3756 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3757 3758 #if defined(USART6) 3759 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3760 #endif /* USART6 */ 3761 3762 #if defined(USART10) 3763 #define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3764 #endif /* USART10 */ 3765 3766 #if defined(USART11) 3767 #define __HAL_RCC_USART11_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3768 #endif /* USART11 */ 3769 3770 #if defined(CEC) 3771 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3772 #endif /* CEC */ 3773 3774 #if defined(UART7) 3775 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3776 #endif /* UART7 */ 3777 3778 #if defined(UART8) 3779 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3780 #endif /* UART8 */ 3781 3782 3783 #if defined(UART9) 3784 #define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3785 #endif /* UART9 */ 3786 3787 #if defined(UART12) 3788 #define __HAL_RCC_UART12_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3789 #endif /* UART12 */ 3790 3791 #define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3792 3793 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3794 3795 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) 3796 3797 #if defined(UCPD1) 3798 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3799 #endif /* UCPD1 */ 3800 3801 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM2LPEN) 3802 3803 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM3LPEN) 3804 3805 #if defined(TIM4) 3806 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM4LPEN) 3807 #endif /* TIM4 */ 3808 3809 #if defined(TIM5) 3810 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM5LPEN) 3811 #endif /* TIM5 */ 3812 3813 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM6LPEN) 3814 3815 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM7LPEN) 3816 3817 #if defined(TIM12) 3818 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM12LPEN) 3819 #endif /* TIM12 */ 3820 3821 #if defined(TIM13) 3822 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM13LPEN) 3823 #endif /* TIM12 */ 3824 3825 #if defined(TIM14) 3826 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_TIM14LPEN) 3827 #endif /* TIM14 */ 3828 3829 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_WWDGLPEN) 3830 3831 #if defined(OPAMP1) 3832 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_OPAMPLPEN) 3833 #endif /* OPAMP1 */ 3834 3835 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN) 3836 3837 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN) 3838 3839 #if defined(COMP1) 3840 #define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_COMPLPEN) 3841 #endif /* COMP1 */ 3842 3843 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART2LPEN) 3844 3845 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART3LPEN) 3846 3847 #if defined(UART4) 3848 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART4LPEN) 3849 #endif /* UART4 */ 3850 3851 #if defined(UART5) 3852 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART5LPEN) 3853 #endif /* UART5 */ 3854 3855 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C1LPEN) 3856 3857 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I2C2LPEN) 3858 3859 #define __HAL_RCC_I3C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_I3C1LPEN) 3860 3861 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CRSLPEN) 3862 3863 #if defined(USART6) 3864 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART6LPEN) 3865 #endif /* USART6 */ 3866 3867 #if defined(USART10) 3868 #define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART10LPEN) 3869 #endif /* USART10 */ 3870 3871 #if defined(USART11) 3872 #define __HAL_RCC_USART11_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_USART11LPEN) 3873 #endif /* USART11 */ 3874 3875 #if defined(CEC) 3876 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_CECLPEN) 3877 #endif /* CEC */ 3878 3879 #if defined(UART7) 3880 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART7LPEN) 3881 #endif /* UART7 */ 3882 3883 #if defined(UART8) 3884 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1LLPENR, RCC_APB1LLPENR_UART8LPEN) 3885 #endif /* UART8 */ 3886 3887 3888 #if defined(UART9) 3889 #define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART9LPEN) 3890 #endif /* UART9 */ 3891 3892 #if defined(UART12) 3893 #define __HAL_RCC_UART12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UART12LPEN) 3894 #endif /* UART12 */ 3895 3896 #define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_DTSLPEN) 3897 3898 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_LPTIM2LPEN) 3899 3900 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_FDCANLPEN) 3901 3902 #if defined(UCPD1) 3903 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1HLPENR, RCC_APB1HLPENR_UCPD1LPEN) 3904 #endif /* UCPD1 */ 3905 3906 /** 3907 * @} 3908 */ 3909 3910 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 3911 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 3912 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 3913 * @note By default, all peripheral clocks are enabled during SLEEP mode. 3914 * @{ 3915 */ 3916 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3917 3918 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3919 3920 #if defined(TIM8) 3921 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3922 #endif /* TIM8 */ 3923 3924 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3925 3926 #if defined(TIM15) 3927 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3928 #endif /* TIM15 */ 3929 3930 #if defined(TIM16) 3931 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3932 #endif /* TIM16 */ 3933 3934 #if defined(TIM17) 3935 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3936 #endif /* TIM17 */ 3937 3938 #if defined(SPI4) 3939 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3940 #endif /* SPI4 */ 3941 3942 #if defined(SPI6) 3943 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 3944 #endif /* SPI6 */ 3945 3946 #if defined(SAI1) 3947 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3948 #endif /* SAI1 */ 3949 3950 #if defined(SAI2) 3951 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3952 #endif /* SAI2 */ 3953 3954 #if defined(USB_DRD_FS) 3955 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 3956 #endif /* USB_DRD_FS */ 3957 3958 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM1LPEN) 3959 3960 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN) 3961 3962 #if defined(TIM8) 3963 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM8LPEN) 3964 #endif /* TIM8 */ 3965 3966 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USART1LPEN) 3967 3968 #if defined(TIM15) 3969 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM15LPEN) 3970 #endif /* TIM15 */ 3971 3972 #if defined(TIM16) 3973 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM16LPEN) 3974 #endif /* TIM16 */ 3975 3976 #if defined(TIM17) 3977 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_TIM17LPEN) 3978 #endif /* TIM17 */ 3979 3980 #if defined(SPI4) 3981 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN) 3982 #endif /* SPI4 */ 3983 3984 #if defined(SPI6) 3985 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SPI6LPEN) 3986 #endif /* SPI6 */ 3987 3988 #if defined(SAI1) 3989 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI1LPEN) 3990 #endif /* SAI1 */ 3991 3992 #if defined(SAI2) 3993 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_SAI2LPEN) 3994 #endif /* SAI2 */ 3995 3996 #if defined(USB_DRD_FS) 3997 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2LPENR, RCC_APB2LPENR_USBLPEN) 3998 #endif /* USB_DRD_FS */ 3999 4000 /** 4001 * @} 4002 */ 4003 4004 /** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable 4005 * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode. 4006 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 4007 * @note By default, all peripheral clocks are enabled during SLEEP mode. 4008 * @{ 4009 */ 4010 #define __HAL_RCC_SBS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 4011 4012 #if defined(SPI5) 4013 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4014 #endif /* SPI5 */ 4015 4016 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4017 4018 #if defined(I2C3) 4019 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4020 #endif /* I2C3 */ 4021 4022 #if defined(I2C4) 4023 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4024 #endif /* I2C4 */ 4025 4026 #if defined(I3C2) 4027 #define __HAL_RCC_I3C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4028 #endif /* I3C2 */ 4029 4030 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4031 4032 #if defined(LPTIM3) 4033 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4034 #endif /* LPTIM3 */ 4035 4036 #if defined(LPTIM4) 4037 #define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4038 #endif /* LPTIM4 */ 4039 4040 #if defined(LPTIM5) 4041 #define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4042 #endif /* LPTIM5 */ 4043 4044 #if defined(LPTIM6) 4045 #define __HAL_RCC_LPTIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4046 #endif /* LPTIM6 */ 4047 4048 #if defined(VREFBUF) 4049 #define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4050 #endif /* VREFBUF */ 4051 4052 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4053 4054 #define __HAL_RCC_SBS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SBSLPEN) 4055 4056 #if defined(SPI5) 4057 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_SPI5LPEN) 4058 #endif /* SPI5 */ 4059 4060 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPUART1LPEN) 4061 4062 #if defined(I2C3) 4063 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C3LPEN) 4064 #endif /* I2C3 */ 4065 4066 #if defined(I2C4) 4067 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I2C4LPEN) 4068 #endif /* I2C4 */ 4069 4070 #if defined(I3C2) 4071 #define __HAL_RCC_I3C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_I3C2LPEN) 4072 #endif /* I3C2 */ 4073 4074 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM1LPEN) 4075 4076 #if defined(LPTIM3) 4077 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM3LPEN) 4078 #endif /* LPTIM3 */ 4079 4080 #if defined(LPTIM4) 4081 #define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM4LPEN) 4082 #endif /* LPTIM4 */ 4083 4084 #if defined(LPTIM5) 4085 #define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM5LPEN) 4086 #endif /* LPTIM5 */ 4087 4088 #if defined(LPTIM6) 4089 #define __HAL_RCC_LPTIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_LPTIM6LPEN) 4090 #endif /* LPTIM6 */ 4091 4092 #if defined(VREFBUF) 4093 #define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_VREFLPEN) 4094 #endif /* VREFBUF */ 4095 4096 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) 4097 4098 /** 4099 * @} 4100 */ 4101 4102 4103 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 4104 * @{ 4105 */ 4106 4107 /** @brief Macros to force or release the Backup domain reset. 4108 * @note This function resets the RTC peripheral (including the backup registers) 4109 * and the RTC clock source selection in RCC_BDCR register. 4110 * @note The BKPSRAM is not affected by this reset. 4111 * @retval None 4112 */ 4113 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4114 4115 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST) 4116 4117 /** 4118 * @} 4119 */ 4120 4121 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 4122 * @{ 4123 */ 4124 4125 /** @brief Macros to enable or disable the RTC clock. 4126 * @note As the RTC is in the Backup domain and write access is denied to 4127 * this domain after reset, you have to enable write access using 4128 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 4129 * (to be done once after reset). 4130 * @note These macros must be used after the RTC clock source was selected. 4131 * @retval None 4132 */ 4133 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4134 4135 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 4136 4137 /** 4138 * @} 4139 */ 4140 4141 /** @brief Macro to configure the Internal High Speed oscillator (HSI). 4142 * @param __HSIDIV__ specifies the HSI division factor. 4143 * This parameter can be one of the following values: 4144 * @arg RCC_HSI_DIV1 Divide the HSI oscillator clock by 1 (default after reset) 4145 * @arg RCC_HSI_DIV2 Divide the HSI oscillator clock by 2 4146 * @arg RCC_HSI_DIV4 Divide the HSI oscillator clock by 4 4147 * @arg RCC_HSI_DIV8 Divide the HSI oscillator clock by 8 4148 */ 4149 #define __HAL_RCC_HSI_DIVIDER_CONFIG(__HSIDIV__) \ 4150 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV , (uint32_t)(__HSIDIV__)) 4151 4152 4153 /** @brief Macro to get the HSI divider. 4154 * @retval The HSI divider. The returned value can be one 4155 * of the following: 4156 * - RCC_HSI_DIV1 HSI oscillator divided by 1 4157 * - RCC_HSI_DIV2 HSI oscillator divided by 2 4158 * - RCC_HSI_DIV4 HSI oscillator divided by 4 4159 * - RCC_HSI_DIV8 HSI oscillator divided by 8 4160 */ 4161 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 4162 4163 /** @brief Macros to enable or disable the Internal High Speed 64MHz oscillator (HSI). 4164 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 4165 * It is used (enabled by hardware) as system clock source after startup 4166 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 4167 * of the HSE used directly or indirectly as system clock (if the HSE Clock 4168 * Security System HSECSS is enabled). 4169 * @note HSI can not be stopped if it is used as system clock source. In this case, 4170 * you have to select another source of the system clock then stop the HSI. 4171 * @note After enabling the HSI, the application software should wait on HSIRDY 4172 * flag to be set indicating that HSI clock is stable and can be used as 4173 * system clock source. 4174 * This parameter can be: ENABLE or DISABLE. 4175 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 4176 * clock cycles. 4177 * @retval None 4178 */ 4179 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 4180 4181 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 4182 4183 /** @brief Macro to adjust the Internal High Speed 64MHz oscillator (HSI) calibration value. 4184 * @note The calibration is used to compensate for the variations in voltage 4185 * and temperature that influence the frequency of the internal HSI RC. 4186 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 4187 * (default is RCC_HSICALIBRATION_DEFAULT). 4188 * This parameter must be a number between 0 and 0x7F. 4189 * @retval None 4190 */ 4191 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 4192 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_HSICFGR_HSITRIM_Pos) 4193 4194 /** 4195 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 4196 * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. 4197 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 4198 * speed because of the HSI startup time. 4199 * @note The enable of this function has not effect on the HSION bit. 4200 * This parameter can be: ENABLE or DISABLE. 4201 * @retval None 4202 */ 4203 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 4204 4205 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 4206 4207 /** 4208 * @brief Macros to enable or disable the Internal Low-power oscillator (CSI). 4209 * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. 4210 * It is used (enabled by hardware) as system clock source after 4211 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 4212 * of failure of the HSE used directly or indirectly as system clock 4213 * (if the HSE Clock Security System HSECSS is enabled and CSI is selected 4214 * as system clock after wake up from system stop). 4215 * @note CSI can not be stopped if it is used as system clock source. 4216 * In this case, you have to select another source of the system 4217 * clock then stop the CSI. 4218 * @note After enabling the CSI, the application software should wait on 4219 * CSIRDY flag to be set indicating that CSI clock is stable and can 4220 * be used as system clock source. 4221 * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator 4222 * clock cycles. 4223 * @retval None 4224 */ 4225 #define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) 4226 4227 #define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) 4228 4229 /** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. 4230 * @note The calibration is used to compensate for the variations in voltage 4231 * and temperature that influence the frequency of the internal CSI RC. 4232 * @param __CSICalibrationValue__: specifies the calibration trimming value. 4233 * This parameter must be a number between 0 and 0x3F. 4234 */ 4235 #define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ 4236 do { \ 4237 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ 4238 } while(0) 4239 4240 /** 4241 * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) 4242 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 4243 * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication 4244 * speed because of the CSI start-up time. 4245 * @note The enable of this function has not effect on the CSION bit. 4246 * This parameter can be: ENABLE or DISABLE. 4247 * @retval None 4248 */ 4249 #define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) 4250 #define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) 4251 4252 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 4253 * @note After enabling the LSI, the application software should wait on 4254 * LSIRDY flag to be set indicating that LSI clock is stable and can 4255 * be used to clock the IWDG and/or the RTC. 4256 * @note LSI can not be disabled if the IWDG is running. 4257 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 4258 * clock cycles. 4259 * @retval None 4260 */ 4261 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) 4262 4263 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION) 4264 4265 /** 4266 * @brief Macro to configure the External High Speed oscillator (HSE). 4267 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 4268 * supported by this macro. User should request a transition to HSE Off 4269 * first and then HSE On or HSE Bypass. 4270 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 4271 * software should wait on HSERDY flag to be set indicating that HSE clock 4272 * is stable and can be used to clock the PLLs and/or system clock. 4273 * @note HSE state can not be changed if it is used directly or through the 4274 * PLL1 as system clock. In this case, you have to select another source 4275 * of the system clock then change the HSE state (ex. disable it). 4276 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 4277 * @param __STATE__: specifies the new state of the HSE. 4278 * This parameter can be one of the following values: 4279 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 4280 * 6 HSE oscillator clock cycles. 4281 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 4282 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 4283 * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed with digital external clock. 4284 * @retval None 4285 */ 4286 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 4287 do { \ 4288 if ((__STATE__) == RCC_HSE_ON) \ 4289 { \ 4290 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4291 } \ 4292 else if ((__STATE__) == RCC_HSE_OFF) \ 4293 { \ 4294 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4295 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4296 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4297 } \ 4298 else if ((__STATE__) == RCC_HSE_BYPASS) \ 4299 { \ 4300 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4301 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4302 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4303 } \ 4304 else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ 4305 { \ 4306 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4307 SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4308 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 4309 } \ 4310 else \ 4311 { \ 4312 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 4313 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 4314 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ 4315 } \ 4316 } while(0) 4317 4318 /** 4319 * @brief Macro to configure the External Low Speed oscillator (LSE). 4320 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 4321 * supported by this macro. User should request a transition to LSE Off 4322 * first and then LSE On or LSE Bypass. 4323 * @note As the LSE is in the Backup domain and write access is denied to 4324 * this domain after reset, you have to enable write access using 4325 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4326 * (to be done once after reset). 4327 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 4328 * software should wait on LSERDY flag to be set indicating that LSE clock 4329 * is stable and can be used to clock the RTC. 4330 * @param __STATE__: specifies the new state of the LSE. 4331 * This parameter can be one of the following values: 4332 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 4333 * 6 LSE oscillator clock cycles. 4334 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 4335 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 4336 * @arg @ref RCC_LSE_BYPASS_DIGITAL LSE oscillator bypassed with external digital clock. 4337 * @retval None 4338 */ 4339 4340 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 4341 do { \ 4342 if((__STATE__) == RCC_LSE_ON) \ 4343 { \ 4344 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4345 } \ 4346 else if((__STATE__) == RCC_LSE_OFF) \ 4347 { \ 4348 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4349 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4350 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4351 } \ 4352 else if((__STATE__) == RCC_LSE_BYPASS) \ 4353 { \ 4354 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4355 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4356 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4357 } \ 4358 else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ 4359 { \ 4360 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4361 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4362 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4363 } \ 4364 else \ 4365 { \ 4366 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 4367 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 4368 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ 4369 } \ 4370 } while(0) 4371 4372 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 4373 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 4374 * @note After enabling the HSI48, the application software should wait on HSI48RDY 4375 * flag to be set indicating that HSI48 clock is stable. 4376 * This parameter can be: ENABLE or DISABLE. 4377 * @retval None 4378 */ 4379 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) 4380 4381 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) 4382 4383 /** @brief Macros to configure the RTC clock (RTCCLK). 4384 * @note As the RTC clock configuration bits are in the Backup domain and write 4385 * access is denied to this domain after reset, you have to enable write 4386 * access using the Power Backup Access macro before to configure 4387 * the RTC clock source (to be done once after reset). 4388 * @note Once the RTC clock is configured it cannot be changed unless the 4389 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by 4390 * a Power On Reset (POR). 4391 * @param __RTCCLKSource__: specifies the RTC clock source. 4392 * This parameter can be one of the following values: 4393 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4394 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4395 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected 4396 * as RTC clock, where x can be between 2 and 63 4397 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 4398 * work in STOP and STANDBY modes, and can be used as wakeup source. 4399 * However, when the HSE clock is used as RTC clock source, the RTC 4400 * cannot be used in STOP and STANDBY modes. 4401 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 4402 * RTC clock source). 4403 */ 4404 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ 4405 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_RTCPRE, \ 4406 (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE) 4407 4408 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ 4409 RCC->BDCR &= ~RCC_BDCR_RTCSEL; \ 4410 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ 4411 } while (0) 4412 4413 /** @brief Macro to get the RTC clock source. 4414 * @retval The returned value can be one of the following: 4415 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 4416 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 4417 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 4418 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVx HSE clock divided by x selected as 4419 * RTC clock, where x can be between 2 and 63 4420 (x can be retrieved with @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()) 4421 */ 4422 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 4423 4424 /** @brief Macro to get the HSE division factor for RTC clock. 4425 * 4426 * @retval The HSE division factor for RTC clock. The returned value can be one 4427 * of the following: 4428 * @arg @ref RCC_RTC_HSE_NOCLOCK : No HSE Clock selected as RTC clock 4429 * @arg @ref RCC_RTC_HSE_DIV2 : HSE Divided by 2 selected as RTC clock 4430 * @arg @ref RCC_RTC_HSE_DIV3 : HSE Divided by 3 selected as RTC clock 4431 * @arg @ref RCC_RTC_HSE_DIV4 : HSE Divided by 4 selected as RTC clock 4432 * @arg @ref RCC_RTC_HSE_DIV5 : HSE Divided by 5 selected as RTC clock 4433 * @arg @ref RCC_RTC_HSE_DIV6 : HSE Divided by 6 selected as RTC clock 4434 * @arg @ref RCC_RTC_HSE_DIV7 : HSE Divided by 7 selected as RTC clock 4435 * @arg @ref RCC_RTC_HSE_DIV8 : HSE Divided by 8 selected as RTC clock 4436 * @arg @ref RCC_RTC_HSE_DIV9 : HSE Divided by 9 selected as RTC clock 4437 * @arg @ref RCC_RTC_HSE_DIV10 : HSE Divided by 10 selected as RTC clock 4438 * @arg @ref RCC_RTC_HSE_DIV11 : HSE Divided by 11 selected as RTC clock 4439 * @arg @ref RCC_RTC_HSE_DIV12 : HSE Divided by 12 selected as RTC clock 4440 * @arg @ref RCC_RTC_HSE_DIV13 : HSE Divided by 13 selected as RTC clock 4441 * @arg @ref RCC_RTC_HSE_DIV14 : HSE Divided by 14 selected as RTC clock 4442 * @arg @ref RCC_RTC_HSE_DIV15 : HSE Divided by 15 selected as RTC clock 4443 * @arg @ref RCC_RTC_HSE_DIV16 : HSE Divided by 16 selected as RTC clock 4444 * @arg @ref RCC_RTC_HSE_DIV17 : HSE Divided by 17 selected as RTC clock 4445 * @arg @ref RCC_RTC_HSE_DIV18 : HSE Divided by 18 selected as RTC clock 4446 * @arg @ref RCC_RTC_HSE_DIV19 : HSE Divided by 19 selected as RTC clock 4447 * @arg @ref RCC_RTC_HSE_DIV20 : HSE Divided by 20 selected as RTC clock 4448 * @arg @ref RCC_RTC_HSE_DIV21 : HSE Divided by 21 selected as RTC clock 4449 * @arg @ref RCC_RTC_HSE_DIV22 : HSE Divided by 22 selected as RTC clock 4450 * @arg @ref RCC_RTC_HSE_DIV23 : HSE Divided by 23 selected as RTC clock 4451 * @arg @ref RCC_RTC_HSE_DIV24 : HSE Divided by 24 selected as RTC clock 4452 * @arg @ref RCC_RTC_HSE_DIV25 : HSE Divided by 25 selected as RTC clock 4453 * @arg @ref RCC_RTC_HSE_DIV26 : HSE Divided by 26 selected as RTC clock 4454 * @arg @ref RCC_RTC_HSE_DIV27 : HSE Divided by 27 selected as RTC clock 4455 * @arg @ref RCC_RTC_HSE_DIV28 : HSE Divided by 28 selected as RTC clock 4456 * @arg @ref RCC_RTC_HSE_DIV29 : HSE Divided by 29 selected as RTC clock 4457 * @arg @ref RCC_RTC_HSE_DIV30 : HSE Divided by 30 selected as RTC clock 4458 * @arg @ref RCC_RTC_HSE_DIV31 : HSE Divided by 31 selected as RTC clock 4459 * @arg @ref RCC_RTC_HSE_DIV32 : HSE Divided by 32 selected as RTC clock 4460 * @arg @ref RCC_RTC_HSE_DIV33 : HSE Divided by 33 selected as RTC clock 4461 * @arg @ref RCC_RTC_HSE_DIV34 : HSE Divided by 34 selected as RTC clock 4462 * @arg @ref RCC_RTC_HSE_DIV35 : HSE Divided by 35 selected as RTC clock 4463 * @arg @ref RCC_RTC_HSE_DIV36 : HSE Divided by 36 selected as RTC clock 4464 * @arg @ref RCC_RTC_HSE_DIV37 : HSE Divided by 37 selected as RTC clock 4465 * @arg @ref RCC_RTC_HSE_DIV38 : HSE Divided by 38 selected as RTC clock 4466 * @arg @ref RCC_RTC_HSE_DIV39 : HSE Divided by 39 selected as RTC clock 4467 * @arg @ref RCC_RTC_HSE_DIV40 : HSE Divided by 40 selected as RTC clock 4468 * @arg @ref RCC_RTC_HSE_DIV41 : HSE Divided by 41 selected as RTC clock 4469 * @arg @ref RCC_RTC_HSE_DIV42 : HSE Divided by 42 selected as RTC clock 4470 * @arg @ref RCC_RTC_HSE_DIV43 : HSE Divided by 43 selected as RTC clock 4471 * @arg @ref RCC_RTC_HSE_DIV44 : HSE Divided by 44 selected as RTC clock 4472 * @arg @ref RCC_RTC_HSE_DIV45 : HSE Divided by 45 selected as RTC clock 4473 * @arg @ref RCC_RTC_HSE_DIV46 : HSE Divided by 46 selected as RTC clock 4474 * @arg @ref RCC_RTC_HSE_DIV47 : HSE Divided by 47 selected as RTC clock 4475 * @arg @ref RCC_RTC_HSE_DIV48 : HSE Divided by 48 selected as RTC clock 4476 * @arg @ref RCC_RTC_HSE_DIV49 : HSE Divided by 49 selected as RTC clock 4477 * @arg @ref RCC_RTC_HSE_DIV50 : HSE Divided by 50 selected as RTC clock 4478 * @arg @ref RCC_RTC_HSE_DIV51 : HSE Divided by 51 selected as RTC clock 4479 * @arg @ref RCC_RTC_HSE_DIV52 : HSE Divided by 52 selected as RTC clock 4480 * @arg @ref RCC_RTC_HSE_DIV53 : HSE Divided by 53 selected as RTC clock 4481 * @arg @ref RCC_RTC_HSE_DIV54 : HSE Divided by 54 selected as RTC clock 4482 * @arg @ref RCC_RTC_HSE_DIV55 : HSE Divided by 55 selected as RTC clock 4483 * @arg @ref RCC_RTC_HSE_DIV56 : HSE Divided by 56 selected as RTC clock 4484 * @arg @ref RCC_RTC_HSE_DIV57 : HSE Divided by 57 selected as RTC clock 4485 * @arg @ref RCC_RTC_HSE_DIV58 : HSE Divided by 58 selected as RTC clock 4486 * @arg @ref RCC_RTC_HSE_DIV59 : HSE Divided by 59 selected as RTC clock 4487 * @arg @ref RCC_RTC_HSE_DIV60 : HSE Divided by 60 selected as RTC clock 4488 * @arg @ref RCC_RTC_HSE_DIV61 : HSE Divided by 61 selected as RTC clock 4489 * @arg @ref RCC_RTC_HSE_DIV62 : HSE Divided by 62 selected as RTC clock 4490 * @arg @ref RCC_RTC_HSE_DIV63 : HSE Divided by 63 selected as RTC clock 4491 */ 4492 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_RTCPRE))) 4493 4494 /** @brief Macros to enable or disable the main PLL. 4495 * @note After enabling the main PLL, the application software should wait on 4496 * PLLRDY flag to be set indicating that PLL clock is stable and can 4497 * be used as system clock source. 4498 * @note The main PLL can not be disabled if it is used as system clock source 4499 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 4500 */ 4501 #define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) 4502 #define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) 4503 4504 /** 4505 * @brief Enables or disables each clock output (PLL1P_CLK, PLL1Q_CLK, PLL1R_CLK) 4506 * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, 4507 * (except the ck_pll_p of the System PLL that cannot be stopped if used as System 4508 * Clock. This is mainly used to save Power. 4509 * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted 4510 * This parameter can be one of the following values: 4511 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 250MHz) 4512 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4513 * OCTOSPI, SPI, SAI and Ethernet 4514 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4515 * @retval None 4516 * 4517 */ 4518 #define __HAL_RCC_PLL1_CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4519 4520 #define __HAL_RCC_PLL1_CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4521 4522 /** 4523 * @brief Macro to get the PLL clock output enable status. 4524 * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. 4525 * This parameter can be one of the following values: 4526 * @arg RCC_PLL1_DIVP: This Clock is used to generate the high speed system clock (up to 250MHz) 4527 * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for USB (48 MHz), RNG (<=48 MHz), 4528 * OCTOSPI, SPI, SAI and Ethernet 4529 * @arg RCC_PLL1_DIVR: This Clock is used to generate an accurate clock 4530 * @retval SET / RESET 4531 */ 4532 #define __HAL_RCC_GET_PLL1_CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) 4533 4534 /** 4535 * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO 4536 * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 4537 * @retval None 4538 */ 4539 #define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4540 4541 #define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) 4542 4543 /** 4544 * @brief Macro to configures the main PLL (PLL1) clock source, multiplication and division factors. 4545 * @note This function must be used only when the main PLL1 is disabled. 4546 * 4547 * @param __PLL1SOURCE__: specifies the PLL entry clock source. 4548 * This parameter can be one of the following values: 4549 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4550 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4551 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4552 * @note This clock source (__PLL1SOURCE__) is the clock source for PLL1 (main PLL) and is different 4553 from PLL2 & PLL3 clock sources. 4554 * 4555 * @param __PLL1M__: specifies the division factor for PLL VCO input clock 4556 * This parameter must be a number between 1 and 63. 4557 * @note You have to set the PLL1M parameter correctly to ensure that the VCO input 4558 * frequency ranges from 1 to 16 MHz. 4559 * 4560 * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock 4561 * This parameter must be a number between 4 and 512. 4562 * @note You have to set the PLL1N parameter correctly to ensure that the VCO 4563 * output frequency is between 150 and 420 MHz (when in medium VCO range) or 4564 * between 192 and 836 MHZ (when in wide VCO range) 4565 * 4566 * @param __PLL1P__: specifies the division factor for system clock. 4567 * This parameter must be a number between 2 and 128 (where odd numbers not allowed) 4568 * 4569 * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks 4570 * This parameter must be a number between 1 and 128 4571 * 4572 * @param __PLL1R__: specifies the division factor for peripheral kernel clocks 4573 * This parameter must be a number between 1 and 128 4574 * 4575 * @retval None 4576 */ 4577 #define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ 4578 do{ MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), \ 4579 ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) | ((__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos));\ 4580 WRITE_REG(RCC->PLL1DIVR , ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) | \ 4581 ((((__PLL1P__) - 1U ) << RCC_PLL1DIVR_PLL1P_Pos) & RCC_PLL1DIVR_PLL1P) | \ 4582 ((((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) & RCC_PLL1DIVR_PLL1Q) | \ 4583 ((((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos) & RCC_PLL1DIVR_PLL1R))); \ 4584 } while(0) 4585 4586 /** @brief Macro to configure the PLL1 clock source. 4587 * @note This function must be used only when PLL1 is disabled. 4588 * @param __PLL1SOURCE__: specifies the PLL1 entry clock source. 4589 * This parameter can be one of the following values: 4590 * @arg RCC_PLL1_SOURCE_CSI: CSI oscillator clock selected as PLL1 clock entry 4591 * @arg RCC_PLL1_SOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry 4592 * @arg RCC_PLL1_SOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry 4593 * 4594 */ 4595 #define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLL1SOURCE__) \ 4596 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) 4597 4598 /** @brief Macro to configure the PLL1 input clock division factor M. 4599 * 4600 * @note This function must be used only when the PLL1 is disabled. 4601 * @note PLL1 clock source is common with the main PLL (configured through 4602 * __HAL_RCC_PLL1_CONFIG() macro) 4603 * 4604 * @param __PLL1M__ specifies the division factor for PLL1 clock. 4605 * This parameter must be a number between Min_Data = 1 and Max_Data = 63. 4606 * In order to save power when PLL1 is not used, the value of PLL1M must be set to 0. 4607 * 4608 * @retval None 4609 */ 4610 #define __HAL_RCC_PLL1_DIVM_CONFIG(__PLL1M__) \ 4611 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (__PLL1M__) << RCC_PLL1CFGR_PLL1M_Pos) 4612 4613 /** 4614 * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor 4615 * 4616 * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO 4617 * 4618 * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO 4619 * It should be a value between 0 and 8191 4620 * @note Warning: The software has to set correctly these bits to insure that the VCO 4621 * output frequency is between its valid frequency range, which is: 4622 * 192 to 836 MHz if PLL1VCOSEL = 0 4623 * 150 to 420 MHz if PLL1VCOSEL = 1. 4624 * 4625 * 4626 * @retval None 4627 */ 4628 #define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ 4629 (uint32_t)(__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) 4630 4631 /** @brief Macro to select the PLL1 reference frequency range. 4632 * @param __PLL1VCIRange__: specifies the PLL1 input frequency range 4633 * This parameter can be one of the following values: 4634 * @arg RCC_PLL1_VCIRANGE_0: Range frequency is between 1 and 2 MHz 4635 * @arg RCC_PLL1_VCIRANGE_1: Range frequency is between 2 and 4 MHz 4636 * @arg RCC_PLL1_VCIRANGE_2: Range frequency is between 4 and 8 MHz 4637 * @arg RCC_PLL1_VCIRANGE_3: Range frequency is between 8 and 16 MHz 4638 * @retval None 4639 */ 4640 #define __HAL_RCC_PLL1_VCIRANGE(__PLL1VCIRange__) \ 4641 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) 4642 4643 /** @brief Macro to select the PLL1 reference frequency range. 4644 * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range 4645 * This parameter can be one of the following values: 4646 * @arg RCC_PLL1_VCORANGE_WIDE: Range frequency is between 192 and 836 MHz 4647 * @arg RCC_PLL1_VCORANGE_MEDIUM: Range frequency is between 150 and 420 MHz 4648 * 4649 * 4650 * @retval None 4651 */ 4652 #define __HAL_RCC_PLL1_VCORANGE(__RCC_PLL1VCORange__) \ 4653 MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) 4654 4655 /** @brief Macro to get the oscillator used as PLL1 clock source. 4656 * @retval The oscillator used as PLL1 clock source. The returned value can be one 4657 * of the following: 4658 * - RCC_PLL1_SOURCE_NONE: No oscillator is used as PLL clock source. 4659 * - RCC_PLL1_SOURCE_CSI: CSI oscillator is used as PLL clock source. 4660 * - RCC_PLL1_SOURCE_HSI: HSI oscillator is used as PLL clock source. 4661 * - RCC_PLL1_SOURCE_HSE: HSE oscillator is used as PLL clock source. 4662 */ 4663 #define __HAL_RCC_GET_PLL1_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) 4664 4665 /** 4666 * @brief Macro to configure the system clock source. 4667 * @param __SYSCLKSOURCE__: specifies the system clock source. 4668 * This parameter can be one of the following values: 4669 * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. 4670 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 4671 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 4672 * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1P output is used as system clock source. 4673 * @retval None 4674 */ 4675 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 4676 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) 4677 4678 /** @brief Macro to get the clock source used as system clock. 4679 * @retval The clock source used as system clock. The returned value can be one 4680 * of the following: 4681 * - RCC_SYSCLKSOURCE_STATUS_CSI: CSI used as system clock. 4682 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 4683 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 4684 * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1P used as system clock. 4685 */ 4686 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) 4687 4688 /** 4689 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 4690 * @note As the LSE is in the Backup domain and write access is denied to 4691 * this domain after reset, you have to enable the write access using 4692 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 4693 * (to be done once after reset). 4694 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 4695 * This parameter can be one of the following values: 4696 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 4697 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 4698 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 4699 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 4700 * @retval None 4701 */ 4702 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 4703 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 4704 4705 /** 4706 * @brief Macro to configure the wake up from stop clock. 4707 * @note The configured clock is also used as emergency clock for the Clock Security System on HSE (HSECSS). 4708 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 4709 * This parameter can be one of the following values: 4710 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 4711 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI selected as system clock source 4712 * @retval None 4713 */ 4714 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 4715 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) 4716 4717 #define __HAL_RCC_HSECSS_RECOVCLK_CONFIG __HAL_RCC_WAKEUPSTOP_CLK_CONFIG 4718 4719 /** 4720 * @brief Macro to configure the Kernel wake up from stop clock. 4721 * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop 4722 * This parameter can be one of the following values: 4723 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source 4724 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source 4725 * @retval None 4726 */ 4727 #define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ 4728 MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) 4729 4730 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 4731 * @{ 4732 */ 4733 4734 /** @brief Macro to configure the MCO1 clock. 4735 * @param __MCOCLKSOURCE__ specifies the MCO1 clock source. 4736 * This parameter can be one of the following values: 4737 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source 4738 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source 4739 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source 4740 * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source 4741 * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source 4742 * @param __MCODIV__ specifies the MCO clock prescaler. 4743 * This parameter can be one of the following values: 4744 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock 4745 */ 4746 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4747 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO1SEL | RCC_CFGR1_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 4748 4749 /** @brief Macro to configure the MCO2 clock. 4750 * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. 4751 * This parameter can be one of the following values: 4752 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source 4753 * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source 4754 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source 4755 * @arg RCC_MCO2SOURCE_PLL1PCLK: PLL1P clock selected as MCO2 source 4756 * @arg RCC_MCO2SOURCE_CSI: CSI clock selected as MCO2 source 4757 * @arg RCC_MCO2SOURCE_LSI: LSI clock selected as MCO2 source 4758 * @param __MCODIV__ specifies the MCO clock prescaler. 4759 * This parameter can be one of the following values: 4760 * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock 4761 */ 4762 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 4763 MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCO2SEL | RCC_CFGR1_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); 4764 4765 /** 4766 * @} 4767 */ 4768 4769 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 4770 * @brief macros to manage the specified RCC Flags and interrupts. 4771 * @{ 4772 */ 4773 4774 /** @brief Enable RCC interrupt (Perform access to RCC_CIER[8:0] bits to enable 4775 * the selected interrupts). 4776 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 4777 * This parameter can be any combination of the following values: 4778 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4779 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4780 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4781 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4782 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4783 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4784 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4785 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4786 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4787 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4788 * @retval None 4789 * 4790 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4791 */ 4792 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 4793 4794 /** @brief Disable RCC interrupt (Perform access to RCC_CIER[8:0] bits to disable 4795 * the selected interrupts). 4796 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 4797 * This parameter can be any combination of the following values: 4798 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4799 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4800 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4801 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4802 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4803 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4804 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4805 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4806 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4807 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4808 * @retval None 4809 * 4810 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4811 */ 4812 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 4813 4814 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CICR[10:0] 4815 * bits to clear the selected interrupt pending bits. 4816 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 4817 * This parameter can be any combination of the following values: 4818 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4819 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4820 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4821 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4822 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4823 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4824 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4825 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4826 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4827 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4828 * @retval None 4829 * 4830 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4831 */ 4832 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 4833 4834 /** @brief Check whether the RCC interrupt has occurred or not. 4835 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 4836 * This parameter can be one of the following values: 4837 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 4838 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 4839 * @arg @ref RCC_IT_CSIRDY CSI ready interrupt 4840 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 4841 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 4842 * @arg @ref RCC_IT_PLL1RDY Main PLL ready interrupt 4843 * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt 4844 * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt (*) 4845 * @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt 4846 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 4847 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4848 * 4849 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4850 */ 4851 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 4852 4853 /** @brief Set RMVF bit to clear the reset flags. 4854 * The reset flags are: RCC_FLAG_SFTRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 4855 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 4856 * @retval None 4857 */ 4858 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) 4859 4860 /** @brief Check whether the selected RCC flag is set or not. 4861 * @param __FLAG__: specifies the flag to check. 4862 * This parameter can be one of the following values: 4863 * @arg @ref RCC_FLAG_CSIRDY CSI oscillator clock ready 4864 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 4865 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 4866 * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready 4867 * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready 4868 * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready (*) 4869 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 4870 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 4871 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 4872 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 4873 * @arg @ref RCC_FLAG_HSIDIVF HSI Divider 4874 * @arg @ref RCC_FLAG_BORRST BOR reset 4875 * @arg @ref RCC_FLAG_PINRST Pin reset 4876 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 4877 * @arg @ref RCC_FLAG_SFTRST Software reset 4878 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 4879 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 4880 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 4881 * @retval The new state of __FLAG__ (TRUE or FALSE). 4882 * 4883 * (*) : For stm32h56xxx and stm32h57xxx family lines. 4884 */ 4885 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 4886 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 4887 ((((__FLAG__) >> 5U) == 3U) ? RCC->RSR : RCC->CIFR))) & \ 4888 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) 4889 /** 4890 * @} 4891 */ 4892 4893 /** 4894 * @} 4895 */ 4896 4897 /* Private constants ---------------------------------------------------------*/ 4898 /** @defgroup RCC_Private_Constants RCC Private Constants 4899 * @{ 4900 */ 4901 4902 /** @defgroup RCC_Timeout_Value Timeout Values 4903 * @{ 4904 */ 4905 #define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 4906 #define RCC_HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4907 #define RCC_CSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 4908 #define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ 4909 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 4910 /** 4911 * @} 4912 */ 4913 4914 /* Defines used for Flags */ 4915 #define RCC_CR_REG_INDEX (1U) 4916 #define RCC_BDCR_REG_INDEX (2U) 4917 #define RCC_RSR_REG_INDEX (3U) 4918 4919 #define RCC_FLAG_MASK (0x1FU) 4920 4921 /* Defines Oscillator Masks */ 4922 #define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | \ 4923 RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) 4924 /*!< All Oscillator to configure */ 4925 4926 4927 /** 4928 * @} 4929 */ 4930 4931 /* Private macros ------------------------------------------------------------*/ 4932 /** @addtogroup RCC_Private_Macros 4933 * @{ 4934 */ 4935 4936 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 4937 (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) 4938 4939 4940 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 4941 ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) 4942 4943 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 4944 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_DIGITAL)) 4945 4946 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 4947 4948 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 4949 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8)) 4950 4951 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4952 <= (uint32_t)( RCC_HSICFGR_HSITRIM >> RCC_HSICFGR_HSITRIM_Pos)) 4953 4954 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 4955 4956 #define IS_RCC_CSI(__CSI__) (((__CSI__) == RCC_CSI_OFF) || ((__CSI__) == RCC_CSI_ON)) 4957 4958 #define IS_RCC_CSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 4959 <= (uint32_t)( RCC_CSICFGR_CSITRIM >> RCC_CSICFGR_CSITRIM_Pos)) 4960 4961 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 4962 4963 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ 4964 ((PLL) == RCC_PLL_ON)) 4965 4966 #define IS_RCC_PLL1_SOURCE(SOURCE) (((SOURCE) == RCC_PLL1_SOURCE_CSI) || \ 4967 ((SOURCE) == RCC_PLL1_SOURCE_HSI) || \ 4968 ((SOURCE) == RCC_PLL1_SOURCE_HSE)) 4969 4970 #define IS_RCC_PLL1_DIVM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) 4971 #define IS_RCC_PLL1_MULN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) 4972 #define IS_RCC_PLL1_DIVP_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 128U)) 4973 #define IS_RCC_PLL1_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4974 #define IS_RCC_PLL1_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) 4975 4976 #define IS_RCC_PLL1_CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ 4977 ((VALUE) == RCC_PLL1_DIVQ) || \ 4978 ((VALUE) == RCC_PLL1_DIVR)) 4979 4980 #define IS_RCC_PLL1_VCIRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCIRANGE_0) || \ 4981 ((VALUE) == RCC_PLL1_VCIRANGE_1) || \ 4982 ((VALUE) == RCC_PLL1_VCIRANGE_2) || \ 4983 ((VALUE) == RCC_PLL1_VCIRANGE_3)) 4984 4985 #define IS_RCC_PLL1_VCORGE_VALUE(VALUE) (((VALUE) == RCC_PLL1_VCORANGE_WIDE) || ((VALUE) == RCC_PLL1_VCORANGE_MEDIUM)) 4986 4987 #define IS_RCC_PLL1_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) 4988 4989 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) 4990 4991 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_CSI) || \ 4992 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 4993 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 4994 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 4995 4996 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 4997 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 4998 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 4999 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 5000 ((__HCLK__) == RCC_SYSCLK_DIV512)) 5001 5002 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 5003 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 5004 ((__PCLK__) == RCC_HCLK_DIV16)) 5005 5006 #define IS_RCC_RTCCLKSOURCE(SOURCE) \ 5007 (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ 5008 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ 5009 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ 5010 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ 5011 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ 5012 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ 5013 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ 5014 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ 5015 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ 5016 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ 5017 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ 5018 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ 5019 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ 5020 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ 5021 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ 5022 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ 5023 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ 5024 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ 5025 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ 5026 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ 5027 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ 5028 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ 5029 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ 5030 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ 5031 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ 5032 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ 5033 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ 5034 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ 5035 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ 5036 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ 5037 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ 5038 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63) || \ 5039 ((SOURCE) == RCC_RTCCLKSOURCE_NO_CLK)) 5040 5041 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) 5042 5043 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ 5044 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1Q) || \ 5045 ((SOURCE) == RCC_MCO1SOURCE_HSI48)) 5046 5047 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2P) || \ 5048 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLL1P) || \ 5049 ((SOURCE) == RCC_MCO2SOURCE_CSI) || ((SOURCE) == RCC_MCO2SOURCE_LSI)) 5050 5051 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ 5052 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ 5053 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ 5054 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ 5055 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ 5056 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ 5057 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ 5058 ((DIV) == RCC_MCODIV_15)) 5059 5060 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 5061 ((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 5062 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 5063 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 5064 5065 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_CSI) || \ 5066 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 5067 5068 #define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ 5069 ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) 5070 5071 #if defined(RCC_SECCFGR_HSISEC) 5072 5073 #define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((((ITEM) & RCC_ALL) != 0U) && (((ITEM) & ~RCC_ALL) == 0U)) 5074 5075 #define IS_RCC_SINGLE_ITEM_ATTRIBUTES(ITEM) (((ITEM) == RCC_HSI) || \ 5076 ((ITEM) == RCC_HSE) || \ 5077 ((ITEM) == RCC_CSI) || \ 5078 ((ITEM) == RCC_LSI) || \ 5079 ((ITEM) == RCC_LSE) || \ 5080 ((ITEM) == RCC_SYSCLK) || \ 5081 ((ITEM) == RCC_PRESC) || \ 5082 ((ITEM) == RCC_PLL1) || \ 5083 ((ITEM) == RCC_PLL2) || \ 5084 ((ITEM) == RCC_PLL3) || \ 5085 ((ITEM) == RCC_HSI48) || \ 5086 ((ITEM) == RCC_RMVF) || \ 5087 ((ITEM) == RCC_CKPERSEL)) 5088 #endif /* RCC_SECCFGR_HSISEC */ 5089 5090 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 5091 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ 5092 ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ 5093 ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ 5094 ((ATTRIBUTES) == RCC_NSEC_NPRIV)) 5095 #elif defined(RCC_PRIVCFGR_NSPRIV) 5096 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) 5097 #else 5098 #define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NPRIV) || ((ATTRIBUTES) == RCC_PRIV)) 5099 #endif /* __ARM_FEATURE_CMSE */ 5100 /** 5101 * @} 5102 */ 5103 5104 /* Include RCC HAL Extended module */ 5105 #include "stm32h5xx_hal_rcc_ex.h" 5106 5107 /* Exported functions --------------------------------------------------------*/ 5108 /** @addtogroup RCC_Exported_Functions 5109 * @{ 5110 */ 5111 5112 /** @addtogroup RCC_Exported_Functions_Group1 5113 * @{ 5114 */ 5115 5116 /* Initialization and de-initialization functions ******************************/ 5117 HAL_StatusTypeDef HAL_RCC_DeInit(void); 5118 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pOscInitStruct); 5119 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *pClkInitStruct, uint32_t FLatency); 5120 5121 /** 5122 * @} 5123 */ 5124 5125 /** @addtogroup RCC_Exported_Functions_Group2 5126 * @{ 5127 */ 5128 5129 /* Peripheral Control functions **********************************************/ 5130 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 5131 void HAL_RCC_EnableCSS(void); 5132 uint32_t HAL_RCC_GetSysClockFreq(void); 5133 uint32_t HAL_RCC_GetHCLKFreq(void); 5134 uint32_t HAL_RCC_GetPCLK1Freq(void); 5135 uint32_t HAL_RCC_GetPCLK2Freq(void); 5136 uint32_t HAL_RCC_GetPCLK3Freq(void); 5137 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pOscInitStruct); 5138 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pClkInitStruct, uint32_t *pFLatency); 5139 /* CSS NMI IRQ handler */ 5140 void HAL_RCC_NMI_IRQHandler(void); 5141 /* User Callbacks in non blocking mode (IT mode) */ 5142 void HAL_RCC_CSSCallback(void); 5143 uint32_t HAL_RCC_GetResetSource(void); 5144 5145 /** 5146 * @} 5147 */ 5148 5149 /** @addtogroup RCC_Exported_Functions_Group3 5150 * @{ 5151 */ 5152 5153 /* Attributes management functions ********************************************/ 5154 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 5155 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 5156 5157 /** 5158 * @} 5159 */ 5160 5161 /** 5162 * @} 5163 */ 5164 5165 /** 5166 * @} 5167 */ 5168 5169 /** 5170 * @} 5171 */ 5172 5173 #ifdef __cplusplus 5174 } 5175 #endif 5176 5177 #endif /* __STM32H5xx_HAL_RCC_H */ 5178
