1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32N6xx_HAL_H 22 #define __STM32N6xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32n6xx_hal_conf.h" 30 31 /** @addtogroup STM32N6xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup HAL_Exported_Constants HAL Exported Constants 75 * @{ 76 */ 77 78 /** 79 * @brief STM32N6xx HAL Driver version number 80 */ 81 #define __STM32N6xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 82 #define __STM32N6xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ 83 #define __STM32N6xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ 84 #define __STM32N6xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 85 #define __STM32N6xx_HAL_VERSION ((__STM32N6xx_HAL_VERSION_MAIN << 24U) \ 86 |(__STM32N6xx_HAL_VERSION_SUB1 << 16U) \ 87 |(__STM32N6xx_HAL_VERSION_SUB2 << 8U ) \ 88 |(__STM32N6xx_HAL_VERSION_RC)) 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 95 * @{ 96 */ 97 98 /** @defgroup SYSCFG_BootId Boot Id 99 * @{ 100 */ 101 #define SYSCFG_BOOT_0 SYSCFG_BOOTCR_BOOT0_PD /*!< Boot 0 selection */ 102 #define SYSCFG_BOOT_1 SYSCFG_BOOTCR_BOOT1_PD /*!< Boot 1 selection */ 103 /** 104 * @} 105 */ 106 107 /** @defgroup SYSCFG_SDMMCId SDMMC Id 108 * @{ 109 */ 110 #define SYSCFG_SDMMC1 SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE /*!< SDMMC 1 selection */ 111 #define SYSCFG_SDMMC2 SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE /*!< SDMMC 2 selection */ 112 #define SYSCFG_SDMMC_ALL (SYSCFG_SDMMC1 | SYSCFG_SDMMC2) /*!< SDMMC 1 & 2 selection */ 113 /** 114 * @} 115 */ 116 117 /** @defgroup SYSCFG_USBId USB Id 118 * @{ 119 */ 120 #define SYSCFG_USB1 SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE /*!< USB 1 selection */ 121 #define SYSCFG_USB2 SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE /*!< USB 2 selection */ 122 #define SYSCFG_USB_ALL (SYSCFG_USB1 | SYSCFG_USB2) /*!< USB 1 & 2 selection */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup SYSCFG_XPUId XPU Id 128 * @{ 129 */ 130 #if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) 131 #define SYSCFG_NPU_NIC SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE /*!< NPU_NIC clock gating disable selection */ 132 #endif /* defined(SYSCFG_ICNCGCR_NPU_NOCSYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_CG_DISABLE) */ 133 #define SYSCFG_CPU_NIC SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE /*!< CPU_NIC clock gating disable selection */ 134 #define SYSCFG_CPU_NOC SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE /*!< CPU_NOC clock gating disable selection */ 135 #if defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) 136 #define SYSCFG_CPU_ALL (SYSCFG_NPU_NIC | SYSCFG_CPU_NIC | SYSCFG_CPU_NOC) 137 #else 138 #define SYSCFG_CPU_ALL (SYSCFG_CPU_NIC | SYSCFG_CPU_NOC) 139 #endif /* defined(SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE) */ 140 /** 141 * @} 142 */ 143 144 /** @defgroup SYSCFG_Compensation_Cell_Selection Compensation Cell Selection 145 * @{ 146 */ 147 #define SYSCFG_IO_VDDIO2_CELL 0U /*!< I/O Compensation cell for VDDIO2 */ 148 #define SYSCFG_IO_VDDIO3_CELL 1U /*!< I/O Compensation cell for VDDIO3 */ 149 #define SYSCFG_IO_VDDIO4_CELL 2U /*!< I/O Compensation cell for VDDIO4 */ 150 #define SYSCFG_IO_VDDIO5_CELL 3U /*!< I/O Compensation cell for VDDIO5 */ 151 /** 152 * @} 153 */ 154 155 /** @defgroup SYSCFG_IO_Compensation_Code_Config IO Compensation Code config 156 * @{ 157 */ 158 #define SYSCFG_IO_CELL_CODE 0UL /*!< Code from the cell */ 159 #define SYSCFG_IO_REGISTER_CODE 1UL /*!< Code from the values in the cell code register */ 160 /** 161 * @} 162 */ 163 164 /** @defgroup SYSCFG_DELAY_Feedback_Clock Delay on feedback clock 165 * @{ 166 */ 167 #define SYSCFG_DELAY_FEEDBACK_NONE 0U /*!< No delay on the feedback clock */ 168 #define SYSCFG_DELAY_FEEDBACK_HALF_CYCLE SYSCFG_FMC_RETIMECR_SDFBCLK_180 /*!< Half a cycle delay on the feedback clock */ 169 /** 170 * @} 171 */ 172 173 174 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 175 * @{ 176 */ 177 #define SYSCFG_IT_FPU_IOC SYSCFG_CM55CR_FPU_IT_EN_0 /*!< Floating Point Unit Invalid operation Interrupt */ 178 #define SYSCFG_IT_FPU_DZC SYSCFG_CM55CR_FPU_IT_EN_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 179 #define SYSCFG_IT_FPU_UFC SYSCFG_CM55CR_FPU_IT_EN_2 /*!< Floating Point Unit Underflow Interrupt */ 180 #define SYSCFG_IT_FPU_OFC SYSCFG_CM55CR_FPU_IT_EN_3 /*!< Floating Point Unit Overflow Interrupt */ 181 #define SYSCFG_IT_FPU_IDC SYSCFG_CM55CR_FPU_IT_EN_4 /*!< Floating Point Unit Input denormal Interrupt */ 182 #define SYSCFG_IT_FPU_IXC SYSCFG_CM55CR_FPU_IT_EN_5 /*!< Floating Point Unit Inexact Interrupt */ 183 #define SYSCFG_IT_FPU_ALL (SYSCFG_CM55CR_FPU_IT_EN_0 |\ 184 SYSCFG_CM55CR_FPU_IT_EN_1 |\ 185 SYSCFG_CM55CR_FPU_IT_EN_2 |\ 186 SYSCFG_CM55CR_FPU_IT_EN_3 |\ 187 SYSCFG_CM55CR_FPU_IT_EN_4 |\ 188 SYSCFG_CM55CR_FPU_IT_EN_5) 189 190 /** 191 * @} 192 */ 193 194 195 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 196 * @brief SYSCFG items to set lock on 197 * @{ 198 */ 199 #define SYSCFG_MPU_NSEC SYSCFG_CM55CR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 200 #define SYSCFG_VTOR_NSEC SYSCFG_CM55CR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 201 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 202 #define SYSCFG_DCAIC (SYSCFG_CM55CR_LOCKDCAIC) /*!< Disable access to the instruction cache direct cache access registers DCAICLR 203 and DCAICRR */ 204 #define SYSCFG_SAU (SYSCFG_CM55CR_LOCKSAU) /*!< SAU lock (privileged secure code only) */ 205 #define SYSCFG_MPU_SEC (SYSCFG_CM55CR_LOCKSMPU) /*!< Secure MPU lock (privileged secure code only) */ 206 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CM55CR_LOCKSVTAIRCR) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 207 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC | SYSCFG_DCAIC | SYSCFG_SAU | SYSCFG_MPU_SEC | SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 208 #else 209 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC | SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 210 #endif /* __ARM_FEATURE_CMSE */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup SYSCFG_DTCM_size SYSCFG DTCM size 216 * @brief DTCM size to be configured 217 * @{ 218 */ 219 #define SYSCFG_DTCM_128K (SYSCFG_CM55TCMCR_CFGDTCMSZ_3) /*!< DTCM memory size is 128K */ 220 #define SYSCFG_DTCM_256K (SYSCFG_CM55TCMCR_CFGDTCMSZ_0 | SYSCFG_CM55TCMCR_CFGDTCMSZ_3) /*!< DTCM memory size is 256K */ 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup SYSCFG_ITCM_size SYSCFG ITCM size 227 * @brief ITCM size to be configured 228 * @{ 229 */ 230 #define SYSCFG_ITCM_64K (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_1 | SYSCFG_CM55TCMCR_CFGITCMSZ_2) /*!< ITCM memory size is 64K */ 231 #define SYSCFG_ITCM_128K (SYSCFG_CM55TCMCR_CFGITCMSZ_3) /*!< ITCM memory size is 128K */ 232 #define SYSCFG_ITCM_256K (SYSCFG_CM55TCMCR_CFGITCMSZ_0 | SYSCFG_CM55TCMCR_CFGITCMSZ_3) /*!< ITCM memory size is 256K */ 233 234 /** 235 * @} 236 */ 237 238 /** @defgroup SYSCFG_WRITE_access WRITE access selection 239 * @brief WRITE assess to be configured 240 * @{ 241 */ 242 #define SYSCFG_LOCK_WR_TCM (SYSCFG_CM55TCMCR_LOCKTCM) /*!< ITCM memory size is 64K */ 243 #define SYSCFG_LOCK_WR_ITGU (SYSCFG_CM55TCMCR_LOCKITGU) /*!< Disable writes to registers associated with the ITCM interface security/gating. */ 244 #define SYSCFG_LOCK_WR_DTGU (SYSCFG_CM55TCMCR_LOCKDTGU) /*!< Disable writes to registers associated with the DTCM interface security/gating */ 245 #define SYSCFG_LOCK_WR_ALL (SYSCFG_CM55TCMCR_LOCKTCM | SYSCFG_CM55TCMCR_LOCKITGU | SYSCFG_CM55TCMCR_LOCKDTGU) /*!< All writes accesses */ 246 /** 247 * @} 248 */ 249 /** @defgroup SYSCFG_CACHE_biasing Cache biasing level adjust input selection 250 * @brief CACHE biasing level adjust input selection 251 * @{ 252 */ 253 #define SYSCFG_CACHE_BIAS_VNOM SYSCFG_CM55RWMCR_BC1_CACHE 254 #define SYSCFG_CACHE_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_CACHE 255 /** 256 * @} 257 */ 258 259 /** @defgroup SYSCFG_TCM_biasing biasing level selection 260 * @brief TCM biasing level adjust input selection 261 * @{ 262 */ 263 #define SYSCFG_TCM_BIAS_VNOM SYSCFG_CM55RWMCR_BC1_TCM 264 #define SYSCFG_TCM_BIAS_VNOM_10_PERCENT SYSCFG_CM55RWMCR_BC2_TCM 265 /** 266 * @} 267 */ 268 269 /** @defgroup SBS_Timer_Break_Inputs Timer Break Inputs 270 * @{ 271 */ 272 #define SYSCFG_CBR_BREAK_LOCK_CORE SYSCFG_CBR_CM55L /*!< Cortex-CM55 lockup break lock */ 273 #define SYSCFG_CBR_BREAK_LOCK_PVD SYSCFG_CBR_PVDL_LOCK /*!< PVD lock */ 274 #define SYSCFG_CBR_BREAK_LOCK_BKPRAM SYSCFG_CBR_BKPRAML /*!< Backup SRAM ECC error break lock */ 275 #define SYSCFG_CBR_BREAK_LOCK_CM55_CACHE SYSCFG_CBR_CM55CACHEL /*!< CM55 cache double ECC error lock */ 276 #define SYSCFG_CBR_BREAK_LOCK_CM55_TCM SYSCFG_CBR_CM55TCML /*!< CM55 TCM double ECC error lock */ 277 #define SYSCFG_CBR_BREAK_LOCK_ALL (SYSCFG_CBR_CM55L |\ 278 SYSCFG_CBR_PVDL_LOCK |\ 279 SYSCFG_CBR_BKPRAML |\ 280 SYSCFG_CBR_CM55CACHEL |\ 281 SYSCFG_CBR_CM55TCML) 282 283 /** 284 * @} 285 */ 286 287 /** 288 * @} 289 */ 290 291 292 293 /* Exported macros -----------------------------------------------------------*/ 294 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 295 * @{ 296 */ 297 298 /** @brief Freeze/Unfreeze Peripherals in Debug mode 299 */ 300 #if defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP) 301 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP) 302 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_STOP) 303 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM2_STOP) */ 304 305 #if defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP) 306 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP) 307 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_STOP) 308 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM3_STOP) */ 309 310 #if defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP) 311 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP) 312 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_STOP) 313 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM4_STOP) */ 314 315 #if defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP) 316 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP) 317 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_STOP) 318 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM5_STOP) */ 319 320 #if defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP) 321 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP) 322 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_STOP) 323 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM6_STOP) */ 324 325 #if defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP) 326 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP) 327 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_STOP) 328 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM7_STOP) */ 329 330 #if defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP) 331 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP) 332 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10_STOP) 333 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM10_STOP) */ 334 335 #if defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP) 336 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP) 337 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11_STOP) 338 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM11_STOP) */ 339 340 #if defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP) 341 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP) 342 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12_STOP) 343 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM12_STOP) */ 344 345 #if defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP) 346 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP) 347 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13_STOP) 348 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM13_STOP) */ 349 350 #if defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP) 351 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP) 352 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM14_STOP) 353 #endif /* defined(DBGMCU_APB1LFZ1_DBG_TIM14_STOP) */ 354 355 #if defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) 356 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) 357 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) 358 #endif /* defined(DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP) */ 359 360 #if defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) 361 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) 362 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) 363 #endif /* defined(DBGMCU_APB1LFZ1_DBG_WWDG1_STOP) */ 364 365 #if defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP) 366 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP) 367 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C1_STOP) 368 #endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C1_STOP) */ 369 370 #if defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP) 371 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP) 372 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C2_STOP) 373 #endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C2_STOP) */ 374 375 #if defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP) 376 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP) 377 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I2C3_STOP) 378 #endif /* defined(DBGMCU_APB1LFZ1_DBG_I2C3_STOP) */ 379 380 #if defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP) 381 #define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP) 382 #define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C1_STOP) 383 #endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C1_STOP) */ 384 385 #if defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP) 386 #define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP) 387 #define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_I3C2_STOP) 388 #endif /* defined(DBGMCU_APB1LFZ1_DBG_I3C2_STOP) */ 389 390 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) 391 #define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) 392 #define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1HFZ1, DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) 393 #endif /* defined(DBGMCU_APB1HFZ1_DBG_FDCAN_STOP) */ 394 395 #if defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP) 396 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP) 397 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM1_STOP) 398 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM1_STOP) */ 399 400 #if defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP) 401 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP) 402 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM8_STOP) 403 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM8_STOP) */ 404 405 #if defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP) 406 #define __HAL_DBGMCU_FREEZE_TIM18() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP) 407 #define __HAL_DBGMCU_UNFREEZE_TIM18() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM18_STOP) 408 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM18_STOP) */ 409 410 #if defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP) 411 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP) 412 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM15_STOP) 413 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM15_STOP) */ 414 415 #if defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP) 416 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP) 417 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM16_STOP) 418 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM16_STOP) */ 419 420 #if defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP) 421 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP) 422 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM17_STOP) 423 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM17_STOP) */ 424 425 #if defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP) 426 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP) 427 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2FZ1_DBG_TIM9_STOP) 428 #endif /* defined(DBGMCU_APB2FZ1_DBG_TIM9_STOP) */ 429 430 #if defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP) 431 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP) 432 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_I2C4_STOP) 433 #endif /* defined(DBGMCU_APB4FZ1_DBG_I2C4_STOP) */ 434 435 #if defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) 436 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) 437 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) 438 #endif /* defined(DBGMCU_APB4FZ1_DBG_LPTIM2_STOP) */ 439 440 #if defined(DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) 441 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) 442 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM3_STOP) 443 #endif /* DBGMCU_APB4FZ1_DBG_LPTIM3_STOP */ 444 445 #if defined(DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) 446 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) 447 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM4_STOP) 448 #endif /* DBGMCU_APB4FZ1_DBG_LPTIM4_STOP */ 449 450 #if defined(DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) 451 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) 452 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_LPTIM5_STOP) 453 #endif /* DBGMCU_APB4FZ1_DBG_LPTIM5_STOP */ 454 455 #if defined(DBGMCU_APB4FZ1_DBG_RTC_STOP) 456 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP) 457 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_RTC_STOP) 458 #endif /* DBGMCU_APB4FZ1_DBG_RTC_STOP */ 459 460 #if defined(DBGMCU_APB4FZ1_DBG_IWDG_STOP) 461 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP) 462 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4FZ1_DBG_IWDG_STOP) 463 #endif /* DBGMCU_APB4FZ1_DBG_IWDG_STOP */ 464 465 #if defined(DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) 466 #define __HAL_DBGMCU_FREEZE_GFXTIM() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) 467 #define __HAL_DBGMCU_UNFREEZE_GFXTIM() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5FZ1_DBG_GFXTIM_STOP) 468 #endif /* DBGMCU_APB5FZ1_DBG_GFXTIM_STOP */ 469 470 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) 471 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH0() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) 472 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH0() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP) 473 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP */ 474 475 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) 476 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH1() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) 477 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH1() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP) 478 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP */ 479 480 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) 481 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH2() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) 482 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH2() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP) 483 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP */ 484 485 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) 486 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH3() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) 487 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH3() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP) 488 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP */ 489 490 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) 491 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH4() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) 492 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH4() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP) 493 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP */ 494 495 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) 496 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH5() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) 497 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH5() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP) 498 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP */ 499 500 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) 501 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH6() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) 502 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH6() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP) 503 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP */ 504 505 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) 506 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH7() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) 507 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH7() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP) 508 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP */ 509 510 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) 511 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH8() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) 512 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH8() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP) 513 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP */ 514 515 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) 516 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH9() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) 517 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH9() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP) 518 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP */ 519 520 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) 521 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH10() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) 522 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH10() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP) 523 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP */ 524 525 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) 526 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH11() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) 527 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH11() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP) 528 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP */ 529 530 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) 531 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH12() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) 532 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH12() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP) 533 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP */ 534 535 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) 536 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH13() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) 537 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH13() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP) 538 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP */ 539 540 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) 541 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH14() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) 542 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH14() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP) 543 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP */ 544 545 #if defined(DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) 546 #define __HAL_DBGMCU_FREEZE_GPDMA1_CH15() SET_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) 547 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_CH15() CLEAR_BIT(DBGMCU->AHB1FZ1, DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP) 548 #endif /* DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP */ 549 550 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) 551 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH0() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) 552 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH0() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP) 553 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP */ 554 555 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) 556 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH1() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) 557 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH1() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP) 558 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP */ 559 560 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) 561 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH2() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) 562 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH2() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP) 563 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP */ 564 565 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) 566 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH3() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) 567 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH3() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP) 568 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP */ 569 570 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) 571 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH4() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) 572 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH4() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP) 573 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP */ 574 575 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) 576 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH5() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) 577 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH5() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP) 578 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP */ 579 580 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) 581 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH6() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) 582 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH6() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP) 583 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP */ 584 585 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) 586 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH7() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) 587 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH7() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP) 588 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP */ 589 590 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) 591 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH8() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) 592 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH8() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP) 593 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP */ 594 595 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) 596 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH9() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) 597 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH9() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP) 598 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP */ 599 600 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) 601 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH10() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) 602 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH10() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP) 603 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP */ 604 605 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) 606 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH11() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) 607 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH11() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP) 608 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP */ 609 610 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) 611 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH12() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) 612 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH12() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP) 613 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP */ 614 615 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) 616 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH13() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) 617 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH13() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP) 618 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP */ 619 620 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) 621 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH14() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) 622 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH14() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP) 623 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP */ 624 625 #if defined(DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) 626 #define __HAL_DBGMCU_FREEZE_HPDMA1_CH15() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) 627 #define __HAL_DBGMCU_UNFREEZE_HPDMA1_CH15() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP) 628 #endif /* DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP */ 629 630 #if defined(DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) 631 #define __HAL_DBGMCU_FREEZE_NPU() SET_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) 632 #define __HAL_DBGMCU_UNFREEZE_NPU() CLEAR_BIT(DBGMCU->AHB5FZ1, DBGMCU_AHB5FZ1_NPU_DBG_FREEZE) 633 #endif /* DBGMCU_AHB5FZ1_NPU_DBG_FREEZE */ 634 635 636 /** 637 * @} 638 */ 639 640 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 641 * @{ 642 */ 643 644 /** @brief Floating Point Unit interrupt enable/disable macros 645 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 646 */ 647 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 648 SET_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\ 649 }while(0) 650 651 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 652 CLEAR_BIT(SYSCFG->CM55CR, (__INTERRUPT__));\ 653 }while(0) 654 655 /* Private macros ------------------------------------------------------------*/ 656 657 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 658 * @{ 659 */ 660 #define IS_SYSCFG_BOOT_ID(__BOOTID__) ((((__BOOTID__) & SYSCFG_BOOT_0) == SYSCFG_BOOT_0) || \ 661 (((__BOOTID__) & SYSCFG_BOOT_1) == SYSCFG_BOOT_1)) 662 663 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) (((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 664 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 665 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 666 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 667 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 668 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) && \ 669 (((__INTERRUPT__) & ~(SYSCFG_IT_FPU_ALL)) == 0U)) 670 671 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 672 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 673 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 674 (((__ITEM__) & SYSCFG_DCAIC) == SYSCFG_DCAIC) || \ 675 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 676 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 677 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC)) && \ 678 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 679 #else 680 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) (((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 681 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC)) && \ 682 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 683 #endif /* __ARM_FEATURE_CMSE */ 684 685 #define IS_SYSCFG_DTCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_128K) || \ 686 (((__SIZE__) & SYSCFG_CM55TCMCR_CFGDTCMSZ) == SYSCFG_DTCM_256K)) 687 688 #define IS_SYSCFG_ITCM_SIZE(__SIZE__) ((((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_64K) || \ 689 (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_128K) || \ 690 (((__SIZE__) & SYSCFG_CM55TCMCR_CFGITCMSZ) == SYSCFG_ITCM_256K)) 691 692 #define IS_SYSCFG_LOCK_WRACCESS(__WRACCESS__) (((((__WRACCESS__) & SYSCFG_LOCK_WR_TCM) == SYSCFG_LOCK_WR_TCM) || \ 693 (((__WRACCESS__) & SYSCFG_LOCK_WR_ITGU) == SYSCFG_LOCK_WR_ITGU) || \ 694 (((__WRACCESS__) & SYSCFG_LOCK_WR_DTGU) == SYSCFG_LOCK_WR_DTGU)) && \ 695 (((__WRACCESS__) & ~(SYSCFG_LOCK_WR_ALL)) == 0U)) 696 697 #define IS_TCM_MARGIN_INPUT(__MARGIN__) ((__MARGIN__) < 16U) 698 699 #define IS_SYSCFG_CACHE_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM) || \ 700 (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_CACHE | SYSCFG_CM55RWMCR_BC2_CACHE)) == SYSCFG_CACHE_BIAS_VNOM_10_PERCENT)) 701 702 #define IS_SYSCFG_TCM_BIASING_LEVEL(__LEVEL__) ((((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM) || \ 703 (((__LEVEL__) & (SYSCFG_CM55RWMCR_BC1_TCM | SYSCFG_CM55RWMCR_BC2_TCM)) == SYSCFG_TCM_BIAS_VNOM_10_PERCENT)) 704 705 #define IS_VTOR_ADDRESS(__ADDRESS__) (((__ADDRESS__) & 0x7FU) == 0U) 706 707 #define IS_SYSCFG_QOS_CPU(__QOS__) ((__QOS__) < 16U) 708 709 #define IS_SYSCFG_SDMMC(__SDMMC__) (((((__SDMMC__) & SYSCFG_SDMMC1) == SYSCFG_SDMMC1) || \ 710 (((__SDMMC__) & SYSCFG_SDMMC2) == SYSCFG_SDMMC2)) && \ 711 (((__SDMMC__) & ~(SYSCFG_SDMMC_ALL)) == 0U)) 712 713 #define IS_SYSCFG_USB(__USB__) (((((__USB__) & SYSCFG_USB1) == SYSCFG_USB1) || \ 714 (((__USB__) & SYSCFG_USB2) == SYSCFG_USB2)) && \ 715 (((__USB__) & ~(SYSCFG_USB_ALL)) == 0U)) 716 717 #if defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE) 718 #define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_NPU_NOC) == SYSCFG_NPU_NOC) || \ 719 (((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) || \ 720 (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \ 721 (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U)) 722 #else 723 #define IS_SYSCFG_CPU_CLK_GATING(__CPU__) (((((__CPU__) & SYSCFG_CPU_NIC) == SYSCFG_CPU_NIC) || \ 724 (((__CPU__) & SYSCFG_CPU_NOC) == SYSCFG_CPU_NOC)) && \ 725 (((__CPU__) & ~(SYSCFG_CPU_ALL)) == 0U)) 726 #endif /* defined(SYSCFG_ICNCGCR_NPU_NOC_CG_DISABLE) */ 727 728 #define IS_SYSCFG_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) 729 #define IS_SYSCFG_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U)) 730 731 #define IS_SYSCFG_COMPENSATION_CELL(__VALUE__) (((__VALUE__) == SYSCFG_IO_VDDIO2_CELL) || \ 732 ((__VALUE__) == SYSCFG_IO_VDDIO3_CELL) || \ 733 ((__VALUE__) == SYSCFG_IO_VDDIO4_CELL) || \ 734 ((__VALUE__) == SYSCFG_IO_VDDIO5_CELL)) 735 736 #define IS_SYSCFG_IO_COMPENSATION_CODE(__CELL__) (((__CELL__) == SYSCFG_IO_CELL_CODE) || \ 737 ((__CELL__) == SYSCFG_IO_REGISTER_CODE)) 738 739 #define IS_SYSCFG_CBR_BREAK_INPUT(__VALUE__) \ 740 ((((__VALUE__) & SYSCFG_CBR_BREAK_LOCK_ALL) != 0U) && \ 741 (((__VALUE__) & ~SYSCFG_CBR_BREAK_LOCK_ALL) == 0U)) 742 743 #define IS_SYSCFG_DMA_CID_SEC(__CID__) (((__CID__) < 8U)) 744 745 #define IS_SYSCFG_DMA_CID_NON_SEC(__CID__) (((__CID__) < 8U)) 746 747 #define IS_SYSCFG_DMA_DELAY_FEEDBACK_CLOCK(__DELAY__) (((__DELAY__) == SYSCFG_DELAY_FEEDBACK_NONE) || \ 748 ((__DELAY__) == SYSCFG_DELAY_FEEDBACK_HALF_CYCLE)) 749 750 /** 751 * @} 752 */ 753 754 755 /** @defgroup HAL_Private_Macros HAL Private Macros 756 * @{ 757 */ 758 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 759 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 760 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 761 /** 762 * @} 763 */ 764 765 /* Exported functions --------------------------------------------------------*/ 766 767 /** @addtogroup HAL_Exported_Functions 768 * @{ 769 */ 770 771 /** @addtogroup HAL_Exported_Functions_Group1 772 * @{ 773 */ 774 775 /* Initialization and de-initialization functions ******************************/ 776 HAL_StatusTypeDef HAL_Init(void); 777 HAL_StatusTypeDef HAL_DeInit(void); 778 void HAL_MspInit(void); 779 void HAL_MspDeInit(void); 780 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 781 782 /** 783 * @} 784 */ 785 786 /** @addtogroup HAL_Exported_Functions_Group2 787 * @{ 788 */ 789 790 /* Peripheral Control functions ************************************************/ 791 void HAL_IncTick(void); 792 void HAL_Delay(uint32_t Delay); 793 uint32_t HAL_GetTick(void); 794 uint32_t HAL_GetTickPrio(void); 795 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 796 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 797 void HAL_SuspendTick(void); 798 void HAL_ResumeTick(void); 799 uint32_t HAL_GetHalVersion(void); 800 uint32_t HAL_GetREVID(void); 801 uint32_t HAL_GetDEVID(void); 802 uint32_t HAL_GetUIDw0(void); 803 uint32_t HAL_GetUIDw1(void); 804 uint32_t HAL_GetUIDw2(void); 805 806 /** 807 * @} 808 */ 809 810 /** @addtogroup HAL_Exported_Functions_Group3 811 * @{ 812 */ 813 814 /* DBGMCU Peripheral Control functions *****************************************/ 815 void HAL_DBGMCU_EnableDBGSleepMode(void); 816 void HAL_DBGMCU_DisableDBGSleepMode(void); 817 void HAL_DBGMCU_EnableDBGStopMode(void); 818 void HAL_DBGMCU_DisableDBGStopMode(void); 819 void HAL_DBGMCU_EnableDBGStandbyMode(void); 820 void HAL_DBGMCU_DisableDBGStandbyMode(void); 821 822 /** @addtogroup HAL_Exported_Functions_Group4 823 * @{ 824 */ 825 826 /* SYSCFG Peripheral Control functions *****************************************/ 827 void HAL_SYSCFG_EnablePullDown(uint32_t BootId); 828 void HAL_SYSCFG_DisablePullDown(uint32_t BootId); 829 830 831 void HAL_SYSCFG_Lock(uint32_t Item); 832 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 833 834 void HAL_SYSCFG_SetTCMSize(uint32_t DtcmSize, uint32_t ItcmSize); 835 HAL_StatusTypeDef HAL_SYSCFG_GetTCMSize(uint32_t *pDtcmSize, uint32_t *pItcmSize); 836 837 void HAL_SYSCFG_LockWriteAccess(uint32_t Item); 838 HAL_StatusTypeDef HAL_SYSCFG_GetLockWriteAccess(uint32_t *pItem); 839 840 void HAL_SYSCFG_EnableITCMWaiteState(void); 841 void HAL_SYSCFG_DisableITCMWaiteState(void); 842 void HAL_SYSCFG_EnableDTCMWaiteState(void); 843 void HAL_SYSCFG_DisableDTCMWaiteState(void); 844 845 void HAL_SYSCFG_EnableTCMExternalMargin(void); 846 void HAL_SYSCFG_DisableTCMExternalMargin(void); 847 848 void HAL_SYSCFG_SetTCMRWMarginInput(uint32_t TcmRwMarginInput); 849 HAL_StatusTypeDef HAL_SYSCFG_GetTCMRWMarginInput(uint32_t *pTcmRwMarginInput); 850 851 void HAL_SYSCFG_SetTCMBiasingLevel(uint32_t Level); 852 HAL_StatusTypeDef HAL_SYSCFG_GetTCMBiasingLevel(uint32_t *pLevel); 853 854 void HAL_SYSCFG_EnableCacheExternalMargin(void); 855 void HAL_SYSCFG_DisableCacheExternalMargin(void); 856 857 void HAL_SYSCFG_SetCacheRWMarginInput(uint32_t CacheRWMarginInput); 858 HAL_StatusTypeDef HAL_SYSCFG_GetCacheRWMarginInput(uint32_t *pCacheRWMarginInput); 859 860 void HAL_SYSCFG_SetCacheBiasingLevel(uint32_t Level); 861 HAL_StatusTypeDef HAL_SYSCFG_GetCacheBiasingLevel(uint32_t *pLevel); 862 863 864 void HAL_SYSCFG_SetSVTORAddress(uint32_t Address); 865 HAL_StatusTypeDef HAL_SYSCFG_GetSVTORAddress(uint32_t *pAddress); 866 867 void HAL_SYSCFG_SetNSVTORAddress(uint32_t Address); 868 HAL_StatusTypeDef HAL_SYSCFG_GetNSVTORAddress(uint32_t *pAddress); 869 870 871 void HAL_SYSCFG_EnablePowerOnReset(void); 872 void HAL_SYSCFG_DisablePowerOnReset(void); 873 874 void HAL_SYSCFG_EnableLockupWarmResetonRCC(void); 875 void HAL_SYSCFG_DisableLockupWarmResetonRCC(void); 876 877 void HAL_SYSCFG_EnableLockupGenerateNMI(void); 878 void HAL_SYSCFG_DisableLockupGenerateNMI(void); 879 880 HAL_StatusTypeDef HAL_SYSCFG_ReEnableWritePostingErrorCapture(void); 881 882 #if defined(VENC) 883 void HAL_SYSCFG_EnableVENCRAMReserved(void); 884 void HAL_SYSCFG_DisableVENCRAMReserved(void); 885 #endif /* VENC */ 886 887 void HAL_SYSCFG_EnableCRYPPotentialTamper(void); 888 void HAL_SYSCFG_DisableCRYPPotentialTamper(void); 889 890 891 void HAL_SYSCFG_SetWriteQosNP1(uint32_t QosValue); 892 HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP1(uint32_t *pQosValue); 893 void HAL_SYSCFG_SetReadQosNP1(uint32_t QosValue); 894 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP1(uint32_t *pQosValue); 895 896 void HAL_SYSCFG_SetWriteQosNP2(uint32_t QosValue); 897 HAL_StatusTypeDef HAL_SYSCFG_GetWriteQosNP2(uint32_t *pQosValue); 898 void HAL_SYSCFG_SetReadQosNP2(uint32_t QosValue); 899 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosNP2(uint32_t *pQosValue); 900 901 void HAL_SYSCFG_SetWriteQosCPUSS(uint32_t QosValue); 902 HAL_StatusTypeDef HAL_SYSCFG_GetwriteQosCPUSS(uint32_t *pQosValue); 903 void HAL_SYSCFG_SetReadQosCPUSS(uint32_t QosValue); 904 HAL_StatusTypeDef HAL_SYSCFG_GetReadQosCPUSS(uint32_t *pQosValue); 905 906 907 void HAL_SYSCFG_EnableSDMMCEarlyWRRESP(uint32_t Sdmmc); 908 void HAL_SYSCFG_DisableSDMMCEarlyWRRSP(uint32_t Sdmmc); 909 910 void HAL_SYSCFG_EnableUSBEarlyEarlyWRRESP(uint32_t Usb); 911 void HAL_SYSCFG_DisableUSBEarlyEarlyWRRESP(uint32_t Usb); 912 913 914 void HAL_SYSCFG_EnablexPUClockGating(uint32_t Xpu); 915 void HAL_SYSCFG_DisablexPUClockGating(uint32_t Xpu); 916 917 918 919 920 void HAL_SYSCFG_EnableVDDIO2CompensationCell(void); 921 void HAL_SYSCFG_DisableVDDIO2CompensationCell(void); 922 923 void HAL_SYSCFG_EnableVDDIO3CompensationCell(void); 924 void HAL_SYSCFG_DisableVDDIO3CompensationCell(void); 925 926 void HAL_SYSCFG_EnableVDDIO4CompensationCell(void); 927 void HAL_SYSCFG_DisableVDDIO4CompensationCell(void); 928 929 void HAL_SYSCFG_EnableVDDIO5CompensationCell(void); 930 void HAL_SYSCFG_DisableVDDIO5CompensationCell(void); 931 932 933 HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDIOCompensationCell(uint32_t Selection, uint32_t Code, 934 uint32_t NmosValue, uint32_t PmosValue); 935 936 HAL_StatusTypeDef HAL_SYSCFG_GetVDDIOCompensationCell(uint32_t Selection, const uint32_t *pCode, uint32_t *pNmosValue, 937 uint32_t *pPmosValue); 938 939 940 uint32_t HAL_SYSCFG_GetCompVDDIO2CellReadyStatus(void); 941 uint32_t HAL_SYSCFG_GetCompVDDIO3CellReadyStatus(void); 942 uint32_t HAL_SYSCFG_GetCompVDDIO4CellReadyStatus(void); 943 uint32_t HAL_SYSCFG_GetCompVDDIO5CellReadyStatus(void); 944 945 HAL_StatusTypeDef HAL_SYSCFG_ConfigVDDCompensationCell(uint32_t Code, uint32_t NmosValue, uint32_t PmosValue); 946 947 void HAL_SYSCFG_EnableVDDCompensationCell(void); 948 void HAL_SYSCFG_DisableVDDCompensationCell(void); 949 950 HAL_StatusTypeDef HAL_SYSCFG_GetVDDCompensationCell(uint32_t Code, uint32_t *pNmosValue, 951 uint32_t *pPmosValue); 952 uint32_t HAL_SYSCFG_GetCompensationVDDCellReadyStatus(void); 953 954 void HAL_SYSCFG_ConfigTimerBreakInput(uint32_t Input); 955 uint32_t HAL_SYSCFG_GetTimerBreakInputConfig(void); 956 957 void HAL_SYSCFG_SetPerceivedCID(uint32_t Cid); 958 uint32_t HAL_SYSCFG_GetPerceivedCID(void); 959 960 void HAL_SYSCFG_SetPerceivedPrivCID(uint32_t Cid); 961 uint32_t HAL_SYSCFG_GetPerceivedPrivCID(void); 962 963 void HAL_SYSCFG_EnableReTimingRXpath(void); 964 void HAL_SYSCFG_DisableReTimingRXpath(void); 965 966 void HAL_SYSCFG_EnableReTimingTXpath(void); 967 void HAL_SYSCFG_DisableReTimingTXpath(void); 968 969 void HAL_SYSCFG_SetDelayOnFeedbackClock(uint32_t Delay); 970 uint32_t HAL_SYSCFG_GetDelayOnFeedbackClock(void); 971 972 void HAL_SYSCFG_EnableInterleavingCpuRam(void); 973 void HAL_SYSCFG_DisableInterleavingCpuRam(void); 974 975 uint32_t HAL_SYSCFG_GetBootPinConnection(uint32_t BootId); 976 977 uint32_t HAL_SYSCFG_GetAddressWritePostingBuffer(void); 978 979 /** 980 * @} 981 */ 982 983 /** 984 * @} 985 */ 986 987 /** 988 * @} 989 */ 990 991 /** 992 * @} 993 */ 994 995 /** 996 * @} 997 */ 998 999 /** 1000 * @} 1001 */ 1002 1003 #ifdef __cplusplus 1004 } 1005 #endif /* __cplusplus */ 1006 1007 #endif /* __STM32N6xx_HAL_H */ 1008
