Searched refs:__CM7_REV (Results 1 – 25 of 40) sorted by relevance
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154 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
155 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
167 #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ macro
164 #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ macro
166 #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ macro
174 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
178 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
177 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
179 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ macro
211 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
214 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
215 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
212 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
218 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
217 #define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */ macro
215 #define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */ macro
227 #define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */ macro