Home
last modified time | relevance | path

Searched refs:USART_CR2_CLKEN (Results 1 – 25 of 461) sorted by relevance

12345678910>>...19

/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_usart.h242 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
765 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
778 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
791 return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); in LL_USART_IsEnabledSCLKOutput()
1484 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
1523 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
1560 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
1598 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
1642 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
1681 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_usart.h244 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
769 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
782 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
795 return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); in LL_USART_IsEnabledSCLKOutput()
1532 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
1571 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
1608 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
1646 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
1690 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
1729 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_usart.h242 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
765 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
778 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
791 return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); in LL_USART_IsEnabledSCLKOutput()
1484 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
1523 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
1560 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
1598 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
1642 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
1681 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_usart.h242 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
765 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
778 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
791 return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); in LL_USART_IsEnabledSCLKOutput()
1484 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
1523 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
1560 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
1598 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
1642 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
1681 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_usart.h316 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1016 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1029 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1042 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2329 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2331 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigAsyncMode()
2399 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2439 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2492 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2494 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigHalfDuplexMode()
[all …]
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_usart.h295 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1010 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1023 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1036 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2299 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2339 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2377 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2416 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2461 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2501 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_usart.h291 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
975 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
988 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1001 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2266 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2306 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2344 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2383 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2428 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2468 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_usart.h310 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1033 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1046 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1059 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2326 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2366 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2404 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2443 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2488 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2528 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_usart.h334 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1257 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1270 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1283 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2670 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2709 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2746 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2784 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2828 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2867 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_usart.h341 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1266 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1279 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1292 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2680 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2720 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2758 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2797 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2842 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2882 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_usart.h341 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1266 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1279 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1292 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2680 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2720 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2758 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2797 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2842 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2882 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_usart.h334 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1259 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1272 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1285 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2673 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2713 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2751 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2790 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2835 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2875 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_usart.h340 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1265 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1278 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1291 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2679 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2719 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2757 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2796 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2841 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2881 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_usart.h340 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1265 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1278 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1291 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2679 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2719 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2757 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2796 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2841 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2881 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_usart.h340 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1265 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1278 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1291 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2679 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2719 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2757 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2796 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2841 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2881 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_usart.h337 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1285 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1298 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1311 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2666 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2706 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2744 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2783 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2828 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2868 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_usart.h352 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1283 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1296 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1309 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2701 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2741 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2779 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2818 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2863 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2903 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_usart.h341 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1266 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1279 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1292 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2680 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2720 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2758 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2797 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2842 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2882 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_usart.h341 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1266 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1279 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1292 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2680 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2720 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2758 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2797 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2842 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2882 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_usart.h337 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1281 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1294 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1307 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2662 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2702 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2740 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2779 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2824 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2864 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_usart.h340 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1265 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1278 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1291 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2679 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2719 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2757 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2796 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2841 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2881 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_usart.h341 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1266 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1279 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1292 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2680 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2720 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2758 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2797 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2842 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2882 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_usart.h340 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1265 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1278 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1291 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2679 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2719 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2757 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2796 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2841 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
2881 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_usart.h384 #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
1365 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1378 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_DisableSCLKOutput()
1391 return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); in LL_USART_IsEnabledSCLKOutput()
2816 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigAsyncMode()
2856 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_ConfigSyncMode()
2894 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigLINMode()
2933 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); in LL_USART_ConfigHalfDuplexMode()
2978 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); in LL_USART_ConfigSmartcardMode()
3018 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); in LL_USART_ConfigIrdaMode()
[all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_usart.c404 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, in LL_USART_ClockInit()
434 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, in LL_USART_ClockInit()
435 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | in LL_USART_ClockInit()

12345678910>>...19