1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_tim_ex.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_TIM_EX_H 21 #define STM32U5xx_HAL_TIM_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIMEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Hall sensor Configuration Structure definition 45 */ 46 47 typedef struct 48 { 49 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 50 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 51 52 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 53 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 54 55 uint32_t IC1Filter; /*!< Specifies the input capture filter. 56 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 57 58 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 59 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 60 } TIM_HallSensor_InitTypeDef; 61 62 /** 63 * @brief TIM Break/Break2 input configuration 64 */ 65 typedef struct 66 { 67 uint32_t Source; /*!< Specifies the source of the timer break input. 68 This parameter can be a value of @ref TIMEx_Break_Input_Source */ 69 uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. 70 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ 71 uint32_t Polarity; /*!< Specifies the break input source polarity. 72 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ 73 } TIMEx_BreakInputConfigTypeDef; 74 75 /** 76 * @brief TIM Encoder index configuration 77 */ 78 typedef struct 79 { 80 uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ 81 82 uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ 83 84 uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 85 86 uint32_t Blanking; /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */ 87 88 FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ 89 90 uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ 91 92 uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ 93 94 } TIMEx_EncoderIndexConfigTypeDef; 95 96 /** 97 * @} 98 */ 99 /* End of exported types -----------------------------------------------------*/ 100 101 /* Exported constants --------------------------------------------------------*/ 102 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 103 * @{ 104 */ 105 106 /** @defgroup TIMEx_Remap TIM Extended Remapping 107 * @{ 108 */ 109 #define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ 110 #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ 111 #if defined(COMP2) 112 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ 113 #endif /* COMP2 */ 114 #define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSIK */ 115 #define TIM_TIM1_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */ 116 #define TIM_TIM1_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSI */ 117 #if defined(ADC2) 118 #define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD2 */ 119 #define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD3 */ 120 #endif /* ADC2 */ 121 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3) /*!< TIM1_ETR is connected to ADC1 AWD1 */ 122 #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD2 */ 123 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC1 AWD3 */ 124 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ 125 #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ 126 #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ 127 #if defined(ADC2) 128 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */ 129 #endif /* ADC2 */ 130 131 #define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ 132 #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ 133 #if defined(COMP2) 134 #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ 135 #endif /* COMP2 */ 136 #define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIK */ 137 #define TIM_TIM2_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ 138 #define TIM_TIM2_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIS */ 139 #if defined(DCMI) && defined(LTDC) 140 #define TIM_TIM2_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI VSYNC */ 141 #define TIM_TIM2_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC_VSYNC */ 142 #endif /* DCMI && LTDC */ 143 #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ 144 #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ 145 #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM5 ETR */ 146 #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ 147 #if defined(DSI) 148 #define TIM_TIM2_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DSI_TE */ 149 #endif /* DSI */ 150 #if defined(DCMI) && defined(LTDC) 151 #define TIM_TIM2_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI HSYNC */ 152 #define TIM_TIM2_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC HSYNC */ 153 #endif /* DCMI && LTDC */ 154 155 #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ 156 #define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ 157 #if defined(COMP2) 158 #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ 159 #endif /* COMP2 */ 160 #define TIM_TIM3_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIK */ 161 #define TIM_TIM3_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ 162 #define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */ 163 #if defined(DCMI) && defined(LTDC) 164 #define TIM_TIM3_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI VSYNC */ 165 #define TIM_TIM3_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC_VSYNC */ 166 #endif /* DCMI && LTDC */ 167 #define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ 168 #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */ 169 #if defined(DSI) 170 #define TIM_TIM3_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DSI_TE */ 171 #endif /* DSI */ 172 #define TIM_TIM3_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD1 */ 173 #define TIM_TIM3_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC1 AWD2 */ 174 #define TIM_TIM3_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD3 */ 175 #if defined(DCMI) && defined(LTDC) 176 #define TIM_TIM3_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI HSYNC */ 177 #define TIM_TIM3_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC HSYNC */ 178 #endif /* DCMI && LTDC */ 179 180 #define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ 181 #define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ 182 #if defined(COMP2) 183 #define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ 184 #endif /* COMP2 */ 185 #define TIM_TIM4_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */ 186 #define TIM_TIM4_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ 187 #define TIM_TIM4_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */ 188 #if defined(DCMI) && defined(LTDC) 189 #define TIM_TIM4_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI VSYNC */ 190 #define TIM_TIM4_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC_VSYNC */ 191 #endif /* DCMI && LTDC */ 192 #define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */ 193 #define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */ 194 #if defined(DSI) 195 #define TIM_TIM4_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */ 196 #endif /* DSI */ 197 #if defined(ADC2) 198 #define TIM_TIM4_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD1 */ 199 #define TIM_TIM4_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to ADC2 AWD2 */ 200 #define TIM_TIM4_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD3 */ 201 #endif /* ADC2 */ 202 #if defined(DCMI) && defined(LTDC) 203 #define TIM_TIM4_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI HSYNC */ 204 #define TIM_TIM4_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC HSYNC */ 205 #endif /* DCMI && LTDC */ 206 207 #define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ 208 #define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */ 209 #if defined(COMP2) 210 #define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */ 211 #endif /* COMP2 */ 212 #define TIM_TIM5_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIK */ 213 #define TIM_TIM5_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to HSI */ 214 #define TIM_TIM5_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIS */ 215 #if defined(DCMI) && defined(LTDC) 216 #define TIM_TIM5_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI VSYNC */ 217 #define TIM_TIM5_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC_VSYNC */ 218 #endif /* DCMI && LTDC */ 219 #define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ 220 #define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ 221 #if defined(DSI) 222 #define TIM_TIM5_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DSI_TE */ 223 #endif /* DSI */ 224 #if defined(DCMI) && defined(LTDC) 225 #define TIM_TIM5_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI HSYNC */ 226 #define TIM_TIM5_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC HSYNC */ 227 #endif /* DCMI && LTDC */ 228 229 #define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ 230 #define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */ 231 #if defined(COMP2) 232 #define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */ 233 #endif /* COMP2 */ 234 #define TIM_TIM8_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIK */ 235 #define TIM_TIM8_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to HSI */ 236 #define TIM_TIM8_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIS */ 237 #if defined(ADC2) 238 #define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD2 */ 239 #define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ 240 #endif /* ADC2 */ 241 #define TIM_TIM8_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC1 AWD1 */ 242 #define TIM_TIM8_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD2 */ 243 #define TIM_TIM8_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC1 AWD3 */ 244 #define TIM_TIM8_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD1 */ 245 #define TIM_TIM8_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC4 AWD2 */ 246 #define TIM_TIM8_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD3 */ 247 #if defined(ADC2) 248 #define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD1 */ 249 #endif /* ADC2 */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup TIMEx_Break_Input TIM Extended Break input 255 * @{ 256 */ 257 #define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ 258 #define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source 264 * @{ 265 */ 266 #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ 267 #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ 268 #if defined(COMP2) 269 #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ 270 #endif /* COMP2 */ 271 #define TIM_BREAKINPUTSOURCE_MDF1 0x00000008U /*!< The analog watchdog output of the MDF1 peripheral is connected to the break input */ 272 /** 273 * @} 274 */ 275 276 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling 277 * @{ 278 */ 279 #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ 280 #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ 281 /** 282 * @} 283 */ 284 285 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity 286 * @{ 287 */ 288 #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ 289 #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection 295 * @{ 296 */ 297 #define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ 298 #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ 299 #if defined(COMP2) 300 #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ 301 #endif /* COMP2 */ 302 303 #define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ 304 #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ 305 #if defined(COMP2) 306 #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ 307 #endif /* COMP2 */ 308 #define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ 309 #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ 310 #if defined(COMP2) 311 #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ 312 #endif /* COMP2 */ 313 #define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ 314 #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ 315 #if defined(COMP2) 316 #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ 317 #endif /* COMP2 */ 318 319 #define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ 320 #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ 321 #if defined(COMP2) 322 #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ 323 #endif /* COMP2 */ 324 #define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ 325 #define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 OUT */ 326 #if defined(COMP2) 327 #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ 328 #endif /* COMP2 */ 329 330 #define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ 331 #define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */ 332 #if defined(COMP2) 333 #define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */ 334 #endif /* COMP2 */ 335 #define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */ 336 #define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4_TI2 is connected to COMP1 OUT */ 337 #if defined(COMP2) 338 #define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4_TI2 is connected to COMP2 OUT */ 339 #endif /* COMP2 */ 340 341 #define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */ 342 #define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to LSI */ 343 #define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to LSE */ 344 #define TIM_TIM5_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to RTC Wakeup */ 345 #define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5_COMP1 is connected to COMP1 OUT */ 346 #if defined(COMP2) 347 #define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5_COMP2 is connected to COMP2 OUT */ 348 #endif /* COMP2 */ 349 350 #define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */ 351 #define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5_TI2 is connected to COMP1 OUT */ 352 #if defined(COMP2) 353 #define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5_TI2 is connected to COMP2 OUT */ 354 #endif /* COMP2 */ 355 356 #define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */ 357 #define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP1 OUT */ 358 #if defined(COMP2) 359 #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP2 OUT */ 360 #endif /* COMP2 */ 361 362 #define TIM_TIM15_TI1_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ 363 #define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to LSE */ 364 #define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to COMP1 OUT */ 365 #if defined(COMP2) 366 #define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 OUT */ 367 #endif /* COMP2 */ 368 #define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */ 369 #if defined(COMP2) 370 #define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to COMP2 OUT */ 371 #endif /* COMP2 */ 372 373 #define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ 374 #define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */ 375 #define TIM_TIM16_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSE/32 */ 376 #define TIM_TIM16_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM16_TI1 is connected to RTC Wakeup */ 377 #define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to LSE */ 378 #define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16_TI1 is connected to LSI */ 379 #define TIM_TIM16_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to MSIS/1024 */ 380 #define TIM_TIM16_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to MSIS/4 */ 381 #define TIM_TIM16_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSI/256 */ 382 383 #define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ 384 #define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to MCO */ 385 #define TIM_TIM17_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSE/32 */ 386 #define TIM_TIM17_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to RTC Wakeup */ 387 #define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to LSE */ 388 #define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17_TI1 is connected to LSI */ 389 #define TIM_TIM17_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MSIS/1024 */ 390 #define TIM_TIM17_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM17_TI1 is connected to MSIS/4 */ 391 #define TIM_TIM17_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSI/256 */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling 397 * @{ 398 */ 399 #define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ 400 #define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking 406 * @{ 407 */ 408 #define TIM_ENCODERINDEX_BLANKING_DISABLE 0x00000000U /*!< Encoder index blanking is disabled */ 409 #define TIM_ENCODERINDEX_BLANKING_TI3 TIM_ECR_IBLK_0 /*!< Encoder index blanking is enabled on TI3 */ 410 #define TIM_ENCODERINDEX_BLANKING_TI4 TIM_ECR_IBLK_1 /*!< Encoder index blanking is enabled on TI4 */ 411 412 /** 413 * @} 414 */ 415 416 /** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position 417 * @{ 418 */ 419 #define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ 420 #define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ 421 #define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ 422 #define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ 423 #define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ 424 #define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ 425 /** 426 * @} 427 */ 428 429 /** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction 430 * @{ 431 */ 432 #define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ 433 #define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ 434 #define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ 435 /** 436 * @} 437 */ 438 439 /** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity 440 * @{ 441 */ 442 #define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 443 #define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler 449 * @{ 450 */ 451 #define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 452 #define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 453 #define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 454 #define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 455 /** 456 * @} 457 */ 458 459 /** 460 * @} 461 */ 462 /* End of exported constants -------------------------------------------------*/ 463 464 /* Exported macro ------------------------------------------------------------*/ 465 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 466 * @{ 467 */ 468 469 /** 470 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 471 * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); 472 * @param __TIMCLK__ timer input clock frequency (in Hz) 473 * @param __CNTCLK__ counter clock frequency (in Hz) 474 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 475 */ 476 #define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 477 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U 478 479 /** 480 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 481 * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); 482 * @param __TIMCLK__ timer input clock frequency (in Hz) 483 * @param __PSC__ prescaler 484 * @param __FREQ__ output signal frequency (in Hz) 485 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 486 */ 487 #define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ 488 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U 489 490 /** 491 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required 492 * output signal frequency. 493 * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); 494 * @note This macro should be used only if dithering is already enabled 495 * @param __TIMCLK__ timer input clock frequency (in Hz) 496 * @param __PSC__ prescaler 497 * @param __FREQ__ output signal frequency (in Hz) 498 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) 499 */ 500 #define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ 501 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ 502 (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U 503 504 /** 505 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare 506 * active/inactive delay. 507 * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); 508 * @param __TIMCLK__ timer input clock frequency (in Hz) 509 * @param __PSC__ prescaler 510 * @param __DELAY__ timer output compare active/inactive delay (in us) 511 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 512 */ 513 #define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ 514 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 515 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 516 517 /** 518 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer 519 * output compare active/inactive delay. 520 * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); 521 * @note This macro should be used only if dithering is already enabled 522 * @param __TIMCLK__ timer input clock frequency (in Hz) 523 * @param __PSC__ prescaler 524 * @param __DELAY__ timer output compare active/inactive delay (in us) 525 * @retval Compare value (between Min_Data=0 and Max_Data=65519) 526 */ 527 #define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ 528 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ 529 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 530 531 /** 532 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 533 * (when the timer operates in one pulse mode). 534 * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); 535 * @param __TIMCLK__ timer input clock frequency (in Hz) 536 * @param __PSC__ prescaler 537 * @param __DELAY__ timer output compare active/inactive delay (in us) 538 * @param __PULSE__ pulse duration (in us) 539 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 540 */ 541 #define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 542 ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ 543 + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) 544 545 /** 546 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required 547 * pulse duration (when the timer operates in one pulse mode). 548 * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); 549 * @note This macro should be used only if dithering is already enabled 550 * @param __TIMCLK__ timer input clock frequency (in Hz) 551 * @param __PSC__ prescaler 552 * @param __DELAY__ timer output compare active/inactive delay (in us) 553 * @param __PULSE__ pulse duration (in us) 554 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) 555 */ 556 #define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 557 ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ 558 + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) 559 560 /** 561 * @} 562 */ 563 /* End of exported macro -----------------------------------------------------*/ 564 565 /* Private macro -------------------------------------------------------------*/ 566 /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 567 * @{ 568 */ 569 #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) 570 #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ 571 ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) 572 573 #if defined(COMP2) 574 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ 575 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ 576 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ 577 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) 578 #else 579 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ 580 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ 581 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) 582 #endif /* COMP2 */ 583 584 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ 585 ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) 586 587 #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ 588 ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) 589 590 #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) 591 592 #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ 593 (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) 594 595 #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ 596 ((((INSTANCE) == TIM1) && \ 597 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 598 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 599 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 600 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 601 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 602 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 603 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 604 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 605 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 606 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 607 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 608 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 609 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 610 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ 611 || \ 612 (((INSTANCE) == TIM2) && \ 613 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 614 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 615 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 616 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 617 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 618 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 619 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 620 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 621 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 622 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 623 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 624 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 625 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 626 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 627 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ 628 || \ 629 (((INSTANCE) == TIM3) && \ 630 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 631 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 632 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 633 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 634 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 635 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 636 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 637 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 638 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 639 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 640 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 641 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 642 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 643 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ 644 || \ 645 (((INSTANCE) == TIM4) && \ 646 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 647 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 648 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 649 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 650 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 651 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 652 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 653 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 654 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 655 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 656 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 657 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 658 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 659 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ 660 || \ 661 (((INSTANCE) == TIM5) && \ 662 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 663 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 664 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 665 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 666 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 667 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 668 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 669 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 670 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 671 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 672 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 673 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 674 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 675 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ 676 || \ 677 (((INSTANCE) == TIM8) && \ 678 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 679 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 680 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 681 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 682 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 683 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 684 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 685 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 686 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 687 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 688 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 689 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 690 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 691 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ 692 || \ 693 (((INSTANCE) == TIM15) && \ 694 (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 695 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 696 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 697 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 698 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 699 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 700 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 701 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 702 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 703 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 704 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 705 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) 706 707 #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ 708 ((((INSTANCE) == TIM1) && \ 709 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 710 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 711 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 712 ((__SELECTION__) == TIM_TS_ITR1) || \ 713 ((__SELECTION__) == TIM_TS_ITR2) || \ 714 ((__SELECTION__) == TIM_TS_ITR3) || \ 715 ((__SELECTION__) == TIM_TS_ETRF) || \ 716 ((__SELECTION__) == TIM_TS_ITR4) || \ 717 ((__SELECTION__) == TIM_TS_ITR5) || \ 718 ((__SELECTION__) == TIM_TS_ITR6) || \ 719 ((__SELECTION__) == TIM_TS_ITR7) || \ 720 ((__SELECTION__) == TIM_TS_ITR8))) \ 721 || \ 722 (((INSTANCE) == TIM2) && \ 723 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 724 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 725 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 726 ((__SELECTION__) == TIM_TS_ITR0) || \ 727 ((__SELECTION__) == TIM_TS_ITR2) || \ 728 ((__SELECTION__) == TIM_TS_ITR3) || \ 729 ((__SELECTION__) == TIM_TS_ETRF) || \ 730 ((__SELECTION__) == TIM_TS_ITR4) || \ 731 ((__SELECTION__) == TIM_TS_ITR5) || \ 732 ((__SELECTION__) == TIM_TS_ITR6) || \ 733 ((__SELECTION__) == TIM_TS_ITR7) || \ 734 ((__SELECTION__) == TIM_TS_ITR8))) \ 735 || \ 736 (((INSTANCE) == TIM3) && \ 737 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 738 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 739 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 740 ((__SELECTION__) == TIM_TS_ITR0) || \ 741 ((__SELECTION__) == TIM_TS_ITR1) || \ 742 ((__SELECTION__) == TIM_TS_ITR3) || \ 743 ((__SELECTION__) == TIM_TS_ETRF) || \ 744 ((__SELECTION__) == TIM_TS_ITR4) || \ 745 ((__SELECTION__) == TIM_TS_ITR5) || \ 746 ((__SELECTION__) == TIM_TS_ITR6) || \ 747 ((__SELECTION__) == TIM_TS_ITR7) || \ 748 ((__SELECTION__) == TIM_TS_ITR8))) \ 749 || \ 750 (((INSTANCE) == TIM4) && \ 751 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 752 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 753 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 754 ((__SELECTION__) == TIM_TS_ITR0) || \ 755 ((__SELECTION__) == TIM_TS_ITR1) || \ 756 ((__SELECTION__) == TIM_TS_ITR2) || \ 757 ((__SELECTION__) == TIM_TS_ITR4) || \ 758 ((__SELECTION__) == TIM_TS_ETRF) || \ 759 ((__SELECTION__) == TIM_TS_ITR5) || \ 760 ((__SELECTION__) == TIM_TS_ITR6) || \ 761 ((__SELECTION__) == TIM_TS_ITR7) || \ 762 ((__SELECTION__) == TIM_TS_ITR8))) \ 763 || \ 764 (((INSTANCE) == TIM5) && \ 765 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 766 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 767 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 768 ((__SELECTION__) == TIM_TS_ITR0) || \ 769 ((__SELECTION__) == TIM_TS_ITR1) || \ 770 ((__SELECTION__) == TIM_TS_ITR2) || \ 771 ((__SELECTION__) == TIM_TS_ITR3) || \ 772 ((__SELECTION__) == TIM_TS_ETRF) || \ 773 ((__SELECTION__) == TIM_TS_ITR5) || \ 774 ((__SELECTION__) == TIM_TS_ITR6) || \ 775 ((__SELECTION__) == TIM_TS_ITR7) || \ 776 ((__SELECTION__) == TIM_TS_ITR8))) \ 777 || \ 778 (((INSTANCE) == TIM8) && \ 779 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 780 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 781 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 782 ((__SELECTION__) == TIM_TS_ITR0) || \ 783 ((__SELECTION__) == TIM_TS_ITR1) || \ 784 ((__SELECTION__) == TIM_TS_ITR2) || \ 785 ((__SELECTION__) == TIM_TS_ITR3) || \ 786 ((__SELECTION__) == TIM_TS_ETRF) || \ 787 ((__SELECTION__) == TIM_TS_ITR4) || \ 788 ((__SELECTION__) == TIM_TS_ITR6) || \ 789 ((__SELECTION__) == TIM_TS_ITR7) || \ 790 ((__SELECTION__) == TIM_TS_ITR8))) \ 791 || \ 792 (((INSTANCE) == TIM15) && \ 793 (((__SELECTION__) == TIM_TS_TI1F_ED) || \ 794 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 795 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 796 ((__SELECTION__) == TIM_TS_ITR0) || \ 797 ((__SELECTION__) == TIM_TS_ITR1) || \ 798 ((__SELECTION__) == TIM_TS_ITR2) || \ 799 ((__SELECTION__) == TIM_TS_ITR3) || \ 800 ((__SELECTION__) == TIM_TS_ITR4) || \ 801 ((__SELECTION__) == TIM_TS_ITR5) || \ 802 ((__SELECTION__) == TIM_TS_ITR7) || \ 803 ((__SELECTION__) == TIM_TS_ITR8)))) 804 805 #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ 806 ((((INSTANCE) == TIM1) && \ 807 (((__SELECTION__) == TIM_TS_ITR1) || \ 808 ((__SELECTION__) == TIM_TS_ITR2) || \ 809 ((__SELECTION__) == TIM_TS_ITR3) || \ 810 ((__SELECTION__) == TIM_TS_ITR4) || \ 811 ((__SELECTION__) == TIM_TS_ITR5) || \ 812 ((__SELECTION__) == TIM_TS_ITR6) || \ 813 ((__SELECTION__) == TIM_TS_ITR7) || \ 814 ((__SELECTION__) == TIM_TS_ITR8) || \ 815 ((__SELECTION__) == TIM_TS_NONE))) \ 816 || \ 817 (((INSTANCE) == TIM2) && \ 818 (((__SELECTION__) == TIM_TS_ITR0) || \ 819 ((__SELECTION__) == TIM_TS_ITR2) || \ 820 ((__SELECTION__) == TIM_TS_ITR3) || \ 821 ((__SELECTION__) == TIM_TS_ITR4) || \ 822 ((__SELECTION__) == TIM_TS_ITR5) || \ 823 ((__SELECTION__) == TIM_TS_ITR6) || \ 824 ((__SELECTION__) == TIM_TS_ITR7) || \ 825 ((__SELECTION__) == TIM_TS_ITR8) || \ 826 ((__SELECTION__) == TIM_TS_ITR11)|| \ 827 ((__SELECTION__) == TIM_TS_NONE))) \ 828 || \ 829 (((INSTANCE) == TIM3) && \ 830 (((__SELECTION__) == TIM_TS_ITR0) || \ 831 ((__SELECTION__) == TIM_TS_ITR1) || \ 832 ((__SELECTION__) == TIM_TS_ITR3) || \ 833 ((__SELECTION__) == TIM_TS_ITR4) || \ 834 ((__SELECTION__) == TIM_TS_ITR5) || \ 835 ((__SELECTION__) == TIM_TS_ITR6) || \ 836 ((__SELECTION__) == TIM_TS_ITR7) || \ 837 ((__SELECTION__) == TIM_TS_ITR8) || \ 838 ((__SELECTION__) == TIM_TS_NONE))) \ 839 || \ 840 (((INSTANCE) == TIM4) && \ 841 (((__SELECTION__) == TIM_TS_ITR0) || \ 842 ((__SELECTION__) == TIM_TS_ITR1) || \ 843 ((__SELECTION__) == TIM_TS_ITR2) || \ 844 ((__SELECTION__) == TIM_TS_ITR4) || \ 845 ((__SELECTION__) == TIM_TS_ITR5) || \ 846 ((__SELECTION__) == TIM_TS_ITR6) || \ 847 ((__SELECTION__) == TIM_TS_ITR7) || \ 848 ((__SELECTION__) == TIM_TS_ITR8) || \ 849 ((__SELECTION__) == TIM_TS_NONE))) \ 850 || \ 851 (((INSTANCE) == TIM5) && \ 852 (((__SELECTION__) == TIM_TS_ITR0) || \ 853 ((__SELECTION__) == TIM_TS_ITR1) || \ 854 ((__SELECTION__) == TIM_TS_ITR2) || \ 855 ((__SELECTION__) == TIM_TS_ITR3) || \ 856 ((__SELECTION__) == TIM_TS_ITR5) || \ 857 ((__SELECTION__) == TIM_TS_ITR6) || \ 858 ((__SELECTION__) == TIM_TS_ITR7) || \ 859 ((__SELECTION__) == TIM_TS_ITR8) || \ 860 ((__SELECTION__) == TIM_TS_NONE))) \ 861 || \ 862 (((INSTANCE) == TIM8) && \ 863 (((__SELECTION__) == TIM_TS_ITR0) || \ 864 ((__SELECTION__) == TIM_TS_ITR1) || \ 865 ((__SELECTION__) == TIM_TS_ITR2) || \ 866 ((__SELECTION__) == TIM_TS_ITR3) || \ 867 ((__SELECTION__) == TIM_TS_ITR4) || \ 868 ((__SELECTION__) == TIM_TS_ITR6) || \ 869 ((__SELECTION__) == TIM_TS_ITR7) || \ 870 ((__SELECTION__) == TIM_TS_ITR8) || \ 871 ((__SELECTION__) == TIM_TS_NONE))) \ 872 || \ 873 (((INSTANCE) == TIM15) && \ 874 (((__SELECTION__) == TIM_TS_ITR0) || \ 875 ((__SELECTION__) == TIM_TS_ITR1) || \ 876 ((__SELECTION__) == TIM_TS_ITR2) || \ 877 ((__SELECTION__) == TIM_TS_ITR3) || \ 878 ((__SELECTION__) == TIM_TS_ITR4) || \ 879 ((__SELECTION__) == TIM_TS_ITR5) || \ 880 ((__SELECTION__) == TIM_TS_ITR7) || \ 881 ((__SELECTION__) == TIM_TS_ITR8) || \ 882 ((__SELECTION__) == TIM_TS_NONE)))) 883 884 #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ 885 (IS_TIM_OC_MODE(__MODE__) \ 886 && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ 887 ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) 888 889 #define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ 890 (((__CHANNEL__) == TIM_CHANNEL_3) || \ 891 ((__CHANNEL__) == TIM_CHANNEL_4)) 892 893 #define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) 894 895 #define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) 896 897 #define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) 898 899 #define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ 900 || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) 901 902 #define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ 903 ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) 904 905 #define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ 906 ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ 907 ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ 908 ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) 909 910 #define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) 911 912 #define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ 913 ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ 914 ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ 915 ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ 916 ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ 917 ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) 918 919 #define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ 920 ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ 921 ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) 922 923 #define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__) (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \ 924 ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3) || \ 925 ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4)) 926 927 /** 928 * @} 929 */ 930 /* End of private macro ------------------------------------------------------*/ 931 932 /* Exported functions --------------------------------------------------------*/ 933 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 934 * @{ 935 */ 936 937 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 938 * @brief Timer Hall Sensor functions 939 * @{ 940 */ 941 /* Timer Hall Sensor functions **********************************************/ 942 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); 943 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 944 945 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 946 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 947 948 /* Blocking mode: Polling */ 949 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 950 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 951 /* Non-Blocking mode: Interrupt */ 952 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 953 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 954 /* Non-Blocking mode: DMA */ 955 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 956 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 957 /** 958 * @} 959 */ 960 961 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 962 * @brief Timer Complementary Output Compare functions 963 * @{ 964 */ 965 /* Timer Complementary Output Compare functions *****************************/ 966 /* Blocking mode: Polling */ 967 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 968 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 969 970 /* Non-Blocking mode: Interrupt */ 971 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 972 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 973 974 /* Non-Blocking mode: DMA */ 975 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 976 uint16_t Length); 977 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 978 /** 979 * @} 980 */ 981 982 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 983 * @brief Timer Complementary PWM functions 984 * @{ 985 */ 986 /* Timer Complementary PWM functions ****************************************/ 987 /* Blocking mode: Polling */ 988 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 989 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 990 991 /* Non-Blocking mode: Interrupt */ 992 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 993 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 994 /* Non-Blocking mode: DMA */ 995 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 996 uint16_t Length); 997 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 998 /** 999 * @} 1000 */ 1001 1002 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 1003 * @brief Timer Complementary One Pulse functions 1004 * @{ 1005 */ 1006 /* Timer Complementary One Pulse functions **********************************/ 1007 /* Blocking mode: Polling */ 1008 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1009 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1010 1011 /* Non-Blocking mode: Interrupt */ 1012 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1013 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 1014 /** 1015 * @} 1016 */ 1017 1018 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 1019 * @brief Peripheral Control functions 1020 * @{ 1021 */ 1022 /* Extended Control functions ************************************************/ 1023 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 1024 uint32_t CommutationSource); 1025 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 1026 uint32_t CommutationSource); 1027 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 1028 uint32_t CommutationSource); 1029 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 1030 const TIM_MasterConfigTypeDef *sMasterConfig); 1031 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 1032 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 1033 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, 1034 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); 1035 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); 1036 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 1037 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); 1038 HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim); 1039 HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim); 1040 1041 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); 1042 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); 1043 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); 1044 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); 1045 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, 1046 uint32_t PulseWidth); 1047 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); 1048 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); 1049 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); 1050 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); 1051 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); 1052 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); 1053 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); 1054 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); 1055 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); 1056 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, 1057 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); 1058 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); 1059 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); 1060 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); 1061 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); 1062 /** 1063 * @} 1064 */ 1065 1066 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 1067 * @brief Extended Callbacks functions 1068 * @{ 1069 */ 1070 /* Extended Callback **********************************************************/ 1071 void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); 1072 void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); 1073 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 1074 void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); 1075 void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); 1076 void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); 1077 void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); 1078 void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); 1079 /** 1080 * @} 1081 */ 1082 1083 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 1084 * @brief Extended Peripheral State functions 1085 * @{ 1086 */ 1087 /* Extended Peripheral State functions ***************************************/ 1088 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); 1089 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); 1090 /** 1091 * @} 1092 */ 1093 1094 /** 1095 * @} 1096 */ 1097 /* End of exported functions -------------------------------------------------*/ 1098 1099 /* Private functions----------------------------------------------------------*/ 1100 /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions 1101 * @{ 1102 */ 1103 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 1104 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); 1105 /** 1106 * @} 1107 */ 1108 /* End of private functions --------------------------------------------------*/ 1109 1110 /** 1111 * @} 1112 */ 1113 1114 /** 1115 * @} 1116 */ 1117 1118 #ifdef __cplusplus 1119 } 1120 #endif 1121 1122 1123 #endif /* STM32U5xx_HAL_TIM_EX_H */ 1124
