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Searched refs:TIM_DCR_DBSS_2 (Results 1 – 25 of 41) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim.c4897 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiWriteStart()
4917 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5351 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiReadStart()
5371 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim.c4897 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiWriteStart()
4917 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5351 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiReadStart()
5371 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim.c4887 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiWriteStart()
4907 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4927 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4947 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5339 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiReadStart()
5359 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5379 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5399 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim.c4897 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiWriteStart()
4917 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4937 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4957 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5351 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiReadStart()
5371 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5391 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5411 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim.c4887 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiWriteStart()
4907 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
4927 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiWriteStart()
4947 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiWriteStart()
5339 tmpDBSS = TIM_DCR_DBSS_2; in HAL_TIM_DMABurst_MultiReadStart()
5359 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
5379 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); in HAL_TIM_DMABurst_MultiReadStart()
5399 tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); in HAL_TIM_DMABurst_MultiReadStart()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_tim.h1352 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 …
1353 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) …
1354 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1355 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_tim.h1320 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 …
1321 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) …
1322 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1323 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_tim.h1281 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 …
1282 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) …
1283 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1284 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_tim.h1413 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 …
1414 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) …
1415 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1416 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_tim.h1428 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 …
1429 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) …
1430 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) …
1431 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) …
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h8907 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32wba52xx.h13075 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32wba54xx.h13783 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32wba5mxx.h13801 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32wba55xx.h13801 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7393 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32h523xx.h9832 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32h562xx.h10558 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
Dstm32h533xx.h10241 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00000400… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h10939 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro
Dstm32u535xx.h10539 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro
Dstm32u575xx.h11562 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h20264 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro
Dstm32h7s7xx.h21579 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro
Dstm32h7s3xx.h21147 #define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000… macro

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