Searched refs:TIM8_OR2_ETRSEL_Pos (Results 1 – 17 of 17) sorted by relevance
14424 #define TIM8_OR2_ETRSEL_Pos (14U) macro14425 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14427 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14428 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14429 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14588 #define TIM8_OR2_ETRSEL_Pos (14U) macro14589 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14591 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14592 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14593 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14745 #define TIM8_OR2_ETRSEL_Pos (14U) macro14746 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14748 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14749 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14750 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14964 #define TIM8_OR2_ETRSEL_Pos (14U) macro14965 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14967 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14968 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14969 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14813 #define TIM8_OR2_ETRSEL_Pos (14U) macro14814 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14816 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14817 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14818 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16295 #define TIM8_OR2_ETRSEL_Pos (14U) macro16296 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */16298 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */16299 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */16300 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15955 #define TIM8_OR2_ETRSEL_Pos (14U) macro15956 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */15958 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */15959 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */15960 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16417 #define TIM8_OR2_ETRSEL_Pos (14U) macro16418 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */16420 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */16421 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */16422 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16916 #define TIM8_OR2_ETRSEL_Pos (14U) macro16917 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */16919 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */16920 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */16921 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16764 #define TIM8_OR2_ETRSEL_Pos (14U) macro16765 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */16767 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */16768 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */16769 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
17263 #define TIM8_OR2_ETRSEL_Pos (14U) macro17264 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */17266 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */17267 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */17268 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
17424 #define TIM8_OR2_ETRSEL_Pos (14U) macro17425 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */17427 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */17428 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */17429 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
17935 #define TIM8_OR2_ETRSEL_Pos (14U) macro17936 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */17938 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */17939 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */17940 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
20048 #define TIM8_OR2_ETRSEL_Pos (14U) macro20049 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */20051 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */20052 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */20053 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
20395 #define TIM8_OR2_ETRSEL_Pos (14U) macro20396 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */20398 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */20399 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */20400 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
14931 #define TIM8_OR2_ETRSEL_Pos (14U) macro14932 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */14934 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */14935 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */14936 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
15670 #define TIM8_OR2_ETRSEL_Pos (14U) macro15671 #define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */15673 #define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */15674 #define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */15675 #define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
