Searched refs:TIM8_OR1_ETR_ADC2_RMP_Pos (Results 1 – 9 of 9) sorted by relevance
14385 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro14386 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */14388 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */14389 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14549 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro14550 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */14552 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */14553 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14706 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro14707 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */14709 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */14710 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14925 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro14926 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */14928 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */14929 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
14774 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro14775 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */14777 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */14778 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
16256 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro16257 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */16259 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */16260 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
15916 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro15917 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */15919 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */15920 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
17390 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro17391 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */17393 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */17394 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
17901 #define TIM8_OR1_ETR_ADC2_RMP_Pos (0U) macro17902 #define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000003 */17904 #define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000001 */17905 #define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos) /*!< 0x00000002 */
