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Searched refs:TIM5_AF1_ETRSEL_1 (Results 1 – 25 of 49) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_tim_ex.h123 #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
125 #define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */
133 #define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is conn…
Dstm32h7xx_ll_tim.h1023 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1
1025 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1
1033 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_tim_ex.h123 #define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< …
124 #define TIM_TIM5_ETR_OTG_SOF (TIM5_AF1_ETRSEL_1 | TIM5_AF1_ETRSEL_0) /* !< …
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h18461 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h7b0xx.h18941 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h7b0xxq.h18953 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h7a3xxq.h18473 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h7b3xx.h18948 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h7b3xxq.h18960 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h730xxq.h20641 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h733xx.h20629 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h725xx.h20154 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h730xx.h20629 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h735xx.h20641 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h742xx.h19551 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h723xx.h20142 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h750xx.h20480 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h753xx.h20486 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h745xx.h20861 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h745xg.h20861 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h743xx.h20199 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h755xx.h21148 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h757xx.h24321 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h747xg.h24034 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32h747xx.h24034 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro

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