Searched refs:TIM4_OR1_OCREF_CLR_Pos (Results 1 – 3 of 3) sorted by relevance
7868 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro7869 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */7871 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */7872 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
9402 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro9403 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */9405 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */9406 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
9098 #define TIM4_OR1_OCREF_CLR_Pos (0U) macro9099 #define TIM4_OR1_OCREF_CLR_Msk (0x3UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000003 */9101 #define TIM4_OR1_OCREF_CLR_0 (0x1UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */9102 #define TIM4_OR1_OCREF_CLR_1 (0x2UL << TIM4_OR1_OCREF_CLR_Pos) /*!< 0x00000002 */
