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Searched refs:TIM4_AF1_ETRSEL_1 (Results 1 – 25 of 28) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_tim_ex.h124 #define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /*!< TIM4_ETR is co…
127 #define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /*!< TIM4_ETR is co…
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g0b0xx.h7879 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32g0c1xx.h9413 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32g0b1xx.h9109 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h32820 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151fxx_cm4.h32983 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151axx_ca7.h32820 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151axx_cm4.h32786 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151dxx_cm4.h32786 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151cxx_ca7.h33017 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151cxx_cm4.h32983 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp151fxx_ca7.h33017 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153axx_ca7.h34371 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153axx_cm4.h34337 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153cxx_ca7.h34568 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153cxx_cm4.h34534 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153dxx_ca7.h34371 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153dxx_cm4.h34337 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153fxx_ca7.h34568 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp153fxx_cm4.h34534 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp157axx_ca7.h35594 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp157axx_cm4.h35560 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp157cxx_ca7.h35791 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp157cxx_cm4.h35757 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32mp157dxx_ca7.h35594 #define TIM4_AF1_ETRSEL_1 (0x2UL << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro

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