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Searched refs:TIM1_OR_ETR_ADC1_RMP_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h9526 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
9527 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
9529 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
9530 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb1mxx.h9549 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
9550 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
9552 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
9553 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb30xx.h9522 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
9523 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
9525 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
9526 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb35xx.h10907 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
10908 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
10910 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
10911 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb55xx.h11812 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
11813 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
11815 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
11816 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb5mxx.h11812 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
11813 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
11815 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
11816 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h9377 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
9378 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
9380 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
9381 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
Dstm32wb15xx.h9549 #define TIM1_OR_ETR_ADC1_RMP_Pos (0U) macro
9550 #define TIM1_OR_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
9552 #define TIM1_OR_ETR_ADC1_RMP_0 (0x1U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
9553 #define TIM1_OR_ETR_ADC1_RMP_1 (0x2U << TIM1_OR_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */