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Searched refs:TIM1_OR1_ETR_ADC_RMP_Pos (Results 1 – 5 of 5) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h9328 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) macro
9329 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */
9331 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */
9332 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */
Dstm32wle5xx.h9328 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) macro
9329 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */
9331 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */
9332 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */
Dstm32wl5mxx.h11000 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) macro
11001 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */
11003 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */
11004 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */
Dstm32wl54xx.h11000 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) macro
11001 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */
11003 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */
11004 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */
Dstm32wl55xx.h11000 #define TIM1_OR1_ETR_ADC_RMP_Pos (0U) macro
11001 #define TIM1_OR1_ETR_ADC_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000003 */
11003 #define TIM1_OR1_ETR_ADC_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000001 */
11004 #define TIM1_OR1_ETR_ADC_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos) /*!< 0x00000002 */