Searched refs:TIM1_OR1_ETR_ADC3_RMP_Pos (Results 1 – 7 of 7) sorted by relevance
14321 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro14322 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */14324 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */14325 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14485 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro14486 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */14488 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */14489 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14642 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro14643 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */14645 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */14646 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14861 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro14862 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */14864 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */14865 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
14710 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro14711 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */14713 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */14714 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
16192 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro16193 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */16195 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */16196 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
15852 #define TIM1_OR1_ETR_ADC3_RMP_Pos (2U) macro15853 #define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x0000000C */15855 #define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000004 */15856 #define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos) /*!< 0x00000008 */
