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Searched refs:TIM17_OR1_TI1_RMP_Pos (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h9355 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
9356 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
9358 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
9359 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wle5xx.h9355 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
9356 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
9358 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
9359 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl5mxx.h11027 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
11028 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11030 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11031 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl54xx.h11027 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
11028 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11030 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11031 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32wl55xx.h11027 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
11028 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
11030 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
11031 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l471xx.h14556 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
14557 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14559 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14560 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l475xx.h14720 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
14721 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14723 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14724 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l476xx.h14877 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
14878 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14880 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14881 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l486xx.h15096 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
15097 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15099 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15100 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l485xx.h14945 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
14946 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
14948 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
14949 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4a6xx.h16428 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
16429 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16431 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16432 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l496xx.h16088 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
16089 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16091 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16092 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4r5xx.h16549 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
16550 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16552 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16553 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4r7xx.h17048 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
17049 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
17051 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
17052 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4s5xx.h16896 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
16897 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16899 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16900 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4s7xx.h17395 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
17396 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
17398 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
17399 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4p5xx.h17557 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
17558 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
17560 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
17561 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4q5xx.h18068 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
18069 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
18071 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
18072 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4r9xx.h20180 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
20181 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
20183 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
20184 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l4s9xx.h20527 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
20528 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
20530 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
20531 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h15063 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
15064 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15066 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15067 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
Dstm32l562xx.h15802 #define TIM17_OR1_TI1_RMP_Pos (0U) macro
15803 #define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
15805 #define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
15806 #define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */