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Searched refs:SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h31707 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31708 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151fxx_cm4.h31870 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31871 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151axx_ca7.h31707 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31708 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151axx_cm4.h31673 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31674 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151dxx_cm4.h31673 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31674 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151cxx_ca7.h31904 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31905 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151cxx_cm4.h31870 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31871 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp151fxx_ca7.h31904 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
31905 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153axx_ca7.h33258 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33259 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153axx_cm4.h33224 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33225 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153cxx_ca7.h33455 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33456 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153cxx_cm4.h33421 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33422 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153dxx_ca7.h33258 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33259 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153dxx_cm4.h33224 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33225 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153fxx_ca7.h33455 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33456 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp153fxx_cm4.h33421 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
33422 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157axx_ca7.h34481 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34482 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157axx_cm4.h34447 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34448 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157cxx_ca7.h34678 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34679 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157cxx_cm4.h34644 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34645 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157dxx_ca7.h34481 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34482 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157dxx_cm4.h34447 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34448 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157fxx_ca7.h34678 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34679 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …
Dstm32mp157fxx_cm4.h34644 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U) macro
34645 #define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1UL << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) …