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Searched refs:SPI_SR_OVR_Pos (Results 1 – 25 of 278) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4395 #define SPI_SR_OVR_Pos (6U) macro
4396 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f101xb.h4457 #define SPI_SR_OVR_Pos (6U) macro
4458 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f100xb.h4862 #define SPI_SR_OVR_Pos (6U) macro
4863 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f102x6.h5514 #define SPI_SR_OVR_Pos (6U) macro
5515 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f100xe.h5376 #define SPI_SR_OVR_Pos (6U) macro
5377 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f101xg.h5462 #define SPI_SR_OVR_Pos (6U) macro
5463 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f101xe.h5388 #define SPI_SR_OVR_Pos (6U) macro
5389 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3857 #define SPI_SR_OVR_Pos (6U) macro
3858 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f030x8.h3901 #define SPI_SR_OVR_Pos (6U) macro
3902 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f070x6.h3937 #define SPI_SR_OVR_Pos (6U) macro
3938 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f031x6.h4018 #define SPI_SR_OVR_Pos (6U) macro
4019 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f030xc.h4227 #define SPI_SR_OVR_Pos (6U) macro
4228 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f038xx.h3990 #define SPI_SR_OVR_Pos (6U) macro
3991 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32f070xb.h4095 #define SPI_SR_OVR_Pos (6U) macro
4096 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h4763 #define SPI_SR_OVR_Pos (6U) macro
4764 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l010x8.h4438 #define SPI_SR_OVR_Pos (6U) macro
4439 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l010xb.h4486 #define SPI_SR_OVR_Pos (6U) macro
4487 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l011xx.h4503 #define SPI_SR_OVR_Pos (6U) macro
4504 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l021xx.h4640 #define SPI_SR_OVR_Pos (6U) macro
4641 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l031xx.h4626 #define SPI_SR_OVR_Pos (6U) macro
4627 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l051xx.h4735 #define SPI_SR_OVR_Pos (6U) macro
4736 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l010x4.h4394 #define SPI_SR_OVR_Pos (6U) macro
4395 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l010x6.h4446 #define SPI_SR_OVR_Pos (6U) macro
4447 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l081xx.h5006 #define SPI_SR_OVR_Pos (6U) macro
5007 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Dstm32l071xx.h4869 #define SPI_SR_OVR_Pos (6U) macro
4870 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */

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