1 /* USER CODE BEGIN Header */ 2 /** 3 ****************************************************************************** 4 * @file transport_layer.h 5 * @author VMA RF Application Team 6 * @version V1.0.0 7 * @date July-2015 8 * @brief 9 ****************************************************************************** 10 * @attention 11 * 12 * Copyright (c) 2024 STMicroelectronics. 13 * All rights reserved. 14 * 15 * This software is licensed under terms that can be found in the LICENSE file 16 * in the root directory of this software component. 17 * If no LICENSE file comes with this software, it is provided AS-IS. 18 * 19 ****************************************************************************** 20 */ 21 /* USER CODE END Header */ 22 23 /* Define to prevent recursive inclusion -------------------------------------*/ 24 #ifndef TRANSPORT_LAYER_H 25 #define TRANSPORT_LAYER_H 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include <stdint.h> 29 #include "crash_handler.h" 30 31 /* Exported types ------------------------------------------------------------*/ 32 /* Exported constants --------------------------------------------------------*/ 33 #define BLUE_FLAG_RAM_RESET 0x01010101 34 35 #define DMA_IDLE 0 36 #define DMA_IN_PROGRESS 1 37 38 #define DMA_RX_BUFFER_SIZE 64 39 40 typedef enum { 41 SPI_PROT_INIT_STATE = 0, /* Initialization phase */ 42 SPI_PROT_CONFIGURED_STATE, /* Configuration phase */ 43 SPI_PROT_SLEEP_STATE, /* Sleep phase */ 44 SPI_PROT_CONFIGURED_HOST_REQ_STATE, /* Host request phase */ 45 SPI_PROT_CONFIGURED_EVENT_PEND_STATE, /* Event pending phase */ 46 SPI_PROT_WAITING_HEADER_STATE, /* Waiting header phase */ 47 SPI_PROT_HEADER_RECEIVED_STATE, /* Header received phase */ 48 SPI_PROT_WAITING_DATA_STATE, /* Waiting data phase */ 49 SPI_PROT_TRANS_COMPLETE_STATE, /* Transaction complete phase */ 50 } SpiProtoType; 51 52 extern SpiProtoType spi_proto_state; 53 54 #ifdef DEBUG_DTM 55 typedef enum { 56 EMPTY = 0, /* Initialization phase */ 57 GPIO_IRQ = 1000, /* Initialization phase */ 58 GPIO_CS_FALLING, /* Configuration phase */ 59 GPIO_CS_RISING, /* Event pending phase */ 60 PARSE_HOST_REQ, /* Host request phase */ 61 PARSE_EVENT_PEND, /* Sleep phase */ 62 ADVANCE_DMA_WRITE, /* Waiting header phase */ 63 ADVANCE_DMA_READ, /* Header received phase */ 64 ADVANCE_DMA_EVENT_PEND, /* Waiting data phase */ 65 ADVANCE_DMA_RESTORE_0, 66 ADVANCE_DMA_RESTORE_1, 67 ADVANCE_DMA_RESTORE, 68 RESTORE_SAVE, 69 ADVANCE_DMA_DISCARD, 70 ENQUEUE_EVENT, 71 SEND_DATA, 72 RECEIVE_DATA, 73 BTLE_STACK_TICK_ON, 74 BTLE_STACK_TICK_OFF, 75 HEADER_RECEIVED, 76 HEADER_NOT_RECEIVED, 77 ENTER_SLEEP_FUNC, 78 EXIT_SLEEP_FUNC, 79 COMMAND_PROCESSED, 80 CPU_HALT0, 81 CPU_HALT1, 82 CPU_HALT2, 83 CPU_RUNNING0, 84 CPU_RUNNING1, 85 DEEP_SLEEP0, 86 DEEP_SLEEP1, 87 SPI_PROT_TRANS_COMPLETE, 88 SPI_PROT_WAITING_DATA, 89 EDGE_SENSITIVE, 90 SLEEP_CHECK_PERFORMED, 91 DISABLE_IRQ0, 92 DISABLE_IRQ1, 93 DMA_REARM, 94 DMA_TC, 95 IRQ_FALL, 96 IRQ_RISE, 97 TXFIFO_NE, 98 SPI_PROT_INIT_STATE_ANN, /* Initialization phase */ 99 SPI_PROT_CONFIGURED_STATE_ANN, /* Configuration phase */ 100 SPI_PROT_SLEEP_STATE_ANN, /* Sleep phase */ 101 SPI_PROT_CONFIGURED_HOST_REQ_STATE_ANN, /* Host request phase */ 102 SPI_PROT_CONFIGURED_EVENT_PEND_STATE_ANN, /* Event pending phase */ 103 SPI_PROT_WAITING_HEADER_STATE_ANN, /* Waiting header phase */ 104 SPI_PROT_HEADER_RECEIVED_STATE_ANN, /* Header received phase */ 105 SPI_PROT_WAITING_DATA_STATE_ANN, /* Waiting data phase */ 106 SPI_PROT_TRANS_COMPLETE_STATE_ANN, /* Transaction complete phase */ 107 } DebugLabel; 108 109 #define DEBUG_ARRAY_LEN 1000 110 extern DebugLabel debug_buf[DEBUG_ARRAY_LEN]; 111 extern uint32_t debug_cnt; 112 #define DEBUG_NOTES(NOTE) do{\ 113 debug_buf[debug_cnt] = NOTE; debug_cnt = (debug_cnt+1)%DEBUG_ARRAY_LEN;\ 114 }while(0) 115 116 #define SPI_STATE_TRANSACTION(NEWSTATE) do{ \ 117 spi_proto_state = NEWSTATE; \ 118 DEBUG_NOTES(NEWSTATE ## _ANN); \ 119 LL_GPIO_SetOutputPin(DEBUG_GPIO_PORT, DEBUG_TEST_1_PIN); __NOP;\ 120 LL_GPIO_ResetOutputPin(DEBUG_GPIO_PORT, DEBUG_TEST_1_PIN);\ 121 }while(0) 122 123 #else 124 125 #define DEBUG_NOTES(NOTE) 126 127 #define SPI_STATE_TRANSACTION(NEWSTATE) (spi_proto_state = NEWSTATE) 128 129 #endif 130 131 #define SPI_STATE_CHECK(STATE) (spi_proto_state==STATE) 132 #define SPI_STATE_FROM(STATE) (spi_proto_state>=STATE) 133 134 /* Exported macro ------------------------------------------------------------*/ 135 /* Exported functions ------------------------------------------------------- */ 136 137 extern void transport_layer_init(void); 138 extern void transport_layer_tick (void); 139 extern void command_received(uint8_t *cmd, uint16_t len); 140 extern void send_event(const uint8_t *buffer_out, uint16_t buffer_out_length, int8_t overflow_index); 141 extern void send_event_2buffers(const uint8_t *buffer_out1, uint16_t buffer_out_length1, const uint8_t *buffer_out2, uint16_t buffer_out_length2, int8_t overflow_index); 142 extern void advance_dma(void); 143 /* The transport layer request to process a command or event in the queue. */ 144 void TL_ProcessReqCallback(void); 145 /* A request to reset the devie has been received. */ 146 void TL_ResetReqCallback(void); 147 148 #endif /* TRANSPORT_LAYER_H */ 149
