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Searched refs:SPI_IFCR_EOTC_Pos (Results 1 – 25 of 77) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h7474 #define SPI_IFCR_EOTC_Pos (3U) macro
7475 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32wba52xx.h11477 #define SPI_IFCR_EOTC_Pos (3U) macro
11478 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32wba54xx.h12185 #define SPI_IFCR_EOTC_Pos (3U) macro
12186 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32wba5mxx.h12203 #define SPI_IFCR_EOTC_Pos (3U) macro
12204 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32wba55xx.h12203 #define SPI_IFCR_EOTC_Pos (3U) macro
12204 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h12691 #define SPI_IFCR_EOTC_Pos (3U) macro
12692 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32h523xx.h18677 #define SPI_IFCR_EOTC_Pos (3U) macro
18678 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32h562xx.h20221 #define SPI_IFCR_EOTC_Pos (3U) macro
20222 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32h533xx.h19270 #define SPI_IFCR_EOTC_Pos (3U) macro
19271 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h16992 #define SPI_IFCR_EOTC_Pos (3U) macro
16993 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h7b0xx.h17472 #define SPI_IFCR_EOTC_Pos (3U) macro
17473 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h7b0xxq.h17484 #define SPI_IFCR_EOTC_Pos (3U) macro
17485 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h7a3xxq.h17004 #define SPI_IFCR_EOTC_Pos (3U) macro
17005 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h7b3xx.h17479 #define SPI_IFCR_EOTC_Pos (3U) macro
17480 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h7b3xxq.h17491 #define SPI_IFCR_EOTC_Pos (3U) macro
17492 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h730xxq.h19058 #define SPI_IFCR_EOTC_Pos (3U) macro
19059 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h733xx.h19046 #define SPI_IFCR_EOTC_Pos (3U) macro
19047 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h725xx.h18571 #define SPI_IFCR_EOTC_Pos (3U) macro
18572 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h730xx.h19046 #define SPI_IFCR_EOTC_Pos (3U) macro
19047 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
Dstm32h735xx.h19058 #define SPI_IFCR_EOTC_Pos (3U) macro
19059 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h20808 #define SPI_IFCR_EOTC_Pos (3U) macro
20809 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32u535xx.h20212 #define SPI_IFCR_EOTC_Pos (3U) macro
20213 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32u575xx.h23347 #define SPI_IFCR_EOTC_Pos (3U) macro
23348 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h18715 #define SPI_IFCR_EOTC_Pos (3U) macro
18716 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…
Dstm32h7s7xx.h20030 #define SPI_IFCR_EOTC_Pos (3U) macro
20031 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008…

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