Home
last modified time | relevance | path

Searched refs:SPI_DR_DR_Msk (Results 1 – 25 of 201) sorted by relevance

123456789

/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4404 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4405 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f101xb.h4466 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4467 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f100xb.h4871 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4872 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f102x6.h5523 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
5524 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f100xe.h5385 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
5386 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f101xg.h5471 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
5472 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f101xe.h5397 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
5398 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3879 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
3880 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f030x8.h3923 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
3924 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f070x6.h3959 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
3960 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f031x6.h4040 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
4041 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f030xc.h4249 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
4250 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f038xx.h4012 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
4013 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32f070xb.h4117 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ macro
4118 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h4775 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4776 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l010x8.h4450 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4451 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l010xb.h4498 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4499 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l011xx.h4515 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4516 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l021xx.h4652 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4653 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l031xx.h4638 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4639 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l051xx.h4747 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4748 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l010x4.h4406 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4407 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l010x6.h4458 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4459 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l081xx.h5018 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
5019 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Dstm32l071xx.h4881 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ macro
4882 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */

123456789