1 /** 2 ****************************************************************************** 3 * @file shci.h 4 * @author MCD Application Team 5 * @brief HCI command for the system channel 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018-2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __SHCI_H 22 #define __SHCI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "mbox_def.h" /* Requested to expose the MB_WirelessFwInfoTable_t structure */ 30 31 /* Exported types ------------------------------------------------------------*/ 32 33 /* SYSTEM EVENT */ 34 typedef enum 35 { 36 WIRELESS_FW_RUNNING = 0x00, 37 FUS_FW_RUNNING = 0x01, 38 } SHCI_SysEvt_Ready_Rsp_t; 39 40 /* ERROR CODES 41 * 42 * These error codes are detected on CPU2 side and are send back to the CPU1 via a system 43 * notification message. It is up to the application running on CPU1 to manage these errors 44 * 45 * These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..) 46 */ 47 typedef enum 48 { 49 ERR_BLE_INIT = 0, /* This event is currently not reported by the CPU2 */ 50 ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */ 51 ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the CPU1 to control the Thread stack is unknown */ 52 ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the CPU1 to control the Zigbee stack is unknown */ 53 } SCHI_SystemErrCode_t; 54 55 #define SHCI_EVTCODE ( 0xFF ) 56 #define SHCI_SUB_EVT_CODE_BASE ( 0x9200 ) 57 58 /** 59 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION 60 */ 61 typedef enum 62 { 63 SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE, 64 SHCI_SUB_EVT_ERROR_NOTIF, 65 SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE, 66 SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE, 67 SHCI_SUB_EVT_NVM_START_WRITE, 68 SHCI_SUB_EVT_NVM_END_WRITE, 69 SHCI_SUB_EVT_NVM_START_ERASE, 70 SHCI_SUB_EVT_NVM_END_ERASE, 71 SHCI_SUB_EVT_CODE_CONCURRENT_802154_EVT, 72 } SHCI_SUB_EVT_CODE_t; 73 74 /** 75 * SHCI_SUB_EVT_CODE_READY 76 * This notifies the CPU1 that the CPU2 is now ready to receive commands 77 * It reports as well which firmware is running on CPU2 : The wireless stack of the FUS (previously named RSS) 78 */ 79 typedef PACKED_STRUCT{ 80 SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp; 81 } SHCI_C2_Ready_Evt_t; 82 83 /** 84 * SHCI_SUB_EVT_ERROR_NOTIF 85 * This reports to the CPU1 some error form the CPU2 86 */ 87 typedef PACKED_STRUCT{ 88 SCHI_SystemErrCode_t errorCode; 89 } SHCI_C2_ErrorNotif_Evt_t; 90 91 /** 92 * SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE 93 * This notifies the CPU1 which part of the BLE NVM RAM has been updated so that only the modified 94 * section could be written in Flash/NVM 95 * StartAddress : Start address of the section that has been modified 96 * Size : Size (in bytes) of the section that has been modified 97 */ 98 typedef PACKED_STRUCT{ 99 uint32_t StartAddress; 100 uint32_t Size; 101 } SHCI_C2_BleNvmRamUpdate_Evt_t; 102 103 /** 104 * SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE 105 * This notifies the CPU1 which part of the OT NVM RAM has been updated so that only the modified 106 * section could be written in Flash/NVM 107 * StartAddress : Start address of the section that has been modified 108 * Size : Size (in bytes) of the section that has been modified 109 */ 110 typedef PACKED_STRUCT{ 111 uint32_t StartAddress; 112 uint32_t Size; 113 } SHCI_C2_ThreadNvmRamUpdate_Evt_t; 114 115 /** 116 * SHCI_SUB_EVT_NVM_START_WRITE 117 * This notifies the CPU1 that the CPU2 has started a write procedure in Flash 118 * NumberOfWords : The number of 64bits data the CPU2 needs to write in Flash. 119 * For each 64bits data, the algorithm as described in AN5289 is executed. 120 * When this number is reported to 0, it means the Number of 64bits to be written 121 * was unknown when the procedure has started. 122 * When all data are written, the SHCI_SUB_EVT_NVM_END_WRITE event is reported 123 */ 124 typedef PACKED_STRUCT{ 125 uint32_t NumberOfWords; 126 } SHCI_C2_NvmStartWrite_Evt_t; 127 128 /** 129 * SHCI_SUB_EVT_NVM_END_WRITE 130 * This notifies the CPU1 that the CPU2 has written all expected data in Flash 131 */ 132 133 /** 134 * SHCI_SUB_EVT_NVM_START_ERASE 135 * This notifies the CPU1 that the CPU2 has started a erase procedure in Flash 136 * NumberOfSectors : The number of sectors the CPU2 needs to erase in Flash. 137 * For each sector, the algorithm as described in AN5289 is executed. 138 * When this number is reported to 0, it means the Number of sectors to be erased 139 * was unknown when the procedure has started. 140 * When all sectors are erased, the SHCI_SUB_EVT_NVM_END_ERASE event is reported 141 */ 142 typedef PACKED_STRUCT{ 143 uint32_t NumberOfSectors; 144 } SHCI_C2_NvmStartErase_Evt_t; 145 146 /** 147 * SHCI_SUB_EVT_NVM_END_ERASE 148 * This notifies the CPU1 that the CPU2 has erased all expected flash sectors 149 */ 150 151 /* SYSTEM COMMAND */ 152 typedef PACKED_STRUCT 153 { 154 /** 155 * MetaData holds : 156 * 2*32bits for chaining list 157 * 1*32bits with BLE header (type + Opcode + Length) 158 */ 159 uint32_t MetaData[3]; 160 } SHCI_Header_t; 161 162 typedef enum 163 { 164 SHCI_Success = 0x00, 165 SHCI_UNKNOWN_CMD = 0x01, 166 SHCI_MEMORY_CAPACITY_EXCEEDED_ERR_CODE= 0x07, 167 SHCI_ERR_UNSUPPORTED_FEATURE = 0x11, 168 SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12, 169 SHCI_ERR_INVALID_PARAMS = 0x42, /* only used for release < v1.13.0 */ 170 SHCI_ERR_INVALID_PARAMS_V2 = 0x92, /* available for release >= v1.13.0 */ 171 SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF, 172 } SHCI_CmdStatus_t; 173 174 typedef enum 175 { 176 SHCI_8BITS = 0x01, 177 SHCI_16BITS = 0x02, 178 SHCI_32BITS = 0x04, 179 } SHCI_Busw_t; 180 181 #define SHCI_OGF ( 0x3F ) 182 #define SHCI_OCF_BASE ( 0x50 ) 183 184 /** 185 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION 186 */ 187 typedef enum 188 { 189 SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE, 190 SHCI_OCF_C2_RESERVED2, 191 SHCI_OCF_C2_FUS_GET_STATE, 192 SHCI_OCF_C2_FUS_RESERVED1, 193 SHCI_OCF_C2_FUS_FW_UPGRADE, 194 SHCI_OCF_C2_FUS_FW_DELETE, 195 SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY, 196 SHCI_OCF_C2_FUS_LOCK_AUTH_KEY, 197 SHCI_OCF_C2_FUS_STORE_USR_KEY, 198 SHCI_OCF_C2_FUS_LOAD_USR_KEY, 199 SHCI_OCF_C2_FUS_START_WS, 200 SHCI_OCF_C2_FUS_RESERVED2, 201 SHCI_OCF_C2_FUS_RESERVED3, 202 SHCI_OCF_C2_FUS_LOCK_USR_KEY, 203 SHCI_OCF_C2_FUS_UNLOAD_USR_KEY, 204 SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK, 205 SHCI_OCF_C2_FUS_RESERVED7, 206 SHCI_OCF_C2_FUS_RESERVED8, 207 SHCI_OCF_C2_FUS_RESERVED9, 208 SHCI_OCF_C2_FUS_RESERVED10, 209 SHCI_OCF_C2_FUS_RESERVED11, 210 SHCI_OCF_C2_FUS_RESERVED12, 211 SHCI_OCF_C2_BLE_INIT, 212 SHCI_OCF_C2_THREAD_INIT, 213 SHCI_OCF_C2_DEBUG_INIT, 214 SHCI_OCF_C2_FLASH_ERASE_ACTIVITY, 215 SHCI_OCF_C2_CONCURRENT_SET_MODE, 216 SHCI_OCF_C2_FLASH_STORE_DATA, 217 SHCI_OCF_C2_FLASH_ERASE_DATA, 218 SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER, 219 SHCI_OCF_C2_MAC_802_15_4_INIT, 220 SHCI_OCF_C2_REINIT, 221 SHCI_OCF_C2_ZIGBEE_INIT, 222 SHCI_OCF_C2_LLD_TESTS_INIT, 223 SHCI_OCF_C2_EXTPA_CONFIG, 224 SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL, 225 SHCI_OCF_C2_BLE_LLD_INIT, 226 SHCI_OCF_C2_CONFIG, 227 SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME, 228 SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION, 229 SHCI_OCF_C2_802_15_4_DEINIT, 230 SHCI_OCF_C2_SET_SYSTEM_CLOCK, 231 } SHCI_OCF_t; 232 233 #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE) 234 /** No command parameters */ 235 /** Response parameters*/ 236 /** It responds a 1 byte value holding FUS State error code when the FUS State value is 0xFF (FUS_STATE_VALUE_ERROR) */ 237 typedef enum 238 { 239 FUS_STATE_ERROR_NO_ERROR = 0x00, 240 FUS_STATE_ERROR_IMG_NOT_FOUND = 0x01, 241 FUS_STATE_ERROR_IMG_CORRUPT = 0x02, 242 FUS_STATE_ERROR_IMG_NOT_AUTHENTIC = 0x03, 243 FUS_STATE_ERROR_IMG_NOT_ENOUGH_SPACE = 0x04, 244 FUS_STATE_ERROR_IMAGE_USRABORT = 0x05, 245 FUS_STATE_ERROR_IMAGE_ERSERROR = 0x06, 246 FUS_STATE_ERROR_IMAGE_WRTERROR = 0x07, 247 FUS_STATE_ERROR_AUTH_TAG_ST_NOTFOUND = 0x08, 248 FUS_STATE_ERROR_AUTH_TAG_CUST_NOTFOUND = 0x09, 249 FUS_STATE_ERROR_AUTH_KEY_LOCKED = 0x0A, 250 FUS_STATE_ERROR_FW_ROLLBACK_ERROR = 0x11, 251 FUS_STATE_ERROR_STATE_NOT_RUNNING = 0xFE, 252 FUS_STATE_ERROR_ERR_UNKNOWN = 0xFF, 253 } SHCI_FUS_GetState_ErrorCode_t; 254 255 enum 256 { 257 FUS_STATE_VALUE_IDLE = 0x00, 258 FUS_STATE_VALUE_FW_UPGRD_ONGOING = 0x10, 259 FUS_STATE_VALUE_FW_UPGRD_ONGOING_END = 0x1F, /* All values between 0x10 and 0x1F has the same meaning */ 260 FUS_STATE_VALUE_FUS_UPGRD_ONGOING = 0x20, 261 FUS_STATE_VALUE_FUS_UPGRD_ONGOING_END = 0x2F, /* All values between 0x20 and 0x2F has the same meaning */ 262 FUS_STATE_VALUE_SERVICE_ONGOING = 0x30, 263 FUS_STATE_VALUE_SERVICE_ONGOING_END = 0x3F, /* All values between 0x30 and 0x3F has the same meaning */ 264 FUS_STATE_VALUE_ERROR = 0xFF, 265 }; 266 267 #define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1) 268 /** No command parameters */ 269 /** No response parameters*/ 270 271 #define SHCI_OPCODE_C2_FUS_FW_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE) 272 /** No structure for command parameters */ 273 /** No response parameters*/ 274 275 #define SHCI_OPCODE_C2_FUS_FW_DELETE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE) 276 /** No command parameters */ 277 /** No response parameters*/ 278 279 #define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY) 280 typedef PACKED_STRUCT{ 281 uint8_t KeySize; 282 uint8_t KeyData[64]; 283 } SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t; 284 285 /** No response parameters*/ 286 287 #define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY) 288 /** No command parameters */ 289 /** No response parameters*/ 290 291 #define SHCI_OPCODE_C2_FUS_STORE_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY) 292 /** Command parameters */ 293 /* List of supported key type */ 294 enum 295 { 296 KEYTYPE_NONE = 0x00, 297 KEYTYPE_SIMPLE = 0x01, 298 KEYTYPE_MASTER = 0x02, 299 KEYTYPE_ENCRYPTED = 0x03, 300 }; 301 302 /* List of supported key size */ 303 enum 304 { 305 KEYSIZE_16 = 16, 306 KEYSIZE_32 = 32, 307 }; 308 309 typedef PACKED_STRUCT{ 310 uint8_t KeyType; 311 uint8_t KeySize; 312 uint8_t KeyData[32 + 12]; 313 } SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t; 314 315 /** Response parameters*/ 316 /** It responds a 1 byte value holding the index given for the stored key */ 317 318 #define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY) 319 /** Command parameters */ 320 /** 1 byte holding the key index value */ 321 322 /** No response parameters*/ 323 324 #define SHCI_OPCODE_C2_FUS_START_WS (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS) 325 /** No command parameters */ 326 /** No response parameters*/ 327 328 #define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2) 329 /** No command parameters */ 330 /** No response parameters*/ 331 332 #define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3) 333 /** No command parameters */ 334 /** No response parameters*/ 335 336 #define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY) 337 /** Command parameters */ 338 /** 1 byte holding the key index value */ 339 340 /** No response parameters*/ 341 342 #define SHCI_OPCODE_C2_FUS_UNLOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UNLOAD_USR_KEY) 343 /** No command parameters */ 344 /** 1 byte holding the key index value */ 345 346 #define SHCI_OPCODE_C2_FUS_ACTIVATE_ANTIROLLBACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK) 347 /** No command parameters */ 348 /** No response parameters*/ 349 350 #define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7) 351 /** No command parameters */ 352 /** No response parameters*/ 353 354 #define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8) 355 /** No command parameters */ 356 /** No response parameters*/ 357 358 #define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9) 359 /** No command parameters */ 360 /** No response parameters*/ 361 362 #define SHCI_OPCODE_C2_FUS_RESERVED10 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10) 363 /** No command parameters */ 364 /** No response parameters*/ 365 366 #define SHCI_OPCODE_C2_FUS_RESERVED11 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11) 367 /** No command parameters */ 368 /** No response parameters*/ 369 370 #define SHCI_OPCODE_C2_FUS_RESERVED12 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12) 371 /** No command parameters */ 372 /** No response parameters*/ 373 374 #define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT) 375 /** THE ORDER SHALL NOT BE CHANGED */ 376 typedef PACKED_STRUCT{ 377 uint8_t* pBleBufferAddress; /**< NOT USED - shall be set to 0 */ 378 uint32_t BleBufferSize; /**< NOT USED - shall be set to 0 */ 379 380 /** 381 * NumAttrRecord 382 * Maximum number of attribute records related to all the required characteristics (excluding the services) 383 * that can be stored in the GATT database, for the specific BLE user application. 384 * For each characteristic, the number of attribute records goes from two to five depending on the characteristic properties: 385 * - minimum of two (one for declaration and one for the value) 386 * - add one more record for each additional property: notify or indicate, broadcast, extended property. 387 * The total calculated value must be increased by 9, due to the records related to the standard attribute profile and 388 * GAP service characteristics, and automatically added when initializing GATT and GAP layers 389 * - Min value: <number of user attributes> + 9 390 * - Max value: depending on the GATT database defined by user application 391 */ 392 uint16_t NumAttrRecord; 393 394 /** 395 * NumAttrServ 396 * Defines the maximum number of services that can be stored in the GATT database. Note that the GAP and GATT services 397 * are automatically added at initialization so this parameter must be the number of user services increased by two. 398 * - Min value: <number of user service> + 2 399 * - Max value: depending GATT database defined by user application 400 */ 401 uint16_t NumAttrServ; 402 403 /** 404 * AttrValueArrSize 405 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 406 * 407 * Size of the storage area for the attribute values. 408 * Each characteristic contributes to the attrValueArrSize value as follows: 409 * - Characteristic value length plus: 410 * + 5 bytes if characteristic UUID is 16 bits 411 * + 19 bytes if characteristic UUID is 128 bits 412 * + 2 bytes if characteristic has a server configuration descriptor 413 * + 2 bytes * NumOfLinks if the characteristic has a client configuration descriptor 414 * + 2 bytes if the characteristic has extended properties 415 * Each descriptor contributes to the attrValueArrSize value as follows: 416 * - Descriptor length 417 */ 418 uint16_t AttrValueArrSize; 419 420 /** 421 * NumOfLinks 422 * Maximum number of BLE links supported 423 * - Min value: 1 424 * - Max value: 8 425 */ 426 uint8_t NumOfLinks; 427 428 /** 429 * ExtendedPacketLengthEnable 430 * Disable/enable the extended packet length BLE 5.0 feature 431 * - Disable: 0 432 * - Enable: 1 433 */ 434 uint8_t ExtendedPacketLengthEnable; 435 436 /** 437 * PrWriteListSize 438 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 439 * 440 * Maximum number of supported "prepare write request" 441 * - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE 442 * - Max value: a value higher than the minimum required can be specified, but it is not recommended 443 */ 444 uint8_t PrWriteListSize; 445 446 /** 447 * MblockCount 448 * NOTE: This parameter is overwritten by the CPU2 with an hardcoded optimal value when the parameter "Options" is set to "LL_only" 449 * ( see Options description in that structure ) 450 * 451 * Number of allocated memory blocks for the BLE stack 452 * - Min value: given by the macro MBLOCKS_CALC 453 * - Max value: a higher value can improve data throughput performance, but uses more memory 454 */ 455 uint8_t MblockCount; 456 457 /** 458 * AttMtu 459 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 460 * 461 * Maximum ATT MTU size supported 462 * - Min value: 23 463 * - Max value: 512 464 */ 465 uint16_t AttMtu; 466 467 /** 468 * PeripheralSca 469 * The sleep clock accuracy (ppm value) that used in BLE connected Peripheral mode to calculate the window widening 470 * (in combination with the sleep clock accuracy sent by master in CONNECT_REQ PDU), 471 * refer to BLE 5.0 specifications - Vol 6 - Part B - chap 4.5.7 and 4.2.2 472 * - Min value: 0 473 * - Max value: 500 (worst possible admitted by specification) 474 */ 475 uint16_t PeripheralSca; 476 477 /** 478 * CentralSca 479 * The sleep clock accuracy handled in Central mode. It is used to determine the connection and advertising events timing. 480 * It is transmitted to the slave in CONNEC_REQ PDU used by the slave to calculate the window widening, 481 * see PeripheralSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2 482 * Possible values: 483 * - 251 ppm to 500 ppm: 0 484 * - 151 ppm to 250 ppm: 1 485 * - 101 ppm to 150 ppm: 2 486 * - 76 ppm to 100 ppm: 3 487 * - 51 ppm to 75 ppm: 4 488 * - 31 ppm to 50 ppm: 5 489 * - 21 ppm to 30 ppm: 6 490 * - 0 ppm to 20 ppm: 7 491 */ 492 uint8_t CentralSca; 493 494 /** 495 * LsSource 496 * Some information for Low speed clock mapped in bits field 497 * - bit 0: 1: Calibration for the RF system wakeup clock source 0: No calibration for the RF system wakeup clock source 498 * - bit 1: 1: STM32W5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module 499 * - bit 2: 1: HSE/1024 Clock config 0: LSE Clock config 500 */ 501 uint8_t LsSource; 502 503 /** 504 * MaxConnEventLength 505 * This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes 506 * the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command), 507 * expressed in units of 625/256 us (~2.44 us) 508 * - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event) 509 * - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time 510 * of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened 511 */ 512 uint32_t MaxConnEventLength; 513 514 /** 515 * HsStartupTime 516 * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us). 517 * - Min value: 0 518 * - Max value: 820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms 519 */ 520 uint16_t HsStartupTime; 521 522 /** 523 * ViterbiEnable 524 * Viterbi implementation in BLE LL reception. 525 * - 0: Enable 526 * - 1: Disable 527 */ 528 uint8_t ViterbiEnable; 529 530 /** 531 * Options flags 532 * - bit 0: 1: LL only 0: LL + host 533 * - bit 1: 1: no service change desc. 0: with service change desc. 534 * - bit 2: 1: device name Read-Only 0: device name R/W 535 * - bit 3: 1: extended advertizing supported 0: extended advertizing not supported 536 * - bit 4: 1: CS Algo #2 supported 0: CS Algo #2 not supported 537 * - bit 5: 1: Reduced GATT database in NVM 0: Full GATT database in NVM 538 * - bit 6: 1: GATT caching is used 0: GATT caching is not used 539 * - bit 7: 1: LE Power Class 1 0: LE Power Class 2-3 540 * - other bits: complete with Options_extension flag 541 */ 542 uint8_t Options; 543 544 /** 545 * HwVersion 546 * Reserved for future use - shall be set to 0 547 */ 548 uint8_t HwVersion; 549 550 /** 551 * Maximum number of connection-oriented channels in initiator mode. 552 * Range: 0 .. 64 553 */ 554 uint8_t max_coc_initiator_nbr; 555 556 /** 557 * Minimum transmit power in dBm supported by the Controller. 558 * Range: -127 .. 20 559 */ 560 int8_t min_tx_power; 561 562 /** 563 * Maximum transmit power in dBm supported by the Controller. 564 * Range: -127 .. 20 565 */ 566 int8_t max_tx_power; 567 568 /** 569 * RX model configuration 570 * - bit 0: 1: agc_rssi model improved vs RF blockers 0: Legacy agc_rssi model 571 * - other bits: reserved ( shall be set to 0) 572 */ 573 uint8_t rx_model_config; 574 575 /* Maximum number of advertising sets. 576 * Range: 1 .. 8 with limitation: 577 * This parameter is linked to max_adv_data_len such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 578 * on Max Extended advertising configuration supported. 579 * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 580 */ 581 uint8_t max_adv_set_nbr; 582 583 /* Maximum advertising data length (in bytes) 584 * Range: 31 .. 1650 with limitation: 585 * This parameter is linked to max_adv_set_nbr such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 586 * on Max Extended advertising configuration supported. 587 * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 588 */ 589 uint16_t max_adv_data_len; 590 591 /* RF TX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 592 * Range: -1280 .. 1280 593 */ 594 int16_t tx_path_compens; 595 596 /* RF RX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 597 * Range: -1280 .. 1280 598 */ 599 int16_t rx_path_compens; 600 601 /* BLE core specification version (8-bit unsigned integer). 602 * values as: 11(5.2), 12(5.3), 13(5.4) 603 */ 604 uint8_t ble_core_version; 605 606 /** 607 * Options flags extension 608 * - bit 0: 1: appearance Writable 0: appearance Read-Only 609 * - bit 1: 1: Enhanced ATT supported 0: Enhanced ATT not supported 610 * - other bits: reserved ( shall be set to 0) 611 */ 612 uint8_t Options_extension; 613 614 } SHCI_C2_Ble_Init_Cmd_Param_t; 615 616 typedef PACKED_STRUCT{ 617 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 618 SHCI_C2_Ble_Init_Cmd_Param_t Param; 619 } SHCI_C2_Ble_Init_Cmd_Packet_t; 620 621 /** 622 * Options 623 * Each definition below may be added together to build the Options value 624 * WARNING : Only one definition per bit shall be added to build the Options value 625 */ 626 #define SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY (1<<0) 627 #define SHCI_C2_BLE_INIT_OPTIONS_LL_HOST (0<<0) 628 629 #define SHCI_C2_BLE_INIT_OPTIONS_NO_SVC_CHANGE_DESC (1<<1) 630 #define SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC (0<<1) 631 632 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO (1<<2) 633 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW (0<<2) 634 635 #define SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV (1<<3) 636 #define SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV (0<<3) 637 638 #define SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2 (1<<4) 639 #define SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 (0<<4) 640 641 #define SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM (1<<5) 642 #define SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM (0<<5) 643 644 #define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED (1<<6) 645 #define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED (0<<6) 646 647 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1 (1<<7) 648 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3 (0<<7) 649 650 /** 651 * Options extension 652 * Each definition below may be added together to build the Options value 653 * WARNING : Only one definition per bit shall be added to build the Options value 654 */ 655 #define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE (1<<0) 656 #define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY (0<<0) 657 658 #define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED (1<<1) 659 #define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED (0<<1) 660 661 /** 662 * RX models configuration 663 */ 664 #define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_LEGACY (0<<0) 665 #define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_BLOCKER (1<<0) 666 667 /** 668 * BLE core version 669 */ 670 #define SHCI_C2_BLE_INIT_BLE_CORE_5_2 11 671 #define SHCI_C2_BLE_INIT_BLE_CORE_5_3 12 672 #define SHCI_C2_BLE_INIT_BLE_CORE_5_4 13 673 674 /** 675 * LsSource information 676 */ 677 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB (0<<0) 678 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CALIB (1<<0) 679 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV (0<<1) 680 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV (1<<1) 681 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE (0<<2) 682 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_HSE_1024 (1<<2) 683 684 #define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT) 685 /** No command parameters */ 686 /** No response parameters*/ 687 688 #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT) 689 /** Command parameters */ 690 typedef PACKED_STRUCT 691 { 692 uint8_t thread_config; 693 uint8_t ble_config; 694 uint8_t mac_802_15_4_config; 695 uint8_t zigbee_config; 696 } SHCI_C2_DEBUG_TracesConfig_t; 697 698 typedef PACKED_STRUCT 699 { 700 uint8_t ble_dtb_cfg; 701 /** 702 * sys_dbg_cfg1 options flag 703 * - bit 0: 0: IP BLE core in LP mode 1: IP BLE core in run mode (no LP supported) 704 * - bit 1: 0: CPU2 STOP mode Enable 1: CPU2 STOP mode Disable 705 * - bit [2-7]: bits reserved ( shall be set to 0) 706 */ 707 uint8_t sys_dbg_cfg1; 708 uint8_t reserved[2]; 709 uint16_t STBY_DebugGpioaPinList; 710 uint16_t STBY_DebugGpiobPinList; 711 uint16_t STBY_DebugGpiocPinList; 712 uint16_t STBY_DtbGpioaPinList; 713 uint16_t STBY_DtbGpiobPinList; 714 } SHCI_C2_DEBUG_GeneralConfig_t; 715 716 typedef PACKED_STRUCT{ 717 uint8_t *pGpioConfig; 718 uint8_t *pTracesConfig; 719 uint8_t *pGeneralConfig; 720 uint8_t GpioConfigSize; 721 uint8_t TracesConfigSize; 722 uint8_t GeneralConfigSize; 723 } SHCI_C2_DEBUG_init_Cmd_Param_t; 724 725 typedef PACKED_STRUCT{ 726 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 727 SHCI_C2_DEBUG_init_Cmd_Param_t Param; 728 } SHCI_C2_DEBUG_Init_Cmd_Packet_t; 729 /** No response parameters*/ 730 731 /** 732 * Options 733 * Each definition below may be added together to build the Options value 734 * WARNING : Only one definition per bit shall be added to build the Options value 735 */ 736 #define SHCI_C2_DEBUG_OPTIONS_IPCORE_LP (0<<0) 737 #define SHCI_C2_DEBUG_OPTIONS_IPCORE_NO_LP (1<<0) 738 739 #define SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_EN (0<<1) 740 #define SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_DIS (1<<1) 741 742 743 #define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY) 744 /** Command parameters */ 745 typedef enum 746 { 747 ERASE_ACTIVITY_OFF = 0x00, 748 ERASE_ACTIVITY_ON = 0x01, 749 } SHCI_EraseActivity_t; 750 751 /** No response parameters*/ 752 753 #define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE) 754 /** command parameters */ 755 typedef enum 756 { 757 BLE_ENABLE, 758 THREAD_ENABLE, 759 ZIGBEE_ENABLE, 760 MAC_ENABLE, 761 } SHCI_C2_CONCURRENT_Mode_Param_t; 762 /** No response parameters*/ 763 764 #define SHCI_OPCODE_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME) 765 /** command parameters */ 766 typedef PACKED_STRUCT 767 { 768 uint32_t relative_time; 769 } SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t; 770 /** No response parameters*/ 771 772 #define SHCI_OPCODE_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION) 773 /** No command parameters */ 774 /** No response parameters*/ 775 776 #define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA) 777 #define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA) 778 /** command parameters */ 779 typedef enum 780 { 781 BLE_IP, 782 THREAD_IP, 783 ZIGBEE_IP, 784 } SHCI_C2_FLASH_Ip_t; 785 /** No response parameters*/ 786 787 #define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER) 788 789 #define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_MAC_802_15_4_INIT) 790 791 #define SHCI_OPCODE_C2_REINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_REINIT) 792 793 #define SHCI_OPCODE_C2_ZIGBEE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_ZIGBEE_INIT) 794 795 #define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT) 796 797 #define SHCI_OPCODE_C2_BLE_LLD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_LLD_INIT) 798 799 #define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG) 800 /** Command parameters */ 801 enum 802 { 803 EXT_PA_ENABLED_LOW, 804 EXT_PA_ENABLED_HIGH, 805 }/* gpio_polarity */; 806 807 enum 808 { 809 EXT_PA_DISABLED, 810 EXT_PA_ENABLED, 811 }/* gpio_status */; 812 813 typedef PACKED_STRUCT{ 814 uint32_t gpio_port; 815 uint16_t gpio_pin_number; 816 uint8_t gpio_polarity; 817 uint8_t gpio_status; 818 } SHCI_C2_EXTPA_CONFIG_Cmd_Param_t; 819 820 /** No response parameters*/ 821 822 #define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL) 823 /** Command parameters */ 824 typedef enum 825 { 826 FLASH_ACTIVITY_CONTROL_PES, 827 FLASH_ACTIVITY_CONTROL_SEM7, 828 }SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t; 829 830 /** No response parameters*/ 831 832 #define SHCI_OPCODE_C2_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG) 833 834 /** Command parameters */ 835 typedef PACKED_STRUCT{ 836 uint8_t PayloadCmdSize; 837 uint8_t Config1; 838 uint8_t EvtMask1; 839 uint8_t Spare1; 840 uint32_t BleNvmRamAddress; 841 uint32_t ThreadNvmRamAddress; 842 uint16_t RevisionID; 843 uint16_t DeviceID; 844 } SHCI_C2_CONFIG_Cmd_Param_t; 845 846 #define SHCI_OPCODE_C2_802_15_4_DEINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT) 847 848 #define SHCI_OPCODE_C2_SET_SYSTEM_CLOCK (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_SYSTEM_CLOCK) 849 /** Command parameters */ 850 typedef enum 851 { 852 SET_SYSTEM_CLOCK_HSE_TO_PLL, 853 SET_SYSTEM_CLOCK_PLL_ON_TO_HSE, 854 SET_SYSTEM_CLOCK_PLL_OFF_TO_HSE, 855 }SHCI_C2_SET_SYSTEM_CLOCK_Cmd_Param_t; 856 857 /** 858 * PayloadCmdSize 859 * Value that shall be used 860 */ 861 #define SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE (sizeof(SHCI_C2_CONFIG_Cmd_Param_t) - 1) 862 863 /** 864 * Device revision ID 865 */ 866 #define SHCI_C2_CONFIG_CUT2_0 (0x2000) 867 #define SHCI_C2_CONFIG_CUT2_1 (0x2001) 868 #define SHCI_C2_CONFIG_CUT2_2 (0x2003) 869 870 /** 871 * Device ID 872 */ 873 #define SHCI_C2_CONFIG_STM32WB55xx (0x495) 874 #define SHCI_C2_CONFIG_STM32WB15xx (0x494) 875 876 /** 877 * Config1 878 * Each definition below may be added together to build the Config1 value 879 * WARNING : Only one definition per bit shall be added to build the Config1 value 880 */ 881 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_INTERNAL_FLASH (0<<0) 882 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_SRAM (1<<0) 883 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_INTERNAL_FLASH (0<<1) 884 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_SRAM (1<<1) 885 #define SHCI_C2_CONFIG_CONFIG1_BIT2_SET_EUI64_FORMAT (1<<2) 886 887 /** 888 * EvtMask1 889 * Each definition below may be added together to build the EvtMask1 value 890 */ 891 #define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE (1<<0) 892 #define SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE (1<<1) 893 #define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE (1<<2) 894 #define SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE (1<<3) 895 #define SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE (1<<4) 896 #define SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE (1<<5) 897 #define SHCI_C2_CONFIG_EVTMASK1_BIT6_NVM_END_ERASE_ENABLE (1<<6) 898 899 /** 900 * BleNvmRamAddress 901 * The buffer shall have a size of BLE_NVM_SRAM_SIZE number of 32bits 902 * The buffer shall be allocated in SRAM2 903 */ 904 #define BLE_NVM_SRAM_SIZE (507) 905 906 /** 907 * ThreadNvmRamAddress 908 * The buffer shall have a size of THREAD_NVM_SRAM_SIZE number of 32bits 909 * The buffer shall be allocated in SRAM2 910 */ 911 #define THREAD_NVM_SRAM_SIZE (1016) 912 913 914 /** No response parameters*/ 915 916 /* Exported type --------------------------------------------------------*/ 917 #define FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD (0xA94656B9) 918 919 /* 920 * At startup, the information relative to the wireless binary are stored in RAM through a structure defined by 921 * MB_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part) 922 * each of those coded on 32 bits as shown on the table below: 923 * 924 * 925 * |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 | 926 * ------------------------------------------------------------------------------------------------- 927 * Version | Major version | Minor version | Sub version | Branch |ReleaseType| 928 * ------------------------------------------------------------------------------------------------- 929 * MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) | 930 * ------------------------------------------------------------------------------------------------- 931 * Info stack | Reserved | Reserved | Reserved | Type (MAC,Thread,BLE) | 932 * ------------------------------------------------------------------------------------------------- 933 * Reserved | Reserved | Reserved | Reserved | Reserved | 934 * ------------------------------------------------------------------------------------------------- 935 * 936 */ 937 938 /* Field Version */ 939 #define INFO_VERSION_MAJOR_OFFSET 24 940 #define INFO_VERSION_MAJOR_MASK 0xff000000 941 #define INFO_VERSION_MINOR_OFFSET 16 942 #define INFO_VERSION_MINOR_MASK 0x00ff0000 943 #define INFO_VERSION_SUB_OFFSET 8 944 #define INFO_VERSION_SUB_MASK 0x0000ff00 945 #define INFO_VERSION_BRANCH_OFFSET 4 946 #define INFO_VERSION_BRANCH_MASK 0x0000000f0 947 #define INFO_VERSION_TYPE_OFFSET 0 948 #define INFO_VERSION_TYPE_MASK 0x00000000f 949 950 #define INFO_VERSION_TYPE_RELEASE 1 951 952 /* Field Memory */ 953 #define INFO_SIZE_SRAM2B_OFFSET 24 954 #define INFO_SIZE_SRAM2B_MASK 0xff000000 955 #define INFO_SIZE_SRAM2A_OFFSET 16 956 #define INFO_SIZE_SRAM2A_MASK 0x00ff0000 957 #define INFO_SIZE_SRAM1_OFFSET 8 958 #define INFO_SIZE_SRAM1_MASK 0x0000ff00 959 #define INFO_SIZE_FLASH_OFFSET 0 960 #define INFO_SIZE_FLASH_MASK 0x000000ff 961 962 /* Field stack information */ 963 #define INFO_STACK_TYPE_OFFSET 0 964 #define INFO_STACK_TYPE_MASK 0x000000ff 965 #define INFO_STACK_TYPE_NONE 0 966 967 #define INFO_STACK_TYPE_BLE_FULL 0x01 968 #define INFO_STACK_TYPE_BLE_HCI 0x02 969 #define INFO_STACK_TYPE_BLE_LIGHT 0x03 970 #define INFO_STACK_TYPE_BLE_BEACON 0x04 971 #define INFO_STACK_TYPE_BLE_BASIC 0x05 972 #define INFO_STACK_TYPE_BLE_FULL_EXT_ADV 0x06 973 #define INFO_STACK_TYPE_BLE_HCI_EXT_ADV 0x07 974 #define INFO_STACK_TYPE_THREAD_FTD 0x10 975 #define INFO_STACK_TYPE_THREAD_MTD 0x11 976 #define INFO_STACK_TYPE_ZIGBEE_FFD 0x30 977 #define INFO_STACK_TYPE_ZIGBEE_RFD 0x31 978 #define INFO_STACK_TYPE_MAC 0x40 979 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50 980 #define INFO_STACK_TYPE_BLE_THREAD_FTD_DYNAMIC 0x51 981 #define INFO_STACK_TYPE_BLE_THREAD_LIGHT_DYNAMIC 0x52 982 #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60 983 #define INFO_STACK_TYPE_802154_PHY_VALID 0x61 984 #define INFO_STACK_TYPE_BLE_PHY_VALID 0x62 985 #define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63 986 #define INFO_STACK_TYPE_BLE_RLV 0x64 987 #define INFO_STACK_TYPE_802154_RLV 0x65 988 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70 989 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_STATIC 0x71 990 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_DYNAMIC 0x78 991 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_DYNAMIC 0x79 992 #define INFO_STACK_TYPE_RLV 0x80 993 #define INFO_STACK_TYPE_BLE_MAC_STATIC 0x90 994 995 typedef struct { 996 /** 997 * Wireless Info 998 */ 999 uint8_t VersionMajor; 1000 uint8_t VersionMinor; 1001 uint8_t VersionSub; 1002 uint8_t VersionBranch; 1003 uint8_t VersionReleaseType; 1004 uint8_t MemorySizeSram2B; /*< Multiple of 1K */ 1005 uint8_t MemorySizeSram2A; /*< Multiple of 1K */ 1006 uint8_t MemorySizeSram1; /*< Multiple of 1K */ 1007 uint8_t MemorySizeFlash; /*< Multiple of 4K */ 1008 uint8_t StackType; 1009 /** 1010 * Fus Info 1011 */ 1012 uint8_t FusVersionMajor; 1013 uint8_t FusVersionMinor; 1014 uint8_t FusVersionSub; 1015 uint8_t FusMemorySizeSram2B; /*< Multiple of 1K */ 1016 uint8_t FusMemorySizeSram2A; /*< Multiple of 1K */ 1017 uint8_t FusMemorySizeFlash; /*< Multiple of 4K */ 1018 }WirelessFwInfo_t; 1019 1020 1021 /* Exported functions ------------------------------------------------------- */ 1022 1023 /** 1024 * SHCI_C2_FUS_GetState 1025 * @brief Read the FUS State 1026 * If the user is not interested by the Error code response, a null value may 1027 * be passed as parameter 1028 * 1029 * Note: This command is fully supported only by the FUS. 1030 * When the wireless firmware receives that command, it responds SHCI_FUS_CMD_NOT_SUPPORTED the first time. 1031 * When the wireless firmware receives that command a second time, it reboots the full device with the FUS running on CPU2 1032 * 1033 * @param p_rsp : return the error code when the FUS State Value = 0xFF 1034 * @retval FUS State Values 1035 */ 1036 uint8_t SHCI_C2_FUS_GetState( SHCI_FUS_GetState_ErrorCode_t *p_rsp ); 1037 1038 /** 1039 * SHCI_C2_FUS_FwUpgrade 1040 * @brief Request the FUS to install the CPU2 firmware update 1041 * Note: This command is only supported by the FUS. 1042 * 1043 * @param fw_src_add: Address of the firmware image location 1044 * @param fw_dest_add: Address of the firmware destination 1045 * @retval Status 1046 */ 1047 SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade( uint32_t fw_src_add, uint32_t fw_dest_add ); 1048 1049 /** 1050 * SHCI_C2_FUS_FwDelete 1051 * @brief Delete the wireless stack on CPU2 1052 * Note: This command is only supported by the FUS. 1053 * 1054 * @param None 1055 * @retval Status 1056 */ 1057 SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete( void ); 1058 1059 /** 1060 * SHCI_C2_FUS_UpdateAuthKey 1061 * @brief Request the FUS to update the authentication key 1062 * Note: This command is only supported by the FUS. 1063 * 1064 * @param pCmdPacket 1065 * @retval Status 1066 */ 1067 SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam ); 1068 1069 /** 1070 * SHCI_C2_FUS_LockAuthKey 1071 * @brief Request the FUS to prevent any future update of the authentication key 1072 * Note: This command is only supported by the FUS. 1073 * 1074 * @param None 1075 * @retval Status 1076 */ 1077 SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey( void ); 1078 1079 /** 1080 * SHCI_C2_FUS_StoreUsrKey 1081 * @brief Request the FUS to store the user key 1082 * Note: This command is supported by both the FUS and the wireless stack. 1083 * 1084 * @param pParam : command parameter 1085 * @param p_key_index : Index allocated by the FUS to the stored key 1086 * 1087 * @retval Status 1088 */ 1089 SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index ); 1090 1091 /** 1092 * SHCI_C2_FUS_LoadUsrKey 1093 * @brief Request the FUS to load the user key into the AES 1094 * Note: This command is supported by both the FUS and the wireless stack. 1095 * 1096 * @param key_index : index of the user key to load in AES1 1097 * @retval Status 1098 */ 1099 SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey( uint8_t key_index ); 1100 1101 /** 1102 * SHCI_C2_FUS_StartWs 1103 * @brief Request the FUS to reboot on the wireless stack 1104 * Note: This command is only supported by the FUS. 1105 * 1106 * @param None 1107 * @retval Status 1108 */ 1109 SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void ); 1110 1111 /** 1112 * SHCI_C2_FUS_LockUsrKey 1113 * @brief Request the FUS to lock the user key so that it cannot be updated later on 1114 * Note: This command is supported by both the FUS and the wireless stack. 1115 * 1116 * @param key_index : index of the user key to lock 1117 * @retval Status 1118 */ 1119 SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index ); 1120 1121 /** 1122 * SHCI_C2_FUS_UnloadUsrKey 1123 * @brief Request the FUS to Unload the user key so that the CPU1 may use the AES with another Key 1124 * Note: This command is supported by both the FUS and the wireless stack. 1125 * 1126 * @param key_index : index of the user key to unload 1127 * @retval Status 1128 */ 1129 SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey( uint8_t key_index ); 1130 1131 /** 1132 * SHCI_C2_FUS_ActivateAntiRollback 1133 * @brief Request the FUS to enable the AntiRollback feature so that it is not possible to update the wireless firmware 1134 * with an older version than the current one. 1135 * Note: 1136 * - This command is only supported by the FUS. 1137 * - Once this feature is enabled, it is not possible anymore to disable it. 1138 * 1139 * @param None 1140 * @retval Status 1141 */ 1142 SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback( void ); 1143 1144 /** 1145 * SHCI_C2_BLE_Init 1146 * @brief Provides parameters and starts the BLE Stack 1147 * 1148 * @param pCmdPacket : Parameters are described SHCI_C2_Ble_Init_Cmd_Packet_t declaration 1149 * @retval Status 1150 */ 1151 SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket ); 1152 1153 /** 1154 * SHCI_C2_THREAD_Init 1155 * @brief Starts the THREAD Stack 1156 * 1157 * @param None 1158 * @retval Status 1159 */ 1160 SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void ); 1161 1162 /** 1163 * SHCI_C2_LLDTESTS_Init 1164 * @brief Starts the LLD tests CLI 1165 * 1166 * @param param_size : Nb of bytes 1167 * @param p_param : pointer with data to give from M4 to M0 1168 * @retval Status 1169 */ 1170 SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param ); 1171 1172 /** 1173 * SHCI_C2_BLE_LLD_Init 1174 * @brief Starts the LLD tests BLE 1175 * 1176 * @param param_size : Nb of bytes 1177 * @param p_param : pointer with data to give from M4 to M0 1178 * @retval Status 1179 */ 1180 SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init( uint8_t param_size, uint8_t * p_param ); 1181 1182 /** 1183 * SHCI_C2_ZIGBEE_Init 1184 * @brief Starts the Zigbee Stack 1185 * 1186 * @param None 1187 * @retval Status 1188 */ 1189 SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void ); 1190 1191 /** 1192 * SHCI_C2_DEBUG_Init 1193 * @brief Starts the Traces 1194 * 1195 * @param None 1196 * @retval Status 1197 */ 1198 SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ); 1199 1200 /** 1201 * SHCI_C2_FLASH_EraseActivity 1202 * @brief Provides the information of the start and the end of a flash erase window on the CPU1 1203 * The protection will be active until next end of radio event. 1204 * 1205 * @param erase_activity: Start/End of erase activity 1206 * @retval Status 1207 */ 1208 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity( SHCI_EraseActivity_t erase_activity ); 1209 1210 /** 1211 * SHCI_C2_CONCURRENT_SetMode 1212 * @brief Enable/Disable Thread on CPU2 (M0+) 1213 * 1214 * @param Mode: BLE or Thread enable flag 1215 * @retval Status 1216 */ 1217 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode ); 1218 1219 /** 1220 * SHCI_C2_CONCURRENT_GetNextBleEvtTime 1221 * @brief Get the next BLE event date (relative time) 1222 * 1223 * @param Command Packet 1224 * @retval None 1225 */ 1226 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime( SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam ); 1227 1228 /** 1229 * SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification 1230 * @brief Activate the next 802.15.4 event notification (one shot) 1231 * 1232 * @param None 1233 * @retval None 1234 */ 1235 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification( void ); 1236 1237 /** 1238 * SHCI_C2_FLASH_StoreData 1239 * @brief Store Data in Flash 1240 * 1241 * @param Ip: BLE or THREAD 1242 * @retval Status 1243 */ 1244 SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip ); 1245 1246 /** 1247 * SHCI_C2_FLASH_EraseData 1248 * @brief Erase Data in Flash 1249 * 1250 * @param Ip: BLE or THREAD 1251 * @retval Status 1252 */ 1253 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip ); 1254 1255 /** 1256 * SHCI_C2_RADIO_AllowLowPower 1257 * @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode. 1258 * 1259 * @param Ip: BLE or 802_15_5 1260 * @param FlagRadioLowPowerOn: True or false 1261 * @retval Status 1262 */ 1263 SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn); 1264 1265 1266 /** 1267 * SHCI_C2_MAC_802_15_4_Init 1268 * @brief Starts the MAC 802.15.4 on M0 1269 * 1270 * @param None 1271 * @retval Status 1272 */ 1273 SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void ); 1274 1275 /** 1276 * SHCI_GetWirelessFwInfo 1277 * @brief This function read back the information relative to the wireless binary loaded. 1278 * Refer yourself to MB_WirelessFwInfoTable_t structure to get the significance 1279 * of the different parameters returned. 1280 * @param pWirelessInfo : Pointer to WirelessFwInfo_t. 1281 * 1282 * @retval SHCI_Success 1283 */ 1284 SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ); 1285 1286 /** 1287 * SHCI_C2_Reinit 1288 * @brief This is required to allow the CPU1 to fake a set C2BOOT when it has already been set. 1289 * In order to fake a C2BOOT, the CPU1 shall : 1290 * - Send SHCI_C2_Reinit() 1291 * - call SEV instruction 1292 * WARNING: 1293 * This function is intended to be used by the SBSFU 1294 * 1295 * @param None 1296 * @retval Status 1297 */ 1298 SHCI_CmdStatus_t SHCI_C2_Reinit( void ); 1299 1300 /** 1301 * SHCI_C2_ExtpaConfig 1302 * @brief Send the Ext PA configuration 1303 * When the CPU2 receives the command, it controls the Ext PA as requested by the configuration 1304 * This configures only which IO is used to enable/disable the ExtPA and the associated polarity 1305 * This command has no effect on the other IO that is used to control the mode of the Ext PA (Rx/Tx) 1306 * 1307 * @param gpio_port: GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family 1308 * @param gpio_pin_number: This parameter can be one of GPIO_PIN_x (= LL_GPIO_PIN_x) where x can be (0..15). 1309 * @param gpio_polarity: This parameter can be either 1310 * - EXT_PA_ENABLED_LOW: ExtPA is enabled when GPIO is low 1311 * - EXT_PA_ENABLED_HIGH: ExtPA is enabled when GPIO is high 1312 * @param gpio_status: This parameter can be either 1313 * - EXT_PA_DISABLED: Stop driving the ExtPA 1314 * - EXT_PA_ENABLED: Drive the ExtPA according to radio activity 1315 * (ON before the Event and OFF at the end of the event) 1316 * @retval Status 1317 */ 1318 SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status); 1319 1320 /** 1321 * SHCI_C2_SetFlashActivityControl 1322 * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash 1323 * 1324 * @param Source: It can be one of the following list 1325 * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash 1326 * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash. 1327 * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash. 1328 * 1329 * @retval Status 1330 */ 1331 SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source); 1332 1333 /** 1334 * SHCI_C2_Config 1335 * @brief Send the system configuration to the CPU2 1336 * 1337 * @param pCmdPacket: address of the buffer holding following parameters 1338 * uint8_t PayloadCmdSize : Size of the payload - shall be SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE 1339 * uint8_t Config1 : 1340 * - bit0 : 0 - BLE NVM Data data are flushed in internal secure flash 1341 * 1 - BLE NVM Data are written in SRAM cache pointed by BleNvmRamAddress 1342 * - bit1 : 0 - THREAD NVM Data data are flushed in internal secure flash 1343 * 1 - THREAD NVM Data are written in SRAM cache pointed by ThreadNvmRamAddress 1344 * - bit2 : 0 - Thread EUI64 is set to new (and current) format 1345 * 1 - Thread EUI64 is set to old format 1346 * - bit3 to bit7 : Unused, shall be set to 0 1347 * uint8_t EvtMask1 : 1348 * When a bit is set to 0, the event is not reported 1349 * bit0 : Asynchronous Event with Sub Evt Code 0x9201 (= SHCI_SUB_EVT_ERROR_NOTIF) 1350 * ... 1351 * bit31 : Asynchronous Event with Sub Evt Code 0x9220 1352 * uint8_t Spare1 : Unused, shall be set to 0 1353 * uint32_t BleNvmRamAddress : 1354 * Only considered when Config1.bit0 = 1 1355 * When set to 0, data are kept in internal SRAM on CPU2 1356 * Otherwise, data are copied in the cache pointed by BleNvmRamAddress 1357 * The size of the buffer shall be BLE_NVM_SRAM_SIZE (number of 32bits) 1358 * The buffer shall be allocated in SRAM2 1359 * uint32_t ThreadNvmRamAddress : 1360 * Only considered when Config1.bit1 = 1 1361 * When set to 0, data are kept in internal SRAM on CPU2 1362 * Otherwise, data are copied in the cache pointed by ThreadNvmRamAddress 1363 * The size of the buffer shall be THREAD_NVM_SRAM_SIZE (number of 32bits) 1364 * The buffer shall be allocated in SRAM1 1365 * 1366 * Please check macro definition to be used for this function 1367 * They are defined in this file next to the definition of SHCI_OPCODE_C2_CONFIG 1368 * 1369 * @retval Status 1370 */ 1371 SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket); 1372 1373 /** 1374 * SHCI_C2_802_15_4_DeInit 1375 * @brief Deinit 802.15.4 layer (to be used before entering StandBy mode) 1376 * 1377 * @param None 1378 * @retval Status 1379 */ 1380 SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void ); 1381 1382 /** 1383 * SHCI_C2_SetSystemClock 1384 * @brief Request CPU2 to change system clock 1385 * 1386 * @param clockSel: It can be one of the following list 1387 * - SET_SYSTEM_CLOCK_HSE_TO_PLL : CPU2 set system clock to PLL, PLL must be configured and started before. 1388 * - SET_SYSTEM_CLOCK_PLL_ON_TO_HSE : CPU2 set System clock to HSE, PLL is still ON after command execution. 1389 * - SET_SYSTEM_CLOCK_PLL_OFF_TO_HSE : CPU2 set System clock to HSE, PLL is turned OFF after command execution. 1390 * 1391 * @retval Status 1392 */ 1393 SHCI_CmdStatus_t SHCI_C2_SetSystemClock( SHCI_C2_SET_SYSTEM_CLOCK_Cmd_Param_t clockSel ); 1394 1395 1396 #ifdef __cplusplus 1397 } 1398 #endif 1399 1400 #endif /*__SHCI_H */ 1401 1402 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1403
