SET_BIT (reference) in projects: hal_stm32-latest

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Searched refs:SET_BIT (Results 1 – 25 of 1859) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
D	stm32u5xx_hal_rcc.h	677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 684 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 698 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 705 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 714 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ 723 … SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 730 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 738 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ 747 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ [all …]
D	stm32u5xx_hal.h	304 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STO… 309 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STO… 314 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STO… 319 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STO… 324 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STO… 329 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STO… 334 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STO… 339 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STO… 344 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_… 349 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_… [all …]
D	stm32u5xx_ll_ucpd.h	348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable() 464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterEnable() 486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable() 508 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable() 541 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable() 574 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); in LL_UCPD_TypeCDetectionCC2Disable() 596 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); in LL_UCPD_TypeCDetectionCC1Disable() 607 SET_BIT(UCPDx->CR, UCPD_CR_RDCH); in LL_UCPD_VconnDischargeEnable() 629 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); in LL_UCPD_SignalFRSTX() 640 SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); in LL_UCPD_FRSDetectionEnable() [all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
D	stm32h7rsxx_hal_rcc.h	761 #define __HAL_RCC_AXI_INTERCONNECT_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AXICK… 763 #define __HAL_RCC_AXI_MASTER_AHB_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_AHBCK… 765 #define __HAL_RCC_AXI_MASTER_SDMMC1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_SDMMC… 767 #define __HAL_RCC_AXI_MASTER_HPDMA1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_HPDMA… 769 #define __HAL_RCC_AXI_MASTER_CPU_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_CPUCK… 771 #define __HAL_RCC_AXI_MASTER_GPU_0_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D… 773 #define __HAL_RCC_AXI_MASTER_GPU_1_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D… 775 #define __HAL_RCC_AXI_MASTER_GPU_CACHE_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_GPU2D… 777 #define __HAL_RCC_AXI_MASTER_DCMIPP_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DCMIP… 779 #define __HAL_RCC_AXI_MASTER_DMA2D_CLK_GATING_DISABLE() SET_BIT(RCC->CKGDISR, RCC_CKGDISR_DMA2D… [all …]
D	stm32h7rsxx_hal.h	273 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_0) 276 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_1) 279 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_2) 282 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_3) 285 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_4) 288 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_5) 291 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_6) 294 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_7) 297 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_8) 300 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_GPDMA_9) [all …]
D	stm32h7rsxx_ll_ucpd.h	348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable() 464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterEnable() 486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable() 508 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable() 541 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable() 574 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); in LL_UCPD_TypeCDetectionCC2Disable() 596 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); in LL_UCPD_TypeCDetectionCC1Disable() 607 SET_BIT(UCPDx->CR, UCPD_CR_RDCH); in LL_UCPD_VconnDischargeEnable() 629 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); in LL_UCPD_SignalFRSTX() 640 SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); in LL_UCPD_FRSDetectionEnable() [all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
D	stm32h5xx_hal_rcc.h	734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA2EN); \ 751 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 761 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 770 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 778 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 786 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLITFEN); \ 795 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHEN);\ 803 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN);\ 811 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN);\ [all …]
D	stm32h5xx_hal.h	309 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STO… 314 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STO… 319 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STO… 324 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STO… 329 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STO… 334 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STO… 339 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_S… 344 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_S… 349 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_S… 354 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STO… [all …]
D	stm32h5xx_ll_ucpd.h	348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); in LL_UCPD_Enable() 464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); in LL_UCPD_RxAnalogFilterEnable() 486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); in LL_UCPD_WakeUpEnable() 508 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); in LL_UCPD_ForceClockEnable() 541 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); in LL_UCPD_RxFilterDisable() 574 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); in LL_UCPD_TypeCDetectionCC2Disable() 596 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); in LL_UCPD_TypeCDetectionCC1Disable() 607 SET_BIT(UCPDx->CR, UCPD_CR_RDCH); in LL_UCPD_VconnDischargeEnable() 629 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); in LL_UCPD_SignalFRSTX() 640 SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); in LL_UCPD_FRSDetectionEnable() [all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
D	stm32g4xx_hal_rcc.h	518 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 526 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 534 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 542 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ 550 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ 558 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 566 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 600 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 608 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 616 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
D	stm32l5xx_hal_rcc.h	654 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 662 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 670 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 677 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 685 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 693 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 701 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ 736 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
D	stm32l4xx_hal_rcc.h	639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 673 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 681 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ 700 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ 744 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 752 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
D	stm32wb0x_hal_pwr.h	427 … ((__FLAG__) == PWR_FLAG_DEEPSTOPF) ? (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF)) : \ 428 … ((__FLAG__) == PWR_FLAG_RFPHASEF) ? (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF)) : \ 429 … ((__FLAG__) == PWR_FLAG_WUF0) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF0)) : \ 430 … ((__FLAG__) == PWR_FLAG_WUF1) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF1)) : \ 431 … ((__FLAG__) == PWR_FLAG_WUF2) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF2)) : \ 432 … ((__FLAG__) == PWR_FLAG_WUF3) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF3)) : \ 433 … ((__FLAG__) == PWR_FLAG_WUF4) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF4)) : \ 434 … ((__FLAG__) == PWR_FLAG_WUF5) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF5)) : \ 435 … ((__FLAG__) == PWR_FLAG_WUF6) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF6)) : \ 436 … ((__FLAG__) == PWR_FLAG_WUF7) ? (SET_BIT(PWR->SR1, PWR_SR1_WUF7)) : \ [all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
D	stm32wbaxx_hal_rcc.h	570 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ 578 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 586 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 595 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 604 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ 613 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ 622 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ 652 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 660 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 668 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ [all …]
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
D	stm32l0xx_hal_rcc_ex.h	583 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\ 598 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ 610 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\ 635 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ 650 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ 674 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN)) 680 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN)) 690 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN)) 701 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN)) 702 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN)) [all …]
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
D	stm32u0xx_hal_rcc.h	`702 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 710 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 719 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 727 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 735 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN); \ 743 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 751 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 786 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 794 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 802 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ [all …]`
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
D	stm32g0xx_hal_rcc.h	`861 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 870 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ 881 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 889 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 898 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ 908 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ 941 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 949 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 957 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 965 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ [all …]`
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
D	stm32n6xx_hal.h	301 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM2_… 306 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM3_… 311 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM4_… 316 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM5_… 321 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM6_… 326 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM7_… 331 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM10… 336 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM11… 341 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM12… 346 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1LFZ1, DBGMCU_APB1LFZ1_DBG_TIM13… [all …]
D	stm32n6xx_hal_pwr_ex.h	227 #define __HAL_PWR_USBVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDUSB) 239 #define __HAL_PWR_USBVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDUSB) 251 #define __HAL_PWR_USBVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDUSB) 263 #define __HAL_PWR_USBVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDUSB) 297 #define __HAL_PWR_USBVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDUSB) 321 #define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVM_VDDIO2) 333 #define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVM_VDDIO2) 345 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVM_VDDIO2) 357 #define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVM_VDDIO2) 391 #define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVM_VDDIO2) [all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
D	stm32u5xx_hal_pwr_ex.c	358 SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); in HAL_PWREx_ControlVoltageScaling() 449 SET_BIT(PWR->CR3, PWR_CR3_REGSEL); in HAL_PWREx_ConfigSupply() 482 SET_BIT(PWR->CR3, PWR_CR3_FSTEN); in HAL_PWREx_EnableFastSoftStart() 662 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode() 711 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode() 761 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP3Mode() 799 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSHUTDOWNMode() 837 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); in HAL_PWREx_EnableUltraLowPowerMode() 864 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); in HAL_PWREx_S3WU_IRQHandler() 877 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); in HAL_PWREx_S3WU_IRQHandler() [all …]
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
D	stm32c0xx_hal_rcc.h	`698 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 706 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 714 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 739 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 747 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 755 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 763 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 771 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 799 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ 808 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ [all …]`
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
D	stm32mp1xx_hal.h	239 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 243 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 247 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 251 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 255 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 259 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 263 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STO… 267 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STO… 271 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STO… 275 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_S… [all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
D	stm32h7xx_hal_rcc.h	767 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ 775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ 784 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ 793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ 802 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ 811 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ 820 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ 829 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ 838 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ 847 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ [all …]
D	stm32h7xx_ll_bus.h	569 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock() 700 SET_BIT(RCC->AHB3RSTR, Periphs); in LL_AHB3_GRP1_ForceReset() 782 SET_BIT(RCC->AHB3LPENR, Periphs); in LL_AHB3_GRP1_EnableClockSleep() 875 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock() 978 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset() 1043 SET_BIT(RCC->AHB1LPENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep() 1127 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock() 1232 SET_BIT(RCC->AHB2RSTR, Periphs); in LL_AHB2_GRP1_ForceReset() 1297 SET_BIT(RCC->AHB2LPENR, Periphs); in LL_AHB2_GRP1_EnableClockSleep() 1387 SET_BIT(RCC->AHB4ENR, Periphs); in LL_AHB4_GRP1_EnableClock() [all …]
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
D	stm32f3xx_hal_adc_ex.c	335 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); in HAL_ADC_Init() 360 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init() 425 SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) \| in HAL_ADC_Init() 437 SET_BIT(tmpCFGR, ADC_CFGR_DISCEN \| in HAL_ADC_Init() 452 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init() 463 SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) \| in HAL_ADC_Init() 477 SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) \| in HAL_ADC_Init() 690 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_Init() 693 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init() 758 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init() [all …]

12 3 4 5 6 7 8 9 10 >>...75

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