Searched refs:SDMMC_ICR_DCRCFAILC_Pos (Results 1 – 25 of 108) sorted by relevance
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11510 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11511 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11488 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11489 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11733 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11734 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11711 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11712 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13225 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13226 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12584 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro12585 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12932 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro12933 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13152 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13153 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13839 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13840 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13546 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13547 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11731 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11732 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11786 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11787 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11502 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11503 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11956 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11957 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12774 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro12775 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
11864 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro11865 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12089 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro12090 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12938 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro12939 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13095 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13096 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13314 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13315 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
13163 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro13164 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
14509 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro14510 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
14169 #define SDMMC_ICR_DCRCFAILC_Pos (1U) macro14170 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
